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ar9300_xmit.c (250008) ar9300_xmit.c (278741)
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH

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578}
579
580/*
581 * Stop transmit on the specified queue
582 */
583HAL_BOOL
584ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout)
585{
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH

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578}
579
580/*
581 * Stop transmit on the specified queue
582 */
583HAL_BOOL
584ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout)
585{
586 struct ath_hal_9300 *ahp = AH9300(ah);
587
586 /*
588 /*
589 * If we call abort txdma instead, no need to stop RX.
590 * Otherwise, the RX logic might not be restarted properly.
591 */
592 ahp->ah_abort_txdma_norx = AH_FALSE;
593
594 /*
587 * Directly call abort. It is better, hardware-wise, to stop all
588 * queues at once than individual ones.
589 */
590 return ar9300_abort_tx_dma(ah);
591
592#if 0
593#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
594#define AH_TIME_QUANTUM 100 /* usec */

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793#undef AH_TIME_QUANTUM
794}
795
796/*
797 * Abort transmit on all queues
798 */
799#define AR9300_ABORT_LOOPS 1000
800#define AR9300_ABORT_WAIT 5
595 * Directly call abort. It is better, hardware-wise, to stop all
596 * queues at once than individual ones.
597 */
598 return ar9300_abort_tx_dma(ah);
599
600#if 0
601#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
602#define AH_TIME_QUANTUM 100 /* usec */

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801#undef AH_TIME_QUANTUM
802}
803
804/*
805 * Abort transmit on all queues
806 */
807#define AR9300_ABORT_LOOPS 1000
808#define AR9300_ABORT_WAIT 5
809#define NEXT_TBTT_NOW 10
801HAL_BOOL
802ar9300_abort_tx_dma(struct ath_hal *ah)
803{
810HAL_BOOL
811ar9300_abort_tx_dma(struct ath_hal *ah)
812{
813 struct ath_hal_9300 *ahp = AH9300(ah);
804 int i, q;
814 int i, q;
815 u_int32_t nexttbtt, nextdba, tsf_tbtt, tbtt, dba;
816 HAL_BOOL stopped;
817 HAL_BOOL status = AH_TRUE;
805
818
819 if (ahp->ah_abort_txdma_norx) {
820 /*
821 * First of all, make sure RX has been stopped
822 */
823 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) {
824 /* Need to stop RX DMA before reset otherwise chip might hang */
825 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */
826 ar9300_set_rx_filter(ah, 0);
827 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */
828 if (!stopped) {
829 /*
830 * During the transition from full sleep to reset,
831 * recv DMA regs are not available to be read
832 */
833 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
834 "%s[%d]: ar9300_stop_dma_receive failed\n", __func__, __LINE__);
835 //We still continue to stop TX dma
836 //return AH_FALSE;
837 }
838 } else {
839 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
840 "%s[%d]: Chip is already in full sleep\n", __func__, __LINE__);
841 }
842 }
843
806 /*
807 * set txd on all queues
808 */
809 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
810
811 /*
812 * set tx abort bits (also disable rx)
813 */
814 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
844 /*
845 * set txd on all queues
846 */
847 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
848
849 /*
850 * set tx abort bits (also disable rx)
851 */
852 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
815 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
816 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR));
853 /* Add a new receipe from K31 code */
854 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
855 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);
856 /* beacon Q flush */
857 nexttbtt = OS_REG_READ(ah, AR_NEXT_TBTT_TIMER);
858 nextdba = OS_REG_READ(ah, AR_NEXT_DMA_BEACON_ALERT);
859 //printk("%s[%d]:dba: %d, nt: %d \n", __func__, __LINE__, nextdba, nexttbtt);
860 tsf_tbtt = OS_REG_READ(ah, AR_TSF_L32);
861 tbtt = tsf_tbtt + NEXT_TBTT_NOW;
862 dba = tsf_tbtt;
863 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, dba);
864 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, tbtt);
817 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
818
865 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
866
819 /* Let TXE (all queues) clear before waiting on any pending frames */
820 for (i = 0; i < AR9300_ABORT_LOOPS; i++) {
821 if (OS_REG_READ(ah, AR_Q_TXE) == 0) {
867 /*
868 * Let TXE (all queues) clear before waiting for any pending frames
869 * This is needed before starting the RF_BUS GRANT sequence other wise causes kernel
870 * panic
871 */
872 for(i = 0; i < AR9300_ABORT_LOOPS; i++) {
873 if(OS_REG_READ(ah, AR_Q_TXE) == 0) {
822 break;
823 }
824 OS_DELAY(AR9300_ABORT_WAIT);
825 }
826 if (i == AR9300_ABORT_LOOPS) {
827 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n",
828 __func__, __LINE__);
829 }
830
831 /*
832 * wait on all tx queues
874 break;
875 }
876 OS_DELAY(AR9300_ABORT_WAIT);
877 }
878 if (i == AR9300_ABORT_LOOPS) {
879 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n",
880 __func__, __LINE__);
881 }
882
883 /*
884 * wait on all tx queues
885 * This need to be checked in the last to gain extra 50 usec. on avg.
886 * Currently checked first since we dont have a previous channel information currently.
887 * Which is needed to revert the rf changes.
833 */
888 */
834 for (q = 0; q < AR_NUM_QCU; q++) {
889 for (q = AR_NUM_QCU - 1; q >= 0; q--) {
835 for (i = 0; i < AR9300_ABORT_LOOPS; i++) {
890 for (i = 0; i < AR9300_ABORT_LOOPS; i++) {
836 if (!ar9300_num_tx_pending(ah, q)) {
891 if (!(ar9300_num_tx_pending(ah, q))) {
837 break;
838 }
839 OS_DELAY(AR9300_ABORT_WAIT);
840 }
841 if (i == AR9300_ABORT_LOOPS) {
892 break;
893 }
894 OS_DELAY(AR9300_ABORT_WAIT);
895 }
896 if (i == AR9300_ABORT_LOOPS) {
842 HALDEBUG(ah, HAL_DEBUG_TX,
843 "%s[%d] reached max wait on pending tx, q %d\n",
844 __func__, __LINE__, q);
845 return AH_FALSE;
897 status = AH_FALSE;
898 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
899 "ABORT LOOP finsihsed for Q: %d, num_pending: %d \n",
900 q, ar9300_num_tx_pending(ah, q));
901 goto exit;
846 }
847 }
848
902 }
903 }
904
905 /* Updating the beacon alert register with correct value */
906 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, nextdba);
907 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, nexttbtt);
908
909exit:
849 /*
850 * clear tx abort bits
851 */
852 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
910 /*
911 * clear tx abort bits
912 */
913 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
853 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
854 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR));
914 /* Added a new receipe from K31 code */
915 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
916 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);
855 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
856
857 /*
858 * clear txd
859 */
860 OS_REG_WRITE(ah, AR_Q_TXD, 0);
861
917 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
918
919 /*
920 * clear txd
921 */
922 OS_REG_WRITE(ah, AR_Q_TXD, 0);
923
862 return AH_TRUE;
924 ahp->ah_abort_txdma_norx = AH_TRUE;
925
926 return status;
863}
864
865/*
866 * Determine which tx queues need interrupt servicing.
867 */
868void
869ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs)
870{

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928
929/*
930 * Determine which tx queues need interrupt servicing.
931 */
932void
933ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs)
934{

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