1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
19#include "ah.h"
20#include "ah_desc.h"
21#include "ah_internal.h"
22
23#include "ar9300/ar9300.h"
24#include "ar9300/ar9300reg.h"
25#include "ar9300/ar9300phy.h"
26#include "ar9300/ar9300desc.h"
27
28#define TU_TO_USEC(_tu) ((_tu) << 10)
29#define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7)
30
31/*
32 * Update Tx FIFO trigger level.
33 *
34 * Set b_inc_trig_level to TRUE to increase the trigger level.
35 * Set b_inc_trig_level to FALSE to decrease the trigger level.
36 *
37 * Returns TRUE if the trigger level was updated
38 */
39HAL_BOOL
40ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
41{
42 struct ath_hal_9300 *ahp = AH9300(ah);
43 u_int32_t txcfg, cur_level, new_level;
44 HAL_INT omask;
45
46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD &&
47 b_inc_trig_level)
48 {
49 return AH_FALSE;
50 }
51
52 /*
53 * Disable interrupts while futzing with the fifo level.
54 */
55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0);
56
57 txcfg = OS_REG_READ(ah, AR_TXCFG);
58 cur_level = MS(txcfg, AR_FTRIG);
59 new_level = cur_level;
60
61 if (b_inc_trig_level) { /* increase the trigger level */
62 if (cur_level < MAX_TX_FIFO_THRESHOLD) {
63 new_level++;
64 }
65 } else if (cur_level > MIN_TX_FIFO_THRESHOLD) {
66 new_level--;
67 }
68
69 if (new_level != cur_level) {
70 /* Update the trigger level */
71 OS_REG_WRITE(ah,
72 AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG));
73 }
74
75 /* re-enable chip interrupts */
76 ar9300_set_interrupts(ah, omask, 0);
77
78 AH9300(ah)->ah_tx_trig_level = new_level;
79
80 return (new_level != cur_level);
81}
82
83/*
84 * Returns the value of Tx Trigger Level
85 */
86u_int16_t
87ar9300_get_tx_trig_level(struct ath_hal *ah)
88{
89 return (AH9300(ah)->ah_tx_trig_level);
90}
91
92/*
93 * Set the properties of the tx queue with the parameters
94 * from q_info.
95 */
96HAL_BOOL
97ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info)
98{
99 struct ath_hal_9300 *ahp = AH9300(ah);
100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
101
102 if (q >= p_cap->halTotalQueues) {
103 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
104 return AH_FALSE;
105 }
106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info);
107}
108
109/*
110 * Return the properties for the specified tx queue.
111 */
112HAL_BOOL
113ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info)
114{
115 struct ath_hal_9300 *ahp = AH9300(ah);
116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
117
118
119 if (q >= p_cap->halTotalQueues) {
120 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
121 return AH_FALSE;
122 }
123 return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]);
124}
125
126enum {
127 AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1,
128 AH_TX_QUEUE_MINUS_OFFSET_CAB = 2,
129 AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3,
130 AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4,
131};
132
133/*
134 * Allocate and initialize a tx DCU/QCU combination.
135 */
136int
137ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
138 const HAL_TXQ_INFO *q_info)
139{
140 struct ath_hal_9300 *ahp = AH9300(ah);
141 HAL_TX_QUEUE_INFO *qi;
142 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
143 int q;
144
145 /* XXX move queue assignment to driver */
146 switch (type) {
147 case HAL_TX_QUEUE_BEACON:
148 /* highest priority */
149 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_BEACON;
150 break;
151 case HAL_TX_QUEUE_CAB:
152 /* next highest priority */
153 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_CAB;
154 break;
155 case HAL_TX_QUEUE_UAPSD:
156 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD;
157 break;
158 case HAL_TX_QUEUE_PAPRD:
159 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
160 break;
161 case HAL_TX_QUEUE_DATA:
162 /*
163 * don't infringe on top 4 queues, reserved for:
164 * beacon, CAB, UAPSD, PAPRD
165 */
166 for (q = 0;
167 q < p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
168 q++)
169 {
170 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) {
171 break;
172 }
173 }
174 if (q == p_cap->halTotalQueues - 3) {
175 HALDEBUG(ah, HAL_DEBUG_QUEUE,
176 "%s: no available tx queue\n", __func__);
177 return -1;
178 }
179 break;
180 default:
181 HALDEBUG(ah, HAL_DEBUG_QUEUE,
182 "%s: bad tx queue type %u\n", __func__, type);
183 return -1;
184 }
185
186 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q);
187
188 qi = &ahp->ah_txq[q];
189 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
190 HALDEBUG(ah, HAL_DEBUG_QUEUE,
191 "%s: tx queue %u already active\n", __func__, q);
192 return -1;
193 }
194
195 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
196 qi->tqi_type = type;
197
198 if (q_info == AH_NULL) {
199 /* by default enable OK+ERR+DESC+URN interrupts */
200 qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
201 | HAL_TXQ_TXERRINT_ENABLE
202 | HAL_TXQ_TXDESCINT_ENABLE
203 | HAL_TXQ_TXURNINT_ENABLE;
204 qi->tqi_aifs = INIT_AIFS;
205 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
206 qi->tqi_cwmax = INIT_CWMAX;
207 qi->tqi_shretry = INIT_SH_RETRY;
208 qi->tqi_lgretry = INIT_LG_RETRY;
209 qi->tqi_physCompBuf = 0;
210 } else {
211 qi->tqi_physCompBuf = q_info->tqi_compBuf;
212 (void) ar9300_set_tx_queue_props(ah, q, q_info);
213 }
214 /* NB: must be followed by ar9300_reset_tx_queue */
215 return q;
216}
217
218/*
219 * Update the h/w interrupt registers to reflect a tx q's configuration.
220 */
221static void
222set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
223{
224 struct ath_hal_9300 *ahp = AH9300(ah);
225
226 HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
227 "%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n",
228 __func__,
229 ahp->ah_tx_ok_interrupt_mask,
230 ahp->ah_tx_err_interrupt_mask,
231 ahp->ah_tx_eol_interrupt_mask,
232 ahp->ah_tx_urn_interrupt_mask);
233
234 OS_REG_WRITE(ah, AR_IMR_S0,
235 SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK));
236 OS_REG_WRITE(ah, AR_IMR_S1,
237 SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR)
238 | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
239 OS_REG_RMW_FIELD(ah,
240 AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask);
241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
242}
243
244/*
245 * Free a tx DCU/QCU combination.
246 */
247HAL_BOOL
248ar9300_release_tx_queue(struct ath_hal *ah, u_int q)
249{
250 struct ath_hal_9300 *ahp = AH9300(ah);
251 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
252 HAL_TX_QUEUE_INFO *qi;
253
254 if (q >= p_cap->halTotalQueues) {
255 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
256 return AH_FALSE;
257 }
258
259 qi = &ahp->ah_txq[q];
260 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
261 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
262 return AH_FALSE;
263 }
264
265 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q);
266
267 qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
268 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
269 ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
270 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
271 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
272 set_tx_q_interrupts(ah, qi);
273
274 return AH_TRUE;
275}
276
277/*
278 * Set the retry, aifs, cwmin/max, ready_time regs for specified queue
279 * Assumes:
280 * phw_channel has been set to point to the current channel
281 */
282HAL_BOOL
283ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
284{
285 struct ath_hal_9300 *ahp = AH9300(ah);
286// struct ath_hal_private *ap = AH_PRIVATE(ah);
287 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
288 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
289 HAL_TX_QUEUE_INFO *qi;
290 u_int32_t cw_min, chan_cw_min, value;
291
292 if (q >= p_cap->halTotalQueues) {
293 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
294 return AH_FALSE;
295 }
296
297 qi = &ahp->ah_txq[q];
298 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
299 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
300 return AH_TRUE; /* XXX??? */
301 }
302
303 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q);
304
305 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
306 /*
307 * Select cwmin according to channel type.
308 * NB: chan can be NULL during attach
309 */
310 if (chan && IEEE80211_IS_CHAN_B(chan)) {
311 chan_cw_min = INIT_CWMIN_11B;
312 } else {
313 chan_cw_min = INIT_CWMIN;
314 }
315 /* make sure that the CWmin is of the form (2^n - 1) */
316 for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {}
317 } else {
318 cw_min = qi->tqi_cwmin;
319 }
320
321 /* set cw_min/Max and AIFS values */
322 if (q > 3 || (!AH9300(ah)->ah_fccaifs))
323 /* values should not be overwritten if domain is FCC and manual rate
324 less than 24Mb is set, this check is making sure this */
325 {
326 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN)
327 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
328 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
329 }
330
331 /* Set retry limit values */
332 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
333 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
334 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
335 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
336
337 /* enable early termination on the QCU */
338 OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
339
340 /* enable DCU to wait for next fragment from QCU */
341 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) {
342 /* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff
343 * threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */
344 OS_REG_WRITE(ah, AR_DMISC(q),
345 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
346 } else {
347 OS_REG_WRITE(ah, AR_DMISC(q),
348 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
349 }
350
351 /* multiqueue support */
352 if (qi->tqi_cbrPeriod) {
353 OS_REG_WRITE(ah,
354 AR_QCBRCFG(q),
355 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
356 SM(qi->tqi_cbrOverflowLimit,
357 AR_Q_CBRCFG_OVF_THRESH));
358 OS_REG_WRITE(ah, AR_QMISC(q),
359 OS_REG_READ(ah, AR_QMISC(q)) |
360 AR_Q_MISC_FSP_CBR |
361 (qi->tqi_cbrOverflowLimit ?
362 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
363 }
364
365 if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
366 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
367 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
368 AR_Q_RDYTIMECFG_EN);
369 }
370
371 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
372 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
373
374 if (qi->tqi_burstTime &&
375 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
376 {
377 OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) |
378 AR_Q_MISC_RDYTIME_EXP_POLICY);
379 }
380
381 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
382 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
383 AR_D_MISC_POST_FR_BKOFF_DIS);
384 }
385
386 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
387 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
388 AR_D_MISC_FRAG_BKOFF_EN);
389 }
390
391 switch (qi->tqi_type) {
392 case HAL_TX_QUEUE_BEACON: /* beacon frames */
393 OS_REG_WRITE(ah, AR_QMISC(q),
394 OS_REG_READ(ah, AR_QMISC(q))
395 | AR_Q_MISC_FSP_DBA_GATED
396 | AR_Q_MISC_BEACON_USE
397 | AR_Q_MISC_CBR_INCR_DIS1);
398
399 OS_REG_WRITE(ah, AR_DMISC(q),
400 OS_REG_READ(ah, AR_DMISC(q))
401 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
402 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
403 | AR_D_MISC_BEACON_USE
404 | AR_D_MISC_POST_FR_BKOFF_DIS);
405 /* XXX cwmin and cwmax should be 0 for beacon queue */
406 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) {
407 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
408 | SM(0, AR_D_LCL_IFS_CWMAX)
409 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
410 }
411 break;
412 case HAL_TX_QUEUE_CAB: /* CAB frames */
413 /*
414 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY,
415 * bug #6079. There is an issue with the CAB Queue
416 * not properly refreshing the Tx descriptor if
417 * the TXE clear setting is used.
418 */
419 OS_REG_WRITE(ah, AR_QMISC(q),
420 OS_REG_READ(ah, AR_QMISC(q))
421 | AR_Q_MISC_FSP_DBA_GATED
422 | AR_Q_MISC_CBR_INCR_DIS1
423 | AR_Q_MISC_CBR_INCR_DIS0);
424
425 value = TU_TO_USEC(qi->tqi_readyTime)
426 - (ah->ah_config.ah_sw_beacon_response_time
427 - ah->ah_config.ah_dma_beacon_response_time)
428 - ah->ah_config.ah_additional_swba_backoff;
429 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);
430
431 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
432 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
433 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
434 break;
435 case HAL_TX_QUEUE_PSPOLL:
436 /*
437 * We may configure ps_poll QCU to be TIM-gated in the
438 * future; TIM_GATED bit is not enabled currently because
439 * of a hardware problem in Oahu that overshoots the TIM
440 * bitmap in beacon and may find matching associd bit in
441 * non-TIM elements and send PS-poll PS poll processing
442 * will be done in software
443 */
444 OS_REG_WRITE(ah, AR_QMISC(q),
445 OS_REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
446 break;
447 case HAL_TX_QUEUE_UAPSD:
448 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
449 | AR_D_MISC_POST_FR_BKOFF_DIS);
450 break;
451 default: /* NB: silence compiler */
452 break;
453 }
454
455#ifndef AH_DISABLE_WME
456 /*
457 * Yes, this is a hack and not the right way to do it, but
458 * it does get the lockout bits and backoff set for the
459 * high-pri WME queues for testing. We need to either extend
460 * the meaning of queue_info->mode, or create something like
461 * queue_info->dcumode.
462 */
463 if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
464 OS_REG_WRITE(ah, AR_DMISC(q),
465 OS_REG_READ(ah, AR_DMISC(q)) |
466 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
467 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
468 AR_D_MISC_POST_FR_BKOFF_DIS);
469 }
470#endif
471
472 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
473
474 /*
475 * Always update the secondary interrupt mask registers - this
476 * could be a new queue getting enabled in a running system or
477 * hw getting re-initialized during a reset!
478 *
479 * Since we don't differentiate between tx interrupts corresponding
480 * to individual queues - secondary tx mask regs are always unmasked;
481 * tx interrupts are enabled/disabled for all queues collectively
482 * using the primary mask reg
483 */
484 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) {
485 ahp->ah_tx_ok_interrupt_mask |= (1 << q);
486 } else {
487 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
488 }
489 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) {
490 ahp->ah_tx_err_interrupt_mask |= (1 << q);
491 } else {
492 ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
493 }
494 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) {
495 ahp->ah_tx_eol_interrupt_mask |= (1 << q);
496 } else {
497 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
498 }
499 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) {
500 ahp->ah_tx_urn_interrupt_mask |= (1 << q);
501 } else {
502 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
503 }
504 set_tx_q_interrupts(ah, qi);
505
506 return AH_TRUE;
507}
508
509/*
510 * Get the TXDP for the specified queue
511 */
512u_int32_t
513ar9300_get_tx_dp(struct ath_hal *ah, u_int q)
514{
515 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
516 return OS_REG_READ(ah, AR_QTXDP(q));
517}
518
519/*
520 * Set the tx_dp for the specified queue
521 */
522HAL_BOOL
523ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp)
524{
525 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
526 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
527 HALASSERT(txdp != 0);
528
529 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
530
531 return AH_TRUE;
532}
533
534/*
535 * Transmit Enable is read-only now
536 */
537HAL_BOOL
538ar9300_start_tx_dma(struct ath_hal *ah, u_int q)
539{
540 return AH_TRUE;
541}
542
543/*
544 * Return the number of pending frames or 0 if the specified
545 * queue is stopped.
546 */
547u_int32_t
548ar9300_num_tx_pending(struct ath_hal *ah, u_int q)
549{
550 u_int32_t npend;
551
552 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
553
554 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
555 if (npend == 0) {
556 /*
557 * Pending frame count (PFC) can momentarily go to zero
558 * while TXE remains asserted. In other words a PFC of
559 * zero is not sufficient to say that the queue has stopped.
560 */
561 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) {
562 npend = 1; /* arbitrarily return 1 */
563 }
564 }
565#ifdef DEBUG
566 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
567 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
568 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n");
569 /* Clear the ready_time shutdown status bits */
570 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
571 }
572 }
573#endif
574 HALASSERT((npend == 0) ||
575 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE));
576
577 return npend;
578}
579
580/*
581 * Stop transmit on the specified queue
582 */
583HAL_BOOL
584ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout)
585{
586 struct ath_hal_9300 *ahp = AH9300(ah);
587
588 /*
589 * If we call abort txdma instead, no need to stop RX.
590 * Otherwise, the RX logic might not be restarted properly.
591 */
592 ahp->ah_abort_txdma_norx = AH_FALSE;
593
594 /*
595 * Directly call abort. It is better, hardware-wise, to stop all
596 * queues at once than individual ones.
597 */
598 return ar9300_abort_tx_dma(ah);
599
600#if 0
601#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
602#define AH_TIME_QUANTUM 100 /* usec */
603 u_int wait;
604
605 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
606
607 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
608
609 if (timeout == 0) {
610 timeout = AH_TX_STOP_DMA_TIMEOUT;
611 }
612
613 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
614
615 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
616 if (ar9300_num_tx_pending(ah, q) == 0) {
617 break;
618 }
619 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */
620 }
621
622#ifdef AH_DEBUG
623 if (wait == 0) {
624 HALDEBUG(ah, HAL_DEBUG_QUEUE,
625 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
626 HALDEBUG(ah, HAL_DEBUG_QUEUE,
627 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n",
628 __func__,
629 OS_REG_READ(ah, AR_QSTS(q)),
630 OS_REG_READ(ah, AR_Q_TXE),
631 OS_REG_READ(ah, AR_Q_TXD),
632 OS_REG_READ(ah, AR_QCBRCFG(q)));
633 HALDEBUG(ah, HAL_DEBUG_QUEUE,
634 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
635 __func__,
636 OS_REG_READ(ah, AR_QMISC(q)),
637 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
638 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
639 }
640#endif /* AH_DEBUG */
641
642 /* 2413+ and up can kill packets at the PCU level */
643 if (ar9300_num_tx_pending(ah, q)) {
644 u_int32_t tsf_low, j;
645
646 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
647 __func__, ar9300_num_tx_pending(ah, q), q);
648
649 /* Kill last PCU Tx Frame */
650 /* TODO - save off and restore current values of Q1/Q2? */
651 for (j = 0; j < 2; j++) {
652 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
653 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
654 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
655 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
656 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
657
658 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
659 break;
660 }
661
662 HALDEBUG(ah, HAL_DEBUG_QUEUE,
663 "%s: TSF have moved while trying to set "
664 "quiet time TSF: 0x%08x\n",
665 __func__, tsf_low);
666 /* TSF shouldn't count twice or reg access is taking forever */
667 HALASSERT(j < 1);
668 }
669
670 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
671
672 /* Allow the quiet mechanism to do its work */
673 OS_DELAY(200);
674 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
675
676 /* Verify all transmit is dead */
677 wait = timeout / AH_TIME_QUANTUM;
678 while (ar9300_num_tx_pending(ah, q)) {
679 if ((--wait) == 0) {
680 HALDEBUG(ah, HAL_DEBUG_TX,
681 "%s: Failed to stop Tx DMA in %d msec "
682 "after killing last frame\n",
683 __func__, timeout / 1000);
684 break;
685 }
686 OS_DELAY(AH_TIME_QUANTUM);
687 }
688
689 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
690 }
691
692 OS_REG_WRITE(ah, AR_Q_TXD, 0);
693 return (wait != 0);
694
695#undef AH_TX_STOP_DMA_TIMEOUT
696#undef AH_TIME_QUANTUM
697#endif
698}
699
700/*
701 * Really Stop transmit on the specified queue
702 */
703HAL_BOOL
704ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout)
705{
706#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
707#define AH_TIME_QUANTUM 100 /* usec */
708 u_int wait;
709
710 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
711
712 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
713
714 if (timeout == 0) {
715 timeout = AH_TX_STOP_DMA_TIMEOUT;
716 }
717
718 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
719
720 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
721 if (ar9300_num_tx_pending(ah, q) == 0) {
722 break;
723 }
724 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */
725 }
726
727#ifdef AH_DEBUG
728 if (wait == 0) {
729 HALDEBUG(ah, HAL_DEBUG_QUEUE,
730 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
731 HALDEBUG(ah, HAL_DEBUG_QUEUE,
732 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n",
733 __func__,
734 OS_REG_READ(ah, AR_QSTS(q)),
735 OS_REG_READ(ah, AR_Q_TXE),
736 OS_REG_READ(ah, AR_Q_TXD),
737 OS_REG_READ(ah, AR_QCBRCFG(q)));
738 HALDEBUG(ah, HAL_DEBUG_QUEUE,
739 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
740 __func__,
741 OS_REG_READ(ah, AR_QMISC(q)),
742 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
743 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
744 }
745#endif /* AH_DEBUG */
746
747 /* 2413+ and up can kill packets at the PCU level */
748 if (ar9300_num_tx_pending(ah, q)) {
749 u_int32_t tsf_low, j;
750
751 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
752 __func__, ar9300_num_tx_pending(ah, q), q);
753
754 /* Kill last PCU Tx Frame */
755 /* TODO - save off and restore current values of Q1/Q2? */
756 for (j = 0; j < 2; j++) {
757 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
758 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
759 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
760 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
761 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
762
763 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
764 break;
765 }
766
767 HALDEBUG(ah, HAL_DEBUG_QUEUE,
768 "%s: TSF have moved while trying to set "
769 "quiet time TSF: 0x%08x\n",
770 __func__, tsf_low);
771 /* TSF shouldn't count twice or reg access is taking forever */
772 HALASSERT(j < 1);
773 }
774
775 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
776
777 /* Allow the quiet mechanism to do its work */
778 OS_DELAY(200);
779 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
780
781 /* Verify all transmit is dead */
782 wait = timeout / AH_TIME_QUANTUM;
783 while (ar9300_num_tx_pending(ah, q)) {
784 if ((--wait) == 0) {
785 HALDEBUG(ah, HAL_DEBUG_TX,
786 "%s: Failed to stop Tx DMA in %d msec "
787 "after killing last frame\n",
788 __func__, timeout / 1000);
789 break;
790 }
791 OS_DELAY(AH_TIME_QUANTUM);
792 }
793
794 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
795 }
796
797 OS_REG_WRITE(ah, AR_Q_TXD, 0);
798 return (wait != 0);
799
800#undef AH_TX_STOP_DMA_TIMEOUT
801#undef AH_TIME_QUANTUM
802}
803
804/*
805 * Abort transmit on all queues
806 */
807#define AR9300_ABORT_LOOPS 1000
808#define AR9300_ABORT_WAIT 5
809#define NEXT_TBTT_NOW 10
810HAL_BOOL
811ar9300_abort_tx_dma(struct ath_hal *ah)
812{
813 struct ath_hal_9300 *ahp = AH9300(ah);
814 int i, q;
815 u_int32_t nexttbtt, nextdba, tsf_tbtt, tbtt, dba;
816 HAL_BOOL stopped;
817 HAL_BOOL status = AH_TRUE;
818
819 if (ahp->ah_abort_txdma_norx) {
820 /*
821 * First of all, make sure RX has been stopped
822 */
823 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) {
824 /* Need to stop RX DMA before reset otherwise chip might hang */
825 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */
826 ar9300_set_rx_filter(ah, 0);
827 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */
828 if (!stopped) {
829 /*
830 * During the transition from full sleep to reset,
831 * recv DMA regs are not available to be read
832 */
833 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
834 "%s[%d]: ar9300_stop_dma_receive failed\n", __func__, __LINE__);
835 //We still continue to stop TX dma
836 //return AH_FALSE;
837 }
838 } else {
839 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
840 "%s[%d]: Chip is already in full sleep\n", __func__, __LINE__);
841 }
842 }
843
844 /*
845 * set txd on all queues
846 */
847 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
848
849 /*
850 * set tx abort bits (also disable rx)
851 */
852 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
853 /* Add a new receipe from K31 code */
854 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
855 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);
856 /* beacon Q flush */
857 nexttbtt = OS_REG_READ(ah, AR_NEXT_TBTT_TIMER);
858 nextdba = OS_REG_READ(ah, AR_NEXT_DMA_BEACON_ALERT);
859 //printk("%s[%d]:dba: %d, nt: %d \n", __func__, __LINE__, nextdba, nexttbtt);
860 tsf_tbtt = OS_REG_READ(ah, AR_TSF_L32);
861 tbtt = tsf_tbtt + NEXT_TBTT_NOW;
862 dba = tsf_tbtt;
863 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, dba);
864 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, tbtt);
865 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
866
867 /*
868 * Let TXE (all queues) clear before waiting for any pending frames
869 * This is needed before starting the RF_BUS GRANT sequence other wise causes kernel
870 * panic
871 */
872 for(i = 0; i < AR9300_ABORT_LOOPS; i++) {
873 if(OS_REG_READ(ah, AR_Q_TXE) == 0) {
874 break;
875 }
876 OS_DELAY(AR9300_ABORT_WAIT);
877 }
878 if (i == AR9300_ABORT_LOOPS) {
879 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n",
880 __func__, __LINE__);
881 }
882
883 /*
884 * wait on all tx queues
885 * This need to be checked in the last to gain extra 50 usec. on avg.
886 * Currently checked first since we dont have a previous channel information currently.
887 * Which is needed to revert the rf changes.
888 */
889 for (q = AR_NUM_QCU - 1; q >= 0; q--) {
890 for (i = 0; i < AR9300_ABORT_LOOPS; i++) {
891 if (!(ar9300_num_tx_pending(ah, q))) {
892 break;
893 }
894 OS_DELAY(AR9300_ABORT_WAIT);
895 }
896 if (i == AR9300_ABORT_LOOPS) {
897 status = AH_FALSE;
898 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
899 "ABORT LOOP finsihsed for Q: %d, num_pending: %d \n",
900 q, ar9300_num_tx_pending(ah, q));
901 goto exit;
902 }
903 }
904
905 /* Updating the beacon alert register with correct value */
906 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, nextdba);
907 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, nexttbtt);
908
909exit:
910 /*
911 * clear tx abort bits
912 */
913 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
914 /* Added a new receipe from K31 code */
915 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
916 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);
917 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
918
919 /*
920 * clear txd
921 */
922 OS_REG_WRITE(ah, AR_Q_TXD, 0);
923
924 ahp->ah_abort_txdma_norx = AH_TRUE;
925
926 return status;
927}
928
929/*
930 * Determine which tx queues need interrupt servicing.
931 */
932void
933ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs)
934{
935 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
936 "ar9300_get_tx_intr_queue: Should not be called\n");
937#if 0
938 struct ath_hal_9300 *ahp = AH9300(ah);
939 *txqs &= ahp->ah_intr_txqs;
940 ahp->ah_intr_txqs &= ~(*txqs);
941#endif
942}
943
944void
945ar9300_reset_tx_status_ring(struct ath_hal *ah)
946{
947 struct ath_hal_9300 *ahp = AH9300(ah);
948
949 ahp->ts_tail = 0;
950
951 /* Zero out the status descriptors */
952 OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs));
953 HALDEBUG(ah, HAL_DEBUG_QUEUE,
954 "%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__,
955 ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size);
956
957 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start);
958 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end);
959}
960
961void
962ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start,
963 u_int32_t ts_paddr_start, u_int16_t size)
964{
965 struct ath_hal_9300 *ahp = AH9300(ah);
966
967 ahp->ts_paddr_start = ts_paddr_start;
968 ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs));
969 ahp->ts_size = size;
970 ahp->ts_ring = (struct ar9300_txs *)ts_start;
971
972 ar9300_reset_tx_status_ring(ah);
973}
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
19#include "ah.h"
20#include "ah_desc.h"
21#include "ah_internal.h"
22
23#include "ar9300/ar9300.h"
24#include "ar9300/ar9300reg.h"
25#include "ar9300/ar9300phy.h"
26#include "ar9300/ar9300desc.h"
27
28#define TU_TO_USEC(_tu) ((_tu) << 10)
29#define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7)
30
31/*
32 * Update Tx FIFO trigger level.
33 *
34 * Set b_inc_trig_level to TRUE to increase the trigger level.
35 * Set b_inc_trig_level to FALSE to decrease the trigger level.
36 *
37 * Returns TRUE if the trigger level was updated
38 */
39HAL_BOOL
40ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
41{
42 struct ath_hal_9300 *ahp = AH9300(ah);
43 u_int32_t txcfg, cur_level, new_level;
44 HAL_INT omask;
45
46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD &&
47 b_inc_trig_level)
48 {
49 return AH_FALSE;
50 }
51
52 /*
53 * Disable interrupts while futzing with the fifo level.
54 */
55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0);
56
57 txcfg = OS_REG_READ(ah, AR_TXCFG);
58 cur_level = MS(txcfg, AR_FTRIG);
59 new_level = cur_level;
60
61 if (b_inc_trig_level) { /* increase the trigger level */
62 if (cur_level < MAX_TX_FIFO_THRESHOLD) {
63 new_level++;
64 }
65 } else if (cur_level > MIN_TX_FIFO_THRESHOLD) {
66 new_level--;
67 }
68
69 if (new_level != cur_level) {
70 /* Update the trigger level */
71 OS_REG_WRITE(ah,
72 AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG));
73 }
74
75 /* re-enable chip interrupts */
76 ar9300_set_interrupts(ah, omask, 0);
77
78 AH9300(ah)->ah_tx_trig_level = new_level;
79
80 return (new_level != cur_level);
81}
82
83/*
84 * Returns the value of Tx Trigger Level
85 */
86u_int16_t
87ar9300_get_tx_trig_level(struct ath_hal *ah)
88{
89 return (AH9300(ah)->ah_tx_trig_level);
90}
91
92/*
93 * Set the properties of the tx queue with the parameters
94 * from q_info.
95 */
96HAL_BOOL
97ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info)
98{
99 struct ath_hal_9300 *ahp = AH9300(ah);
100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
101
102 if (q >= p_cap->halTotalQueues) {
103 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
104 return AH_FALSE;
105 }
106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info);
107}
108
109/*
110 * Return the properties for the specified tx queue.
111 */
112HAL_BOOL
113ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info)
114{
115 struct ath_hal_9300 *ahp = AH9300(ah);
116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
117
118
119 if (q >= p_cap->halTotalQueues) {
120 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
121 return AH_FALSE;
122 }
123 return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]);
124}
125
126enum {
127 AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1,
128 AH_TX_QUEUE_MINUS_OFFSET_CAB = 2,
129 AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3,
130 AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4,
131};
132
133/*
134 * Allocate and initialize a tx DCU/QCU combination.
135 */
136int
137ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
138 const HAL_TXQ_INFO *q_info)
139{
140 struct ath_hal_9300 *ahp = AH9300(ah);
141 HAL_TX_QUEUE_INFO *qi;
142 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
143 int q;
144
145 /* XXX move queue assignment to driver */
146 switch (type) {
147 case HAL_TX_QUEUE_BEACON:
148 /* highest priority */
149 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_BEACON;
150 break;
151 case HAL_TX_QUEUE_CAB:
152 /* next highest priority */
153 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_CAB;
154 break;
155 case HAL_TX_QUEUE_UAPSD:
156 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD;
157 break;
158 case HAL_TX_QUEUE_PAPRD:
159 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
160 break;
161 case HAL_TX_QUEUE_DATA:
162 /*
163 * don't infringe on top 4 queues, reserved for:
164 * beacon, CAB, UAPSD, PAPRD
165 */
166 for (q = 0;
167 q < p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
168 q++)
169 {
170 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) {
171 break;
172 }
173 }
174 if (q == p_cap->halTotalQueues - 3) {
175 HALDEBUG(ah, HAL_DEBUG_QUEUE,
176 "%s: no available tx queue\n", __func__);
177 return -1;
178 }
179 break;
180 default:
181 HALDEBUG(ah, HAL_DEBUG_QUEUE,
182 "%s: bad tx queue type %u\n", __func__, type);
183 return -1;
184 }
185
186 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q);
187
188 qi = &ahp->ah_txq[q];
189 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
190 HALDEBUG(ah, HAL_DEBUG_QUEUE,
191 "%s: tx queue %u already active\n", __func__, q);
192 return -1;
193 }
194
195 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
196 qi->tqi_type = type;
197
198 if (q_info == AH_NULL) {
199 /* by default enable OK+ERR+DESC+URN interrupts */
200 qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
201 | HAL_TXQ_TXERRINT_ENABLE
202 | HAL_TXQ_TXDESCINT_ENABLE
203 | HAL_TXQ_TXURNINT_ENABLE;
204 qi->tqi_aifs = INIT_AIFS;
205 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
206 qi->tqi_cwmax = INIT_CWMAX;
207 qi->tqi_shretry = INIT_SH_RETRY;
208 qi->tqi_lgretry = INIT_LG_RETRY;
209 qi->tqi_physCompBuf = 0;
210 } else {
211 qi->tqi_physCompBuf = q_info->tqi_compBuf;
212 (void) ar9300_set_tx_queue_props(ah, q, q_info);
213 }
214 /* NB: must be followed by ar9300_reset_tx_queue */
215 return q;
216}
217
218/*
219 * Update the h/w interrupt registers to reflect a tx q's configuration.
220 */
221static void
222set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
223{
224 struct ath_hal_9300 *ahp = AH9300(ah);
225
226 HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
227 "%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n",
228 __func__,
229 ahp->ah_tx_ok_interrupt_mask,
230 ahp->ah_tx_err_interrupt_mask,
231 ahp->ah_tx_eol_interrupt_mask,
232 ahp->ah_tx_urn_interrupt_mask);
233
234 OS_REG_WRITE(ah, AR_IMR_S0,
235 SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK));
236 OS_REG_WRITE(ah, AR_IMR_S1,
237 SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR)
238 | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
239 OS_REG_RMW_FIELD(ah,
240 AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask);
241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
242}
243
244/*
245 * Free a tx DCU/QCU combination.
246 */
247HAL_BOOL
248ar9300_release_tx_queue(struct ath_hal *ah, u_int q)
249{
250 struct ath_hal_9300 *ahp = AH9300(ah);
251 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
252 HAL_TX_QUEUE_INFO *qi;
253
254 if (q >= p_cap->halTotalQueues) {
255 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
256 return AH_FALSE;
257 }
258
259 qi = &ahp->ah_txq[q];
260 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
261 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
262 return AH_FALSE;
263 }
264
265 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q);
266
267 qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
268 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
269 ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
270 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
271 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
272 set_tx_q_interrupts(ah, qi);
273
274 return AH_TRUE;
275}
276
277/*
278 * Set the retry, aifs, cwmin/max, ready_time regs for specified queue
279 * Assumes:
280 * phw_channel has been set to point to the current channel
281 */
282HAL_BOOL
283ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
284{
285 struct ath_hal_9300 *ahp = AH9300(ah);
286// struct ath_hal_private *ap = AH_PRIVATE(ah);
287 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
288 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
289 HAL_TX_QUEUE_INFO *qi;
290 u_int32_t cw_min, chan_cw_min, value;
291
292 if (q >= p_cap->halTotalQueues) {
293 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
294 return AH_FALSE;
295 }
296
297 qi = &ahp->ah_txq[q];
298 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
299 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
300 return AH_TRUE; /* XXX??? */
301 }
302
303 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q);
304
305 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
306 /*
307 * Select cwmin according to channel type.
308 * NB: chan can be NULL during attach
309 */
310 if (chan && IEEE80211_IS_CHAN_B(chan)) {
311 chan_cw_min = INIT_CWMIN_11B;
312 } else {
313 chan_cw_min = INIT_CWMIN;
314 }
315 /* make sure that the CWmin is of the form (2^n - 1) */
316 for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {}
317 } else {
318 cw_min = qi->tqi_cwmin;
319 }
320
321 /* set cw_min/Max and AIFS values */
322 if (q > 3 || (!AH9300(ah)->ah_fccaifs))
323 /* values should not be overwritten if domain is FCC and manual rate
324 less than 24Mb is set, this check is making sure this */
325 {
326 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN)
327 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
328 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
329 }
330
331 /* Set retry limit values */
332 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
333 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
334 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
335 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
336
337 /* enable early termination on the QCU */
338 OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
339
340 /* enable DCU to wait for next fragment from QCU */
341 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) {
342 /* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff
343 * threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */
344 OS_REG_WRITE(ah, AR_DMISC(q),
345 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
346 } else {
347 OS_REG_WRITE(ah, AR_DMISC(q),
348 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
349 }
350
351 /* multiqueue support */
352 if (qi->tqi_cbrPeriod) {
353 OS_REG_WRITE(ah,
354 AR_QCBRCFG(q),
355 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
356 SM(qi->tqi_cbrOverflowLimit,
357 AR_Q_CBRCFG_OVF_THRESH));
358 OS_REG_WRITE(ah, AR_QMISC(q),
359 OS_REG_READ(ah, AR_QMISC(q)) |
360 AR_Q_MISC_FSP_CBR |
361 (qi->tqi_cbrOverflowLimit ?
362 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
363 }
364
365 if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
366 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
367 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
368 AR_Q_RDYTIMECFG_EN);
369 }
370
371 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
372 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
373
374 if (qi->tqi_burstTime &&
375 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
376 {
377 OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) |
378 AR_Q_MISC_RDYTIME_EXP_POLICY);
379 }
380
381 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
382 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
383 AR_D_MISC_POST_FR_BKOFF_DIS);
384 }
385
386 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
387 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
388 AR_D_MISC_FRAG_BKOFF_EN);
389 }
390
391 switch (qi->tqi_type) {
392 case HAL_TX_QUEUE_BEACON: /* beacon frames */
393 OS_REG_WRITE(ah, AR_QMISC(q),
394 OS_REG_READ(ah, AR_QMISC(q))
395 | AR_Q_MISC_FSP_DBA_GATED
396 | AR_Q_MISC_BEACON_USE
397 | AR_Q_MISC_CBR_INCR_DIS1);
398
399 OS_REG_WRITE(ah, AR_DMISC(q),
400 OS_REG_READ(ah, AR_DMISC(q))
401 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
402 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
403 | AR_D_MISC_BEACON_USE
404 | AR_D_MISC_POST_FR_BKOFF_DIS);
405 /* XXX cwmin and cwmax should be 0 for beacon queue */
406 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) {
407 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
408 | SM(0, AR_D_LCL_IFS_CWMAX)
409 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
410 }
411 break;
412 case HAL_TX_QUEUE_CAB: /* CAB frames */
413 /*
414 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY,
415 * bug #6079. There is an issue with the CAB Queue
416 * not properly refreshing the Tx descriptor if
417 * the TXE clear setting is used.
418 */
419 OS_REG_WRITE(ah, AR_QMISC(q),
420 OS_REG_READ(ah, AR_QMISC(q))
421 | AR_Q_MISC_FSP_DBA_GATED
422 | AR_Q_MISC_CBR_INCR_DIS1
423 | AR_Q_MISC_CBR_INCR_DIS0);
424
425 value = TU_TO_USEC(qi->tqi_readyTime)
426 - (ah->ah_config.ah_sw_beacon_response_time
427 - ah->ah_config.ah_dma_beacon_response_time)
428 - ah->ah_config.ah_additional_swba_backoff;
429 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);
430
431 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
432 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
433 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
434 break;
435 case HAL_TX_QUEUE_PSPOLL:
436 /*
437 * We may configure ps_poll QCU to be TIM-gated in the
438 * future; TIM_GATED bit is not enabled currently because
439 * of a hardware problem in Oahu that overshoots the TIM
440 * bitmap in beacon and may find matching associd bit in
441 * non-TIM elements and send PS-poll PS poll processing
442 * will be done in software
443 */
444 OS_REG_WRITE(ah, AR_QMISC(q),
445 OS_REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
446 break;
447 case HAL_TX_QUEUE_UAPSD:
448 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
449 | AR_D_MISC_POST_FR_BKOFF_DIS);
450 break;
451 default: /* NB: silence compiler */
452 break;
453 }
454
455#ifndef AH_DISABLE_WME
456 /*
457 * Yes, this is a hack and not the right way to do it, but
458 * it does get the lockout bits and backoff set for the
459 * high-pri WME queues for testing. We need to either extend
460 * the meaning of queue_info->mode, or create something like
461 * queue_info->dcumode.
462 */
463 if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
464 OS_REG_WRITE(ah, AR_DMISC(q),
465 OS_REG_READ(ah, AR_DMISC(q)) |
466 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
467 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
468 AR_D_MISC_POST_FR_BKOFF_DIS);
469 }
470#endif
471
472 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
473
474 /*
475 * Always update the secondary interrupt mask registers - this
476 * could be a new queue getting enabled in a running system or
477 * hw getting re-initialized during a reset!
478 *
479 * Since we don't differentiate between tx interrupts corresponding
480 * to individual queues - secondary tx mask regs are always unmasked;
481 * tx interrupts are enabled/disabled for all queues collectively
482 * using the primary mask reg
483 */
484 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) {
485 ahp->ah_tx_ok_interrupt_mask |= (1 << q);
486 } else {
487 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
488 }
489 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) {
490 ahp->ah_tx_err_interrupt_mask |= (1 << q);
491 } else {
492 ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
493 }
494 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) {
495 ahp->ah_tx_eol_interrupt_mask |= (1 << q);
496 } else {
497 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
498 }
499 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) {
500 ahp->ah_tx_urn_interrupt_mask |= (1 << q);
501 } else {
502 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
503 }
504 set_tx_q_interrupts(ah, qi);
505
506 return AH_TRUE;
507}
508
509/*
510 * Get the TXDP for the specified queue
511 */
512u_int32_t
513ar9300_get_tx_dp(struct ath_hal *ah, u_int q)
514{
515 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
516 return OS_REG_READ(ah, AR_QTXDP(q));
517}
518
519/*
520 * Set the tx_dp for the specified queue
521 */
522HAL_BOOL
523ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp)
524{
525 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
526 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
527 HALASSERT(txdp != 0);
528
529 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
530
531 return AH_TRUE;
532}
533
534/*
535 * Transmit Enable is read-only now
536 */
537HAL_BOOL
538ar9300_start_tx_dma(struct ath_hal *ah, u_int q)
539{
540 return AH_TRUE;
541}
542
543/*
544 * Return the number of pending frames or 0 if the specified
545 * queue is stopped.
546 */
547u_int32_t
548ar9300_num_tx_pending(struct ath_hal *ah, u_int q)
549{
550 u_int32_t npend;
551
552 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
553
554 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
555 if (npend == 0) {
556 /*
557 * Pending frame count (PFC) can momentarily go to zero
558 * while TXE remains asserted. In other words a PFC of
559 * zero is not sufficient to say that the queue has stopped.
560 */
561 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) {
562 npend = 1; /* arbitrarily return 1 */
563 }
564 }
565#ifdef DEBUG
566 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
567 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
568 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n");
569 /* Clear the ready_time shutdown status bits */
570 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
571 }
572 }
573#endif
574 HALASSERT((npend == 0) ||
575 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE));
576
577 return npend;
578}
579
580/*
581 * Stop transmit on the specified queue
582 */
583HAL_BOOL
584ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout)
585{
586 struct ath_hal_9300 *ahp = AH9300(ah);
587
588 /*
589 * If we call abort txdma instead, no need to stop RX.
590 * Otherwise, the RX logic might not be restarted properly.
591 */
592 ahp->ah_abort_txdma_norx = AH_FALSE;
593
594 /*
595 * Directly call abort. It is better, hardware-wise, to stop all
596 * queues at once than individual ones.
597 */
598 return ar9300_abort_tx_dma(ah);
599
600#if 0
601#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
602#define AH_TIME_QUANTUM 100 /* usec */
603 u_int wait;
604
605 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
606
607 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
608
609 if (timeout == 0) {
610 timeout = AH_TX_STOP_DMA_TIMEOUT;
611 }
612
613 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
614
615 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
616 if (ar9300_num_tx_pending(ah, q) == 0) {
617 break;
618 }
619 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */
620 }
621
622#ifdef AH_DEBUG
623 if (wait == 0) {
624 HALDEBUG(ah, HAL_DEBUG_QUEUE,
625 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
626 HALDEBUG(ah, HAL_DEBUG_QUEUE,
627 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n",
628 __func__,
629 OS_REG_READ(ah, AR_QSTS(q)),
630 OS_REG_READ(ah, AR_Q_TXE),
631 OS_REG_READ(ah, AR_Q_TXD),
632 OS_REG_READ(ah, AR_QCBRCFG(q)));
633 HALDEBUG(ah, HAL_DEBUG_QUEUE,
634 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
635 __func__,
636 OS_REG_READ(ah, AR_QMISC(q)),
637 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
638 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
639 }
640#endif /* AH_DEBUG */
641
642 /* 2413+ and up can kill packets at the PCU level */
643 if (ar9300_num_tx_pending(ah, q)) {
644 u_int32_t tsf_low, j;
645
646 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
647 __func__, ar9300_num_tx_pending(ah, q), q);
648
649 /* Kill last PCU Tx Frame */
650 /* TODO - save off and restore current values of Q1/Q2? */
651 for (j = 0; j < 2; j++) {
652 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
653 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
654 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
655 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
656 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
657
658 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
659 break;
660 }
661
662 HALDEBUG(ah, HAL_DEBUG_QUEUE,
663 "%s: TSF have moved while trying to set "
664 "quiet time TSF: 0x%08x\n",
665 __func__, tsf_low);
666 /* TSF shouldn't count twice or reg access is taking forever */
667 HALASSERT(j < 1);
668 }
669
670 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
671
672 /* Allow the quiet mechanism to do its work */
673 OS_DELAY(200);
674 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
675
676 /* Verify all transmit is dead */
677 wait = timeout / AH_TIME_QUANTUM;
678 while (ar9300_num_tx_pending(ah, q)) {
679 if ((--wait) == 0) {
680 HALDEBUG(ah, HAL_DEBUG_TX,
681 "%s: Failed to stop Tx DMA in %d msec "
682 "after killing last frame\n",
683 __func__, timeout / 1000);
684 break;
685 }
686 OS_DELAY(AH_TIME_QUANTUM);
687 }
688
689 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
690 }
691
692 OS_REG_WRITE(ah, AR_Q_TXD, 0);
693 return (wait != 0);
694
695#undef AH_TX_STOP_DMA_TIMEOUT
696#undef AH_TIME_QUANTUM
697#endif
698}
699
700/*
701 * Really Stop transmit on the specified queue
702 */
703HAL_BOOL
704ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout)
705{
706#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
707#define AH_TIME_QUANTUM 100 /* usec */
708 u_int wait;
709
710 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
711
712 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
713
714 if (timeout == 0) {
715 timeout = AH_TX_STOP_DMA_TIMEOUT;
716 }
717
718 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
719
720 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
721 if (ar9300_num_tx_pending(ah, q) == 0) {
722 break;
723 }
724 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */
725 }
726
727#ifdef AH_DEBUG
728 if (wait == 0) {
729 HALDEBUG(ah, HAL_DEBUG_QUEUE,
730 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
731 HALDEBUG(ah, HAL_DEBUG_QUEUE,
732 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n",
733 __func__,
734 OS_REG_READ(ah, AR_QSTS(q)),
735 OS_REG_READ(ah, AR_Q_TXE),
736 OS_REG_READ(ah, AR_Q_TXD),
737 OS_REG_READ(ah, AR_QCBRCFG(q)));
738 HALDEBUG(ah, HAL_DEBUG_QUEUE,
739 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
740 __func__,
741 OS_REG_READ(ah, AR_QMISC(q)),
742 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
743 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
744 }
745#endif /* AH_DEBUG */
746
747 /* 2413+ and up can kill packets at the PCU level */
748 if (ar9300_num_tx_pending(ah, q)) {
749 u_int32_t tsf_low, j;
750
751 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
752 __func__, ar9300_num_tx_pending(ah, q), q);
753
754 /* Kill last PCU Tx Frame */
755 /* TODO - save off and restore current values of Q1/Q2? */
756 for (j = 0; j < 2; j++) {
757 tsf_low = OS_REG_READ(ah, AR_TSF_L32);
758 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
759 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
760 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
761 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
762
763 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
764 break;
765 }
766
767 HALDEBUG(ah, HAL_DEBUG_QUEUE,
768 "%s: TSF have moved while trying to set "
769 "quiet time TSF: 0x%08x\n",
770 __func__, tsf_low);
771 /* TSF shouldn't count twice or reg access is taking forever */
772 HALASSERT(j < 1);
773 }
774
775 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
776
777 /* Allow the quiet mechanism to do its work */
778 OS_DELAY(200);
779 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
780
781 /* Verify all transmit is dead */
782 wait = timeout / AH_TIME_QUANTUM;
783 while (ar9300_num_tx_pending(ah, q)) {
784 if ((--wait) == 0) {
785 HALDEBUG(ah, HAL_DEBUG_TX,
786 "%s: Failed to stop Tx DMA in %d msec "
787 "after killing last frame\n",
788 __func__, timeout / 1000);
789 break;
790 }
791 OS_DELAY(AH_TIME_QUANTUM);
792 }
793
794 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
795 }
796
797 OS_REG_WRITE(ah, AR_Q_TXD, 0);
798 return (wait != 0);
799
800#undef AH_TX_STOP_DMA_TIMEOUT
801#undef AH_TIME_QUANTUM
802}
803
804/*
805 * Abort transmit on all queues
806 */
807#define AR9300_ABORT_LOOPS 1000
808#define AR9300_ABORT_WAIT 5
809#define NEXT_TBTT_NOW 10
810HAL_BOOL
811ar9300_abort_tx_dma(struct ath_hal *ah)
812{
813 struct ath_hal_9300 *ahp = AH9300(ah);
814 int i, q;
815 u_int32_t nexttbtt, nextdba, tsf_tbtt, tbtt, dba;
816 HAL_BOOL stopped;
817 HAL_BOOL status = AH_TRUE;
818
819 if (ahp->ah_abort_txdma_norx) {
820 /*
821 * First of all, make sure RX has been stopped
822 */
823 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) {
824 /* Need to stop RX DMA before reset otherwise chip might hang */
825 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */
826 ar9300_set_rx_filter(ah, 0);
827 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */
828 if (!stopped) {
829 /*
830 * During the transition from full sleep to reset,
831 * recv DMA regs are not available to be read
832 */
833 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
834 "%s[%d]: ar9300_stop_dma_receive failed\n", __func__, __LINE__);
835 //We still continue to stop TX dma
836 //return AH_FALSE;
837 }
838 } else {
839 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
840 "%s[%d]: Chip is already in full sleep\n", __func__, __LINE__);
841 }
842 }
843
844 /*
845 * set txd on all queues
846 */
847 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
848
849 /*
850 * set tx abort bits (also disable rx)
851 */
852 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
853 /* Add a new receipe from K31 code */
854 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
855 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);
856 /* beacon Q flush */
857 nexttbtt = OS_REG_READ(ah, AR_NEXT_TBTT_TIMER);
858 nextdba = OS_REG_READ(ah, AR_NEXT_DMA_BEACON_ALERT);
859 //printk("%s[%d]:dba: %d, nt: %d \n", __func__, __LINE__, nextdba, nexttbtt);
860 tsf_tbtt = OS_REG_READ(ah, AR_TSF_L32);
861 tbtt = tsf_tbtt + NEXT_TBTT_NOW;
862 dba = tsf_tbtt;
863 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, dba);
864 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, tbtt);
865 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
866
867 /*
868 * Let TXE (all queues) clear before waiting for any pending frames
869 * This is needed before starting the RF_BUS GRANT sequence other wise causes kernel
870 * panic
871 */
872 for(i = 0; i < AR9300_ABORT_LOOPS; i++) {
873 if(OS_REG_READ(ah, AR_Q_TXE) == 0) {
874 break;
875 }
876 OS_DELAY(AR9300_ABORT_WAIT);
877 }
878 if (i == AR9300_ABORT_LOOPS) {
879 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n",
880 __func__, __LINE__);
881 }
882
883 /*
884 * wait on all tx queues
885 * This need to be checked in the last to gain extra 50 usec. on avg.
886 * Currently checked first since we dont have a previous channel information currently.
887 * Which is needed to revert the rf changes.
888 */
889 for (q = AR_NUM_QCU - 1; q >= 0; q--) {
890 for (i = 0; i < AR9300_ABORT_LOOPS; i++) {
891 if (!(ar9300_num_tx_pending(ah, q))) {
892 break;
893 }
894 OS_DELAY(AR9300_ABORT_WAIT);
895 }
896 if (i == AR9300_ABORT_LOOPS) {
897 status = AH_FALSE;
898 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
899 "ABORT LOOP finsihsed for Q: %d, num_pending: %d \n",
900 q, ar9300_num_tx_pending(ah, q));
901 goto exit;
902 }
903 }
904
905 /* Updating the beacon alert register with correct value */
906 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, nextdba);
907 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, nexttbtt);
908
909exit:
910 /*
911 * clear tx abort bits
912 */
913 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
914 /* Added a new receipe from K31 code */
915 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
916 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);
917 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
918
919 /*
920 * clear txd
921 */
922 OS_REG_WRITE(ah, AR_Q_TXD, 0);
923
924 ahp->ah_abort_txdma_norx = AH_TRUE;
925
926 return status;
927}
928
929/*
930 * Determine which tx queues need interrupt servicing.
931 */
932void
933ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs)
934{
935 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
936 "ar9300_get_tx_intr_queue: Should not be called\n");
937#if 0
938 struct ath_hal_9300 *ahp = AH9300(ah);
939 *txqs &= ahp->ah_intr_txqs;
940 ahp->ah_intr_txqs &= ~(*txqs);
941#endif
942}
943
944void
945ar9300_reset_tx_status_ring(struct ath_hal *ah)
946{
947 struct ath_hal_9300 *ahp = AH9300(ah);
948
949 ahp->ts_tail = 0;
950
951 /* Zero out the status descriptors */
952 OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs));
953 HALDEBUG(ah, HAL_DEBUG_QUEUE,
954 "%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__,
955 ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size);
956
957 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start);
958 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end);
959}
960
961void
962ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start,
963 u_int32_t ts_paddr_start, u_int16_t size)
964{
965 struct ath_hal_9300 *ahp = AH9300(ah);
966
967 ahp->ts_paddr_start = ts_paddr_start;
968 ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs));
969 ahp->ts_size = size;
970 ahp->ts_ring = (struct ar9300_txs *)ts_start;
971
972 ar9300_reset_tx_status_ring(ah);
973}