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ar9300_power.c (269793) ar9300_power.c (278741)
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH

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464 }
465
466 OS_REG_WRITE(ah, AR_EMB_CPU_WOW_ENABLE, val);
467
468 OS_REG_CLR_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF);
469 OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_REQ);
470 OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_INT_EMB_CPU);
471
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH

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464 }
465
466 OS_REG_WRITE(ah, AR_EMB_CPU_WOW_ENABLE, val);
467
468 OS_REG_CLR_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF);
469 OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_REQ);
470 OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_INT_EMB_CPU);
471
472 if (!ath_hal_wait(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF, AR_MBOX_WOW_CONF, bt_handshake_timeout_us)) {
472 if (!ath_hal_waitfor(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF, AR_MBOX_WOW_CONF, bt_handshake_timeout_us)) {
473 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: WoW offload handshake failed", __func__);
474 return 0;
475 }
476 else {
477 OS_REG_CLR_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF);
478 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: WoW offload handshake successful",__func__);
479 }
480 return 1;

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673 if (set_chip)
674 ah->ah_powerMode = mode;
675 status = ar9300_set_power_mode_awake(ah, set_chip);
676#if ATH_SUPPORT_MCI
677 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
678 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
679 }
680#endif
473 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: WoW offload handshake failed", __func__);
474 return 0;
475 }
476 else {
477 OS_REG_CLR_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF);
478 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: WoW offload handshake successful",__func__);
479 }
480 return 1;

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673 if (set_chip)
674 ah->ah_powerMode = mode;
675 status = ar9300_set_power_mode_awake(ah, set_chip);
676#if ATH_SUPPORT_MCI
677 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
678 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
679 }
680#endif
681 ahp->ah_chip_full_sleep = AH_FALSE;
681 break;
682 case HAL_PM_FULL_SLEEP:
683#if ATH_SUPPORT_MCI
684 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
685 if (ar9300_get_power_mode(ah) == HAL_PM_AWAKE) {
686 if ((ar9300_mci_state(ah, HAL_MCI_STATE_ENABLE, NULL) != 0) &&
687 (ahp->ah_mci_bt_state != MCI_BT_SLEEP) &&
688 !ahp->ah_mci_halted_bt_gpm)

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982}
983
984HAL_BOOL
985ar9300_set_power_mode_wow_sleep(struct ath_hal *ah)
986{
987 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
988
989 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
682 break;
683 case HAL_PM_FULL_SLEEP:
684#if ATH_SUPPORT_MCI
685 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
686 if (ar9300_get_power_mode(ah) == HAL_PM_AWAKE) {
687 if ((ar9300_mci_state(ah, HAL_MCI_STATE_ENABLE, NULL) != 0) &&
688 (ahp->ah_mci_bt_state != MCI_BT_SLEEP) &&
689 !ahp->ah_mci_halted_bt_gpm)

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983}
984
985HAL_BOOL
986ar9300_set_power_mode_wow_sleep(struct ath_hal *ah)
987{
988 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
989
990 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
990 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
991 if (!ath_hal_waitfor(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
991 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: dma failed to stop in 10ms\n"
992 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", __func__,
993 OS_REG_READ(ah, AR_CR), OS_REG_READ(ah, AR_DIAG_SW));
994 return AH_FALSE;
995 } else {
996#if 0
997 OS_REG_WRITE(ah, AR_RXDP, 0x0);
998#endif

--- 567 unchanged lines hidden --- 		992 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: dma failed to stop in 10ms\n"
993 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", __func__,
994 OS_REG_READ(ah, AR_CR), OS_REG_READ(ah, AR_DIAG_SW));
995 return AH_FALSE;
996 } else {
997#if 0
998 OS_REG_WRITE(ah, AR_RXDP, 0x0);
999#endif

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