| ar9300_misc.c (250130) | ar9300_misc.c (278741) |
|---|---|
| 1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH --- 1683 unchanged lines hidden (view full) --- 1692 * This is a very common occurence as a compromise between 1693 * BB Panic and AH_FALSE detects (EV71009). It indicates 1694 * radar hang, which can be cleared by reprogramming 1695 * radar related register and does not requre a chip reset 1696 */ 1697 1698 /* Suppress BB Status mesg following signature */ 1699 switch (bb_panic->status) { | 1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH --- 1683 unchanged lines hidden (view full) --- 1692 * This is a very common occurence as a compromise between 1693 * BB Panic and AH_FALSE detects (EV71009). It indicates 1694 * radar hang, which can be cleared by reprogramming 1695 * radar related register and does not requre a chip reset 1696 */ 1697 1698 /* Suppress BB Status mesg following signature */ 1699 switch (bb_panic->status) { |
| 1700 case 0x04000539: 1701 case 0x04008009: 1702 case 0x04000b09: 1703 case 0x1300000a: | 1700 case 0x04000539: 1701 case 0x04008009: 1702 case 0x04000b09: 1703 case 0x1300000a: |
| 1704 return -1; 1705 } 1706 1707 bb_panic->tsf = ar9300_get_tsf32(ah); 1708 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1709 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1710 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1711 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); --- 2001 unchanged lines hidden (view full) --- 3713void 3714ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3715{ 3716 u_int32_t val; 3717 u_int32_t qnum = (u_int32_t)data; 3718 3719 /* Disable AGC to A2 */ 3720 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); | 1704 return -1; 1705 } 1706 1707 bb_panic->tsf = ar9300_get_tsf32(ah); 1708 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1709 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1710 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1711 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); --- 2001 unchanged lines hidden (view full) --- 3713void 3714ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3715{ 3716 u_int32_t val; 3717 u_int32_t qnum = (u_int32_t)data; 3718 3719 /* Disable AGC to A2 */ 3720 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); |
| 3721 OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); 3722 OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); | |
| 3723 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3724 3725 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3726 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3727 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3728 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3729 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3730 /* 200 ok for HT20, 400 ok for HT40 */ --- 27 unchanged lines hidden (view full) --- 3758 return AH_FALSE; 3759} 3760 3761HAL_BOOL 3762ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3763{ 3764 return AH_FALSE; 3765} | 3721 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3722 3723 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3724 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3725 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3726 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3727 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3728 /* 200 ok for HT20, 400 ok for HT40 */ --- 27 unchanged lines hidden (view full) --- 3756 return AH_FALSE; 3757} 3758 3759HAL_BOOL 3760ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3761{ 3762 return AH_FALSE; 3763} |
| 3764 3765HAL_BOOL 3766ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array) 3767{ 3768 struct ath_hal_9300 *ahp = AH9300(ah); 3769 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom; 3770 u_int8_t *ctl_index; 3771 u_int32_t offset = 0; 3772 3773 if (!ctl_array) 3774 return AH_FALSE; 3775 3776 /* copy 2G ctl freqbin and power data */ 3777 ctl_index = p_eep_data->ctl_index_2g; 3778 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array, 3779 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */ 3780 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */ 3781 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) + 3782 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); 3783 3784 3785 /* copy 2G ctl freqbin and power data */ 3786 ctl_index = p_eep_data->ctl_index_5g; 3787 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset, 3788 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */ 3789 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */ 3790 3791 return AH_FALSE; 3792} 3793 3794void 3795ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask) 3796{ 3797 struct ath_hal_9300 *ahp = AH9300(ah); 3798 3799 /* optional txchainmask should be subset of primary txchainmask */ 3800 if ((mask & ahp->ah_tx_chainmask) != mask) { 3801 ahp->ah_tx_chainmaskopt = 0; 3802 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask); 3803 return; 3804 } 3805 3806 ahp->ah_tx_chainmaskopt = mask; 3807} |
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