1700,1703c1700,1703
< case 0x04000539:
< case 0x04008009:
< case 0x04000b09:
< case 0x1300000a:
---
> case 0x04000539:
> case 0x04008009:
> case 0x04000b09:
> case 0x1300000a:
3721,3722d3720
< OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
< OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
3765a3764,3807
>
> HAL_BOOL
> ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array)
> {
> struct ath_hal_9300 *ahp = AH9300(ah);
> ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom;
> u_int8_t *ctl_index;
> u_int32_t offset = 0;
>
> if (!ctl_array)
> return AH_FALSE;
>
> /* copy 2G ctl freqbin and power data */
> ctl_index = p_eep_data->ctl_index_2g;
> OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array,
> OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */
> OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */
> offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) +
> ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G));
>
>
> /* copy 2G ctl freqbin and power data */
> ctl_index = p_eep_data->ctl_index_5g;
> OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset,
> OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */
> OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */
>
> return AH_FALSE;
> }
>
> void
> ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask)
> {
> struct ath_hal_9300 *ahp = AH9300(ah);
>
> /* optional txchainmask should be subset of primary txchainmask */
> if ((mask & ahp->ah_tx_chainmask) != mask) {
> ahp->ah_tx_chainmaskopt = 0;
> ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask);
> return;
> }
>
> ahp->ah_tx_chainmaskopt = mask;
> }