1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
19#include "ah.h"
20#include "ah_internal.h"
21#include "ah_devid.h"
22#ifdef AH_DEBUG
23#include "ah_desc.h" /* NB: for HAL_PHYERR* */
24#endif
25
26#include "ar9300/ar9300.h"
27#include "ar9300/ar9300reg.h"
28#include "ar9300/ar9300phy.h"
29
30
31void
32ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs)
33{
34 struct ath_hal_9300 *ahp = AH9300(ah);
35 *hangs = 0;
36
37 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) {
38 *hangs |= HAL_RIFS_BB_HANG_WAR;
39 }
40 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) {
41 *hangs |= HAL_DFS_BB_HANG_WAR;
42 }
43 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL)
44 == HAL_OK)
45 {
46 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR;
47 }
48 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) {
49 *hangs |= HAL_MAC_HANG_WAR;
50 }
51 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
52 == HAL_OK)
53 {
54 *hangs |= HAL_PHYRESTART_CLR_WAR;
55 }
56
57 ahp->ah_hang_wars = *hangs;
58}
59
60/*
61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
62 * HT20, HT40, fast-clock, turbo mode, etc.
63 */
64static u_int
65ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
66{
67#if 0
68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
69
70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71 return (ath_hal_mac_usec(ah, clks) / 2);
72 } else {
73 return (ath_hal_mac_usec(ah, clks));
74 }
75#endif
76 return (ath_hal_mac_usec(ah, clks));
77}
78
79u_int
80ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
81{
82#if 0
83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
84
85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
86 return (ath_hal_mac_clks(ah, usecs) * 2);
87 } else {
88 return (ath_hal_mac_clks(ah, usecs));
89 }
90#endif
91 return (ath_hal_mac_clks(ah, usecs));
92}
93
94void
95ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
96{
97 struct ath_hal_9300 *ahp = AH9300(ah);
98
99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
100}
101
102HAL_BOOL
103ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac)
104{
105 struct ath_hal_9300 *ahp = AH9300(ah);
106
107 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
108 return AH_TRUE;
109}
110
111void
112ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask)
113{
114 struct ath_hal_9300 *ahp = AH9300(ah);
115
116 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN);
117}
118
119HAL_BOOL
120ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask)
121{
122 struct ath_hal_9300 *ahp = AH9300(ah);
123
124 /* save it since it must be rewritten on reset */
125 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN);
126
127 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
128 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
129 return AH_TRUE;
130}
131
132/*
133 * Attempt to change the cards operating regulatory domain to the given value
134 * Returns: A_EINVAL for an unsupported regulatory domain.
135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
136 */
137HAL_BOOL
138ar9300_set_regulatory_domain(struct ath_hal *ah,
139 u_int16_t reg_domain, HAL_STATUS *status)
140{
141 HAL_STATUS ecode;
142
143 if (AH_PRIVATE(ah)->ah_currentRD == 0) {
144 AH_PRIVATE(ah)->ah_currentRD = reg_domain;
145 return AH_TRUE;
146 }
147 ecode = HAL_EIO;
148
149#if 0
150bad:
151#endif
152 if (status) {
153 *status = ecode;
154 }
155 return AH_FALSE;
156}
157
158/*
159 * Return the wireless modes (a,b,g,t) supported by hardware.
160 *
161 * This value is what is actually supported by the hardware
162 * and is unaffected by regulatory/country code settings.
163 *
164 */
165u_int
166ar9300_get_wireless_modes(struct ath_hal *ah)
167{
168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
169}
170
171/*
172 * Set the interrupt and GPIO values so the ISR can disable RF
173 * on a switch signal. Assumes GPIO port and interrupt polarity
174 * are set prior to call.
175 */
176void
177ar9300_enable_rf_kill(struct ath_hal *ah)
178{
179 /* TODO - can this really be above the hal on the GPIO interface for
180 * TODO - the client only?
181 */
182 struct ath_hal_9300 *ahp = AH9300(ah);
183
184 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
185 /* Check RF kill GPIO before set/clear RFSILENT bits. */
186 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) {
187 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
188 AR_RFSILENT_FORCE);
189 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
190 }
191 else {
192 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
193 AR_RFSILENT_FORCE);
194 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
195 }
196 }
197 else {
198 /* Connect rfsilent_bb_l to baseband */
199 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
200 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
201
202 /* Set input mux for rfsilent_bb_l to GPIO #0 */
203 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
204 AR_GPIO_INPUT_MUX2_RFSILENT);
205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206 (ahp->ah_gpio_select & 0x0f) << 4);
207
208 /*
209 * Configure the desired GPIO port for input and
210 * enable baseband rf silence
211 */
212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
214 }
215
216 /*
217 * If radio disable switch connection to GPIO bit x is enabled
218 * program GPIO interrupt.
219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
220 * verified that it is a later version of eeprom, it has a place for
221 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
222 * connection is present.
223 */
224 /*
225 * RFKill uses polling not interrupt,
226 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue
227 */
228 if (ath_hal_hasrfkill_int(ah)) {
229 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) {
230 /* switch already closed, set to interrupt upon open */
231 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit);
232 } else {
233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit);
234 }
235 }
236}
237
238/*
239 * Change the LED blinking pattern to correspond to the connectivity
240 */
241void
242ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state)
243{
244 static const u_int32_t ledbits[8] = {
245 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */
246 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */
247 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */
248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */
249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */
250 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */
251 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */
252 AR_CFG_LED_ASSOC_NONE,
253 };
254
255 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]);
256}
257
258/*
259 * Sets the Power LED on the cardbus without affecting the Network LED.
260 */
261void
262ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled)
263{
264 u_int32_t val;
265
266 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF;
267 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val);
268}
269
270/*
271 * Sets the Network LED on the cardbus without affecting the Power LED.
272 */
273void
274ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled)
275{
276 u_int32_t val;
277
278 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF;
279 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val);
280}
281
282/*
283 * Change association related fields programmed into the hardware.
284 * Writing a valid BSSID to the hardware effectively enables the hardware
285 * to synchronize its TSF to the correct beacons and receive frames coming
286 * from that BSSID. It is called by the SME JOIN operation.
287 */
288void
289ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
290 u_int16_t assoc_id)
291{
292 struct ath_hal_9300 *ahp = AH9300(ah);
293
294 /* save bssid and assoc_id for restore on reset */
295 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
296 ahp->ah_assoc_id = assoc_id;
297
298 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
299 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
300 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S));
301}
302
303/*
304 * Get the current hardware tsf for stamlme
305 */
306u_int64_t
307ar9300_get_tsf64(struct ath_hal *ah)
308{
309 u_int64_t tsf;
310
311 /* XXX sync multi-word read? */
312 tsf = OS_REG_READ(ah, AR_TSF_U32);
313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
314 return tsf;
315}
316
317void
318ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf)
319{
320 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff));
321 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff));
322}
323
324/*
325 * Get the current hardware tsf for stamlme
326 */
327u_int32_t
328ar9300_get_tsf32(struct ath_hal *ah)
329{
330 return OS_REG_READ(ah, AR_TSF_L32);
331}
332
333u_int32_t
334ar9300_get_tsf2_32(struct ath_hal *ah)
335{
336 return OS_REG_READ(ah, AR_TSF2_L32);
337}
338
339/*
340 * Reset the current hardware tsf for stamlme.
341 */
342void
343ar9300_reset_tsf(struct ath_hal *ah)
344{
345 int count;
346
347 count = 0;
348 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
349 count++;
350 if (count > 10) {
351 HALDEBUG(ah, HAL_DEBUG_RESET,
352 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__);
353 break;
354 }
355 OS_DELAY(10);
356 }
357 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
358}
359
360/*
361 * Set or clear hardware basic rate bit
362 * Set hardware basic rate set if basic rate is found
363 * and basic rate is equal or less than 2Mbps
364 */
365void
366ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
367{
368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
369 u_int32_t reg;
370 u_int8_t xset;
371 int i;
372
373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
374 return;
375 }
376 xset = 0;
377 for (i = 0; i < rs->rs_count; i++) {
378 u_int8_t rset = rs->rs_rates[i];
379 /* Basic rate defined? */
380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
381 xset = rset;
382 }
383 }
384 /*
385 * Set the h/w bit to reflect whether or not the basic
386 * rate is found to be equal or less than 2Mbps.
387 */
388 reg = OS_REG_READ(ah, AR_STA_ID1);
389 if (xset && xset / 2 <= 2) {
390 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
391 } else {
392 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
393 }
394}
395
396/*
397 * Grab a semi-random value from hardware registers - may not
398 * change often
399 */
400u_int32_t
401ar9300_get_random_seed(struct ath_hal *ah)
402{
403 u_int32_t nf;
404
405 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
406 if (nf & 0x100) {
407 nf = 0 - ((nf ^ 0x1ff) + 1);
408 }
409 return (OS_REG_READ(ah, AR_TSF_U32) ^
410 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
411}
412
413/*
414 * Detect if our card is present
415 */
416HAL_BOOL
417ar9300_detect_card_present(struct ath_hal *ah)
418{
419 u_int16_t mac_version, mac_rev;
420 u_int32_t v;
421
422 /*
423 * Read the Silicon Revision register and compare that
424 * to what we read at attach time. If the same, we say
425 * a card/device is present.
426 */
427 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID;
428 if (v == 0xFF) {
429 /* new SREV format */
430 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
431 /*
432 * Include 6-bit Chip Type (masked to 0) to differentiate
433 * from pre-Sowl versions
434 */
435 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
436 mac_rev = MS(v, AR_SREV_REVISION2);
437 } else {
438 mac_version = MS(v, AR_SREV_VERSION);
439 mac_rev = v & AR_SREV_REVISION;
440 }
441 return (AH_PRIVATE(ah)->ah_macVersion == mac_version &&
442 AH_PRIVATE(ah)->ah_macRev == mac_rev);
443}
444
445/*
446 * Update MIB Counters
447 */
448void
449ar9300_update_mib_mac_stats(struct ath_hal *ah)
450{
451 struct ath_hal_9300 *ahp = AH9300(ah);
452 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats;
453
454 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
455 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
456 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
457 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
458 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
459}
460
461void
462ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats)
463{
464 struct ath_hal_9300 *ahp = AH9300(ah);
465 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats;
466
467 stats->ackrcv_bad = istats->ackrcv_bad;
468 stats->rts_bad = istats->rts_bad;
469 stats->fcs_bad = istats->fcs_bad;
470 stats->rts_good = istats->rts_good;
471 stats->beacons = istats->beacons;
472}
473
474/*
475 * Detect if the HW supports spreading a CCK signal on channel 14
476 */
477HAL_BOOL
478ar9300_is_japan_channel_spread_supported(struct ath_hal *ah)
479{
480 return AH_TRUE;
481}
482
483/*
484 * Get the rssi of frame curently being received.
485 */
486u_int32_t
487ar9300_get_cur_rssi(struct ath_hal *ah)
488{
489 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */
490 /* get combined RSSI */
491 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff);
492}
493
494#if ATH_GEN_RANDOMNESS
495/*
496 * Get the rssi value from BB on ctl chain0.
497 */
498u_int32_t
499ar9300_get_rssi_chain0(struct ath_hal *ah)
500{
501 /* get ctl chain0 RSSI */
502 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff;
503}
504#endif
505
506u_int
507ar9300_get_def_antenna(struct ath_hal *ah)
508{
509 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
510}
511
512/* Setup coverage class */
513void
514ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now)
515{
516}
517
518void
519ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
520{
521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
522}
523
524HAL_BOOL
525ar9300_set_antenna_switch(struct ath_hal *ah,
526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
528{
529 struct ath_hal_9300 *ahp = AH9300(ah);
530
531 /*
532 * Owl does not support diversity or changing antennas.
533 *
534 * Instead this API and function are defined differently for AR9300.
535 * To support Tablet PC's, this interface allows the system
536 * to dramatically reduce the TX power on a particular chain.
537 *
538 * Based on the value of (redefined) diversity_control, the
539 * reset code will decrease power on chain 0 or chain 1/2.
540 *
541 * Based on the value of bit 0 of antenna_switch_swap,
542 * the mapping between OID call and chain is defined as:
543 * 0: map A -> 0, B -> 1;
544 * 1: map A -> 1, B -> 0;
545 *
546 * NOTE:
547 * The devices that use this OID should use a tx_chain_mask and
548 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is
549 * used in order to ensure an active transmit antenna. This
550 * API will allow the host to turn off the only transmitting
551 * antenna to ensure the antenna closest to the user's body is
552 * powered-down.
553 */
554 /*
555 * Set antenna control for use during reset sequence by
556 * ar9300_decrease_chain_power()
557 */
558 ahp->ah_diversity_control = settings;
559
560 return AH_TRUE;
561}
562
563HAL_BOOL
564ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah)
565{
566 return AH_TRUE;
567}
568
569HAL_BOOL
570ar9300_set_slot_time(struct ath_hal *ah, u_int us)
571{
572 struct ath_hal_9300 *ahp = AH9300(ah);
573 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) {
574 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us);
575 ahp->ah_slot_time = (u_int) -1; /* restore default handling */
576 return AH_FALSE;
577 } else {
578 /* convert to system clocks */
579 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us));
580 ahp->ah_slot_time = us;
581 return AH_TRUE;
582 }
583}
584
585HAL_BOOL
586ar9300_set_ack_timeout(struct ath_hal *ah, u_int us)
587{
588 struct ath_hal_9300 *ahp = AH9300(ah);
589
590 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
591 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us);
592 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */
593 return AH_FALSE;
594 } else {
595 /* convert to system clocks */
596 OS_REG_RMW_FIELD(ah,
597 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us));
598 ahp->ah_ack_timeout = us;
599 return AH_TRUE;
600 }
601}
602
603u_int
604ar9300_get_ack_timeout(struct ath_hal *ah)
605{
606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
608}
609
610HAL_STATUS
611ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
612 u_int32_t next_start, HAL_QUIET_FLAG flag)
613{
614#define TU_TO_USEC(_tu) ((_tu) << 10)
615 HAL_STATUS status = HAL_EIO;
616 u_int32_t tsf = 0, j, next_start_us = 0;
617 if (flag & HAL_QUIET_ENABLE) {
618 for (j = 0; j < 2; j++) {
619 next_start_us = TU_TO_USEC(next_start);
620 tsf = OS_REG_READ(ah, AR_TSF_L32);
621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
622 next_start_us += tsf;
623 }
624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
625 next_start_us +=
626 ah->ah_config.ah_sw_beacon_response_time;
627 }
628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
634 status = HAL_OK;
635 break;
636 }
637 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved "
638 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf);
639 /* TSF shouldn't count twice or reg access is taking forever */
640 HALASSERT(j < 1);
641 }
642 } else {
643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
644 status = HAL_OK;
645 }
646
647 return status;
648#undef TU_TO_USEC
649}
650#ifdef ATH_SUPPORT_DFS
651void
652ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
653{
654 u32 reg1, reg2;
655
656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));
657 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1));
658 AH9300(ah)->ah_cac_quiet_enabled = enable;
659
660 if (enable) {
661 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
662 reg1 | AR_PCU_FORCE_QUIET_COLL);
663 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
664 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE);
665 } else {
666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
667 reg1 & ~AR_PCU_FORCE_QUIET_COLL);
668 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
669 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE);
670 }
671}
672#endif /* ATH_SUPPORT_DFS */
673
674void
675ar9300_set_pcu_config(struct ath_hal *ah)
676{
677 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode);
678}
679
680HAL_STATUS
681ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
682 u_int32_t capability, u_int32_t *result)
683{
684 struct ath_hal_9300 *ahp = AH9300(ah);
685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
686
687 switch (type) {
688 case HAL_CAP_CIPHER: /* cipher handled in hardware */
689 switch (capability) {
690 case HAL_CIPHER_AES_CCM:
691 case HAL_CIPHER_AES_OCB:
692 case HAL_CIPHER_TKIP:
693 case HAL_CIPHER_WEP:
694 case HAL_CIPHER_MIC:
695 case HAL_CIPHER_CLR:
696 return HAL_OK;
697 default:
698 return HAL_ENOTSUPP;
699 }
700 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
701 switch (capability) {
702 case 0: /* hardware capability */
703 return HAL_OK;
704 case 1:
705 return (ahp->ah_sta_id1_defaults &
706 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
707 default:
708 return HAL_ENOTSUPP;
709 }
710 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
711 switch (capability) {
712 case 0: /* hardware capability */
713 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
714 case 1: /* current setting */
715 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
716 HAL_ENXIO : HAL_OK;
717 default:
718 return HAL_ENOTSUPP;
719 }
720 case HAL_CAP_WME_TKIPMIC:
721 /* hardware can do TKIP MIC when WMM is turned on */
722 return HAL_OK;
723 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
724 return HAL_OK;
725 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
726 switch (capability) {
727 case 0: /* hardware capability */
728 return HAL_OK;
729 case 1: /* current setting */
730 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) &
731 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
732 HAL_OK : HAL_ENXIO;
733 }
734 return HAL_EINVAL;
735 case HAL_CAP_TPC:
736 switch (capability) {
737 case 0: /* hardware capability */
738 return HAL_OK;
739 case 1:
740 return ah->ah_config.ath_hal_desc_tpc ?
741 HAL_OK : HAL_ENXIO;
742 }
743 return HAL_OK;
744 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
745 return HAL_OK;
746 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
747 switch (capability) {
748 case 0: /* hardware capability */
749 return HAL_OK;
750 case 1:
751 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
752 /*
753 * Owl and Merlin have problems in mcast key search.
754 * Disable this cap. in Ad-hoc mode. see Bug 25776 and
755 * 26802
756 */
757 return HAL_ENXIO;
758 } else {
759 return (ahp->ah_sta_id1_defaults &
760 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
761 }
762 }
763 return HAL_EINVAL;
764 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
765 switch (capability) {
766 case 0: /* hardware capability */
767 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
768 case 1:
769 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
770 HAL_OK : HAL_ENXIO;
771 }
772 return HAL_EINVAL;
773 case HAL_CAP_RFSILENT: /* rfsilent support */
774 if (capability == 3) { /* rfkill interrupt */
775 /*
776 * XXX: Interrupt-based notification of RF Kill state
777 * changes not working yet. Report that this feature
778 * is not supported so that polling is used instead.
779 */
780 return (HAL_ENOTSUPP);
781 }
782 return ath_hal_getcapability(ah, type, capability, result);
783 case HAL_CAP_4ADDR_AGGR:
784 return HAL_OK;
785 case HAL_CAP_BB_RIFS_HANG:
786 return HAL_ENOTSUPP;
787 case HAL_CAP_BB_DFS_HANG:
788 return HAL_ENOTSUPP;
789 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG:
790 /* Track chips that are known to have BB hangs related
791 * to rx_clear stuck low.
792 */
793 return HAL_ENOTSUPP;
794 case HAL_CAP_MAC_HANG:
795 /* Track chips that are known to have MAC hangs.
796 */
797 return HAL_OK;
798 case HAL_CAP_RIFS_RX_ENABLED:
799 /* Is RIFS RX currently enabled */
800 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
801#if 0
802 case HAL_CAP_ANT_CFG_2GHZ:
803 *result = p_cap->halNumAntCfg2Ghz;
804 return HAL_OK;
805 case HAL_CAP_ANT_CFG_5GHZ:
806 *result = p_cap->halNumAntCfg5Ghz;
807 return HAL_OK;
808 case HAL_CAP_RX_STBC:
809 *result = p_cap->hal_rx_stbc_support;
810 return HAL_OK;
811 case HAL_CAP_TX_STBC:
812 *result = p_cap->hal_tx_stbc_support;
813 return HAL_OK;
814#endif
815 case HAL_CAP_LDPC:
816 *result = p_cap->halLDPCSupport;
817 return HAL_OK;
818 case HAL_CAP_DYNAMIC_SMPS:
819 return HAL_OK;
820 case HAL_CAP_DS:
821 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
822 (p_cap->halTxChainMask & 0x3) != 0x3 ||
823 (p_cap->halRxChainMask & 0x3) != 0x3) ?
824 HAL_ENOTSUPP : HAL_OK;
825 case HAL_CAP_TS:
826 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
827 (p_cap->halTxChainMask & 0x7) != 0x7 ||
828 (p_cap->halRxChainMask & 0x7) != 0x7) ?
829 HAL_ENOTSUPP : HAL_OK;
830 case HAL_CAP_OL_PWRCTRL:
831 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
832 HAL_OK : HAL_ENOTSUPP;
833 case HAL_CAP_CRDC:
834#if ATH_SUPPORT_CRDC
835 return (AR_SREV_WASP(ah) &&
836 ah->ah_config.ath_hal_crdc_enable) ?
837 HAL_OK : HAL_ENOTSUPP;
838#else
839 return HAL_ENOTSUPP;
840#endif
841#if 0
842 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
843 *result = (u_int32_t)(-1);
844 return HAL_OK;
845 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
846 *result = (u_int32_t)(-1);
847 return HAL_OK;
848#endif
849 case HAL_CAP_BB_PANIC_WATCHDOG:
850 return HAL_OK;
851 case HAL_CAP_PHYRESTART_CLR_WAR:
852 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
853 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
854 {
855 return HAL_OK;
856 }
857 else
858 {
859 return HAL_ENOTSUPP;
860 }
861 case HAL_CAP_ENTERPRISE_MODE:
862 *result = ahp->ah_enterprise_mode >> 16;
863 /*
864 * WAR for EV 77658 - Add delimiters to first sub-frame when using
865 * RTS/CTS with aggregation and non-enterprise Osprey.
866 *
867 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
868 */
869 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
870 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
871 AR_SREV_WASP_10(ah))) {
872 *result |= AH_ENT_RTSCTS_DELIM_WAR;
873 }
874 return HAL_OK;
875 case HAL_CAP_LDPCWAR:
876 /* WAR for RIFS+LDPC issue is required for all chips currently
877 * supported by ar9300 HAL.
878 */
879 return HAL_OK;
880 case HAL_CAP_ENABLE_APM:
881 *result = p_cap->halApmEnable;
882 return HAL_OK;
883 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
884 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
885 case HAL_CAP_PCIE_LCR_OFFSET:
886 *result = p_cap->hal_pcie_lcr_offset;
887 return HAL_OK;
888 case HAL_CAP_SMARTANTENNA:
889 /* FIXME A request is pending with h/w team to add feature bit in
890 * caldata to detect if board has smart antenna or not, once added
891 * we need to fix his piece of code to read and return value without
892 * any compile flags
893 */
894#if UMAC_SUPPORT_SMARTANTENNA
895 /* enable smart antenna for Peacock, Wasp and scorpion
896 for future chips need to modify */
897 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) {
898 return HAL_OK;
899 } else {
900 return HAL_ENOTSUPP;
901 }
902#else
903 return HAL_ENOTSUPP;
904#endif
905
906#ifdef ATH_TRAFFIC_FAST_RECOVER
907 case HAL_CAP_TRAFFIC_FAST_RECOVER:
908 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) {
909 return HAL_OK;
910 } else {
911 return HAL_ENOTSUPP;
912 }
913#endif
914 default:
915 return ath_hal_getcapability(ah, type, capability, result);
916 }
917}
918
919HAL_BOOL
920ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
921 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
922{
923 struct ath_hal_9300 *ahp = AH9300(ah);
924 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
925 u_int32_t v;
926
927 switch (type) {
928 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
929 if (! p_cap->halTkipMicTxRxKeySupport)
930 return AH_FALSE;
931
932 if (setting)
933 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
934 else
935 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
936
937 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
938 return AH_TRUE;
939
940 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
941 if (setting) {
942 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
943 } else {
944 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
945 }
946 return AH_TRUE;
947 case HAL_CAP_DIVERSITY:
948 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
949 if (setting) {
950 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
951 } else {
952 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
953 }
954 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
955 return AH_TRUE;
956 case HAL_CAP_DIAG: /* hardware diagnostic support */
957 /*
958 * NB: could split this up into virtual capabilities,
959 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
960 * seems worth the additional complexity.
961 */
962#ifdef AH_DEBUG
963 AH_PRIVATE(ah)->ah_diagreg = setting;
964#else
965 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
966#endif
967 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
968 return AH_TRUE;
969 case HAL_CAP_TPC:
970 ah->ah_config.ath_hal_desc_tpc = (setting != 0);
971 return AH_TRUE;
972 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
973 if (setting) {
974 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
975 } else {
976 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
977 }
978 return AH_TRUE;
979 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
980 if (p_cap->halTsfAddSupport) {
981 if (setting) {
982 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
983 } else {
984 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
985 }
986 return AH_TRUE;
987 }
988 return AH_FALSE;
989 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */
990 ahp->rx_buf_size = setting & AR_DATABUF_MASK;
991 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
992 return AH_TRUE;
993
994 /* fall thru... */
995 default:
996 return ath_hal_setcapability(ah, type, capability, setting, status);
997 }
998}
999
1000#ifdef AH_DEBUG
1001static void
1002ar9300_print_reg(struct ath_hal *ah, u_int32_t args)
1003{
1004 u_int32_t i = 0;
1005
1006 /* Read 0x80d0 to trigger pcie analyzer */
1007 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1008 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0));
1009
1010 if (args & HAL_DIAG_PRINT_REG_COUNTER) {
1011 struct ath_hal_9300 *ahp = AH9300(ah);
1012 u_int32_t tf, rf, rc, cc;
1013
1014 tf = OS_REG_READ(ah, AR_TFCNT);
1015 rf = OS_REG_READ(ah, AR_RFCNT);
1016 rc = OS_REG_READ(ah, AR_RCCNT);
1017 cc = OS_REG_READ(ah, AR_CCCNT);
1018
1019 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1020 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf);
1021 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1022 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf);
1023 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1024 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc);
1025 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1026 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc);
1027
1028 ahp->last_tf = tf;
1029 ahp->last_rf = rf;
1030 ahp->last_rc = rc;
1031 ahp->last_cc = cc;
1032
1033 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1034 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0));
1035 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1036 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1));
1037 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1038 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2));
1039 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1040 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3));
1041 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1042 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4));
1043 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1044 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5));
1045 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1046 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6));
1047 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1048 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7));
1049 }
1050
1051 if (args & HAL_DIAG_PRINT_REG_ALL) {
1052 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) {
1053 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1054 i, OS_REG_READ(ah, i));
1055 }
1056
1057 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) {
1058 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1059 i, OS_REG_READ(ah, i));
1060 }
1061
1062 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1063 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i));
1064
1065 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1066 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i));
1067
1068 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) {
1069 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1070 i, OS_REG_READ(ah, i));
1071 }
1072
1073 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) {
1074 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1075 i, OS_REG_READ(ah, i));
1076 }
1077
1078 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) {
1079 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1080 i, OS_REG_READ(ah, i));
1081 }
1082
1083 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) {
1084 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1085 i, OS_REG_READ(ah, i));
1086 }
1087
1088 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) {
1089 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1090 i, OS_REG_READ(ah, i));
1091 }
1092
1093 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) {
1094 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1095 i, OS_REG_READ(ah, i));
1096 }
1097
1098 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) {
1099 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1100 i, OS_REG_READ(ah, i));
1101 }
1102
1103 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) {
1104 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1105 i, OS_REG_READ(ah, i));
1106 }
1107
1108 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) {
1109 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1110 i, OS_REG_READ(ah, i));
1111 }
1112
1113 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) {
1114 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1115 i, OS_REG_READ(ah, i));
1116 }
1117
1118 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) {
1119 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1120 i, OS_REG_READ(ah, i));
1121 }
1122 }
1123}
1124#endif
1125
1126HAL_BOOL
1127ar9300_get_diag_state(struct ath_hal *ah, int request,
1128 const void *args, u_int32_t argsize,
1129 void **result, u_int32_t *resultsize)
1130{
1131 struct ath_hal_9300 *ahp = AH9300(ah);
1132
1133 (void) ahp;
1134 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) {
1135 return AH_TRUE;
1136 }
1137 switch (request) {
1138#ifdef AH_PRIVATE_DIAG
1139 case HAL_DIAG_EEPROM:
1140 *result = &ahp->ah_eeprom;
1141 *resultsize = sizeof(ar9300_eeprom_t);
1142 return AH_TRUE;
1143
1144#if 0 /* XXX - TODO */
1145 case HAL_DIAG_EEPROM_EXP_11A:
1146 case HAL_DIAG_EEPROM_EXP_11B:
1147 case HAL_DIAG_EEPROM_EXP_11G:
1148 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A];
1149 *result = pe->p_channels;
1150 *resultsize = (*result == AH_NULL) ? 0 :
1151 roundup(sizeof(u_int16_t) * pe->num_channels,
1152 sizeof(u_int32_t)) +
1153 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels;
1154 return AH_TRUE;
1155#endif
1156 case HAL_DIAG_RFGAIN:
1157 *result = &ahp->ah_gain_values;
1158 *resultsize = sizeof(GAIN_VALUES);
1159 return AH_TRUE;
1160 case HAL_DIAG_RFGAIN_CURSTEP:
1161 *result = (void *) ahp->ah_gain_values.curr_step;
1162 *resultsize = (*result == AH_NULL) ?
1163 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1164 return AH_TRUE;
1165#if 0 /* XXX - TODO */
1166 case HAL_DIAG_PCDAC:
1167 *result = ahp->ah_pcdac_table;
1168 *resultsize = ahp->ah_pcdac_table_size;
1169 return AH_TRUE;
1170#endif
1171 case HAL_DIAG_ANI_CURRENT:
1172 *result = ar9300_ani_get_current_state(ah);
1173 *resultsize = (*result == AH_NULL) ?
1174 0 : sizeof(struct ar9300_ani_state);
1175 return AH_TRUE;
1176 case HAL_DIAG_ANI_STATS:
1177 *result = ar9300_ani_get_current_stats(ah);
1178 *resultsize = (*result == AH_NULL) ?
1179 0 : sizeof(struct ar9300_stats);
1180 return AH_TRUE;
1181 case HAL_DIAG_ANI_CMD:
1182 if (argsize != 2*sizeof(u_int32_t)) {
1183 return AH_FALSE;
1184 }
1185 ar9300_ani_control(
1186 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1187 return AH_TRUE;
1188#if 0
1189 case HAL_DIAG_TXCONT:
1190 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1191 return AH_TRUE;
1192#endif /* 0 */
1193#endif /* AH_PRIVATE_DIAG */
1194 case HAL_DIAG_CHANNELS:
1195#if 0
1196 *result = &(ahp->ah_priv.ah_channels[0]);
1197 *resultsize =
1198 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1199#endif
1200 return AH_TRUE;
1201#ifdef AH_DEBUG
1202 case HAL_DIAG_PRINT_REG:
1203 ar9300_print_reg(ah, *((const u_int32_t *)args));
1204 return AH_TRUE;
1205#endif
1206 default:
1207 break;
1208 }
1209
1210 return AH_FALSE;
1211}
1212
1213void
1214ar9300_dma_reg_dump(struct ath_hal *ah)
1215{
1216#ifdef AH_DEBUG
1217#define NUM_DMA_DEBUG_REGS 8
1218#define NUM_QUEUES 10
1219
1220 u_int32_t val[NUM_DMA_DEBUG_REGS];
1221 int qcu_offset = 0, dcu_offset = 0;
1222 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1223 int i, j, k;
1224 int16_t nfarray[HAL_NUM_NF_READINGS];
1225#ifdef ATH_NF_PER_CHAN
1226 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1227#endif /* ATH_NF_PER_CHAN */
1228 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1229
1230 /* selecting DMA OBS 8 */
1231 OS_REG_WRITE(ah, AR_MACMISC,
1232 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1233 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1234
1235 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1236 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {
1237 if (i % 4 == 0) {
1238 ath_hal_printf(ah, "\n");
1239 }
1240
1241 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1242 ath_hal_printf(ah, "%d: %08x ", i, val[i]);
1243 }
1244
1245 ath_hal_printf(ah, "\n\n");
1246 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1247
1248 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) {
1249 if (i == 8) {
1250 /* only 8 QCU entries in val[0] */
1251 qcu_offset = 0;
1252 qcu_base++;
1253 }
1254
1255 if (i == 6) {
1256 /* only 6 DCU entries in val[4] */
1257 dcu_offset = 0;
1258 dcu_base++;
1259 }
1260
1261 ath_hal_printf(ah,
1262 "%2d %2x %1x %2x %2x\n",
1263 i,
1264 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset,
1265 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3),
1266 val[2] & (0x7 << (i * 3)) >> (i * 3),
1267 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset);
1268 }
1269
1270 ath_hal_printf(ah, "\n");
1271 ath_hal_printf(ah,
1272 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1273 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1274 ath_hal_printf(ah,
1275 "qcu_complete state: %2x dcu_complete state: %2x\n",
1276 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1277 ath_hal_printf(ah,
1278 "dcu_arb state: %2x dcu_fp state: %2x\n",
1279 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1280 ath_hal_printf(ah,
1281 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1282 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1283 ath_hal_printf(ah,
1284 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1285 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1286 ath_hal_printf(ah,
1287 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1288 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1289 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1));
1290 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR));
1291
1292 ar9300_upload_noise_floor(ah, 1, nfarray);
1293 ath_hal_printf(ah, "2G:\n");
1294 ath_hal_printf(ah, "Min CCA Out:\n");
1295 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1296 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1297 nfarray[0], nfarray[1], nfarray[2]);
1298 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1299 nfarray[3], nfarray[4], nfarray[5]);
1300
1301 ar9300_upload_noise_floor(ah, 0, nfarray);
1302 ath_hal_printf(ah, "5G:\n");
1303 ath_hal_printf(ah, "Min CCA Out:\n");
1304 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1305 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1306 nfarray[0], nfarray[1], nfarray[2]);
1307 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1308 nfarray[3], nfarray[4], nfarray[5]);
1309
1310 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1311 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1312 ((i < 3) ? "Control " : "Extension "), i%3);
1313 for (j = 0, k = h->base.curr_index;
1314 j < HAL_NF_CAL_HIST_LEN_FULL;
1315 j++, k++) {
1316 ath_hal_printf(ah, "Element %d: %d\n",
1317 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1318 }
1319 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]);
1320 }
1321
1322 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW);
1323 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n",
1324 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
1325 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
1326 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ);
1327 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n",
1328 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES),
1329 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES));
1330 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n",
1331 MS(reg, AR_PHY_DESIRED_SZ_ADC),
1332 MS(reg, AR_PHY_DESIRED_SZ_ADC));
1333 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG);
1334 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n",
1335 MS(reg, AR_PHY_FIND_SIG_FIRSTEP),
1336 MS(reg, AR_PHY_FIND_SIG_FIRSTEP));
1337 reg = OS_REG_READ(ah, AR_PHY_AGC);
1338 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n",
1339 MS(reg, AR_PHY_AGC_COARSE_HIGH),
1340 MS(reg, AR_PHY_AGC_COARSE_HIGH));
1341 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n",
1342 MS(reg, AR_PHY_AGC_COARSE_LOW),
1343 MS(reg, AR_PHY_AGC_COARSE_LOW));
1344 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n",
1345 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST),
1346 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST));
1347 reg = OS_REG_READ(ah, AR_PHY_TIMING5);
1348 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n",
1349 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE));
1350 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n",
1351 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1),
1352 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1));
1353 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n",
1354 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A),
1355 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A));
1356 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK);
1357 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n",
1358 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR));
1359 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n",
1360 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR),
1361 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR));
1362
1363
1364 /* Step 1a: Set bit 23 of register 0xa360 to 0 */
1365 reg = OS_REG_READ(ah, 0xa360);
1366 reg &= ~0x00800000;
1367 OS_REG_WRITE(ah, 0xa360, reg);
1368
1369 /* Step 2a: Set register 0xa364 to 0x1000 */
1370 reg = 0x1000;
1371 OS_REG_WRITE(ah, 0xa364, reg);
1372
1373 /* Step 3a: Read bits 17:0 of register 0x9c20 */
1374 reg = OS_REG_READ(ah, 0x9c20);
1375 reg &= 0x0003ffff;
1376 ath_hal_printf(ah,
1377 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n",
1378 __func__, reg);
1379
1380 /* Step 1b: Set bit 23 of register 0xa360 to 0 */
1381 reg = OS_REG_READ(ah, 0xa360);
1382 reg &= ~0x00800000;
1383 OS_REG_WRITE(ah, 0xa360, reg);
1384
1385 /* Step 2b: Set register 0xa364 to 0x1400 */
1386 reg = 0x1400;
1387 OS_REG_WRITE(ah, 0xa364, reg);
1388
1389 /* Step 3b: Read bits 17:0 of register 0x9c20 */
1390 reg = OS_REG_READ(ah, 0x9c20);
1391 reg &= 0x0003ffff;
1392 ath_hal_printf(ah,
1393 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n",
1394 __func__, reg);
1395
1396 /* Step 1c: Set bit 23 of register 0xa360 to 0 */
1397 reg = OS_REG_READ(ah, 0xa360);
1398 reg &= ~0x00800000;
1399 OS_REG_WRITE(ah, 0xa360, reg);
1400
1401 /* Step 2c: Set register 0xa364 to 0x3C00 */
1402 reg = 0x3c00;
1403 OS_REG_WRITE(ah, 0xa364, reg);
1404
1405 /* Step 3c: Read bits 17:0 of register 0x9c20 */
1406 reg = OS_REG_READ(ah, 0x9c20);
1407 reg &= 0x0003ffff;
1408 ath_hal_printf(ah,
1409 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n",
1410 __func__, reg);
1411
1412 /* Step 1d: Set bit 24 of register 0xa360 to 0 */
1413 reg = OS_REG_READ(ah, 0xa360);
1414 reg &= ~0x001040000;
1415 OS_REG_WRITE(ah, 0xa360, reg);
1416
1417 /* Step 2d: Set register 0xa364 to 0x5005D */
1418 reg = 0x5005D;
1419 OS_REG_WRITE(ah, 0xa364, reg);
1420
1421 /* Step 3d: Read bits 17:0 of register 0xa368 */
1422 reg = OS_REG_READ(ah, 0xa368);
1423 reg &= 0x0003ffff;
1424 ath_hal_printf(ah,
1425 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n",
1426 __func__, reg);
1427
1428 /* Step 1e: Set bit 24 of register 0xa360 to 0 */
1429 reg = OS_REG_READ(ah, 0xa360);
1430 reg &= ~0x001040000;
1431 OS_REG_WRITE(ah, 0xa360, reg);
1432
1433 /* Step 2e: Set register 0xa364 to 0x7005D */
1434 reg = 0x7005D;
1435 OS_REG_WRITE(ah, 0xa364, reg);
1436
1437 /* Step 3e: Read bits 17:0 of register 0xa368 */
1438 reg = OS_REG_READ(ah, 0xa368);
1439 reg &= 0x0003ffff;
1440 ath_hal_printf(ah,
1441 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n",
1442 __func__, reg);
1443
1444 /* Step 1f: Set bit 24 of register 0xa360 to 0 */
1445 reg = OS_REG_READ(ah, 0xa360);
1446 reg &= ~0x001000000;
1447 reg |= 0x40000;
1448 OS_REG_WRITE(ah, 0xa360, reg);
1449
1450 /* Step 2f: Set register 0xa364 to 0x3005D */
1451 reg = 0x3005D;
1452 OS_REG_WRITE(ah, 0xa364, reg);
1453
1454 /* Step 3f: Read bits 17:0 of register 0xa368 */
1455 reg = OS_REG_READ(ah, 0xa368);
1456 reg &= 0x0003ffff;
1457 ath_hal_printf(ah,
1458 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n",
1459 __func__, reg);
1460
1461 /* Step 1g: Set bit 24 of register 0xa360 to 0 */
1462 reg = OS_REG_READ(ah, 0xa360);
1463 reg &= ~0x001000000;
1464 reg |= 0x40000;
1465 OS_REG_WRITE(ah, 0xa360, reg);
1466
1467 /* Step 2g: Set register 0xa364 to 0x6005D */
1468 reg = 0x6005D;
1469 OS_REG_WRITE(ah, 0xa364, reg);
1470
1471 /* Step 3g: Read bits 17:0 of register 0xa368 */
1472 reg = OS_REG_READ(ah, 0xa368);
1473 reg &= 0x0003ffff;
1474 ath_hal_printf(ah,
1475 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n",
1476 __func__, reg);
1477#endif /* AH_DEBUG */
1478}
1479
1480/*
1481 * Return the busy for rx_frame, rx_clear, and tx_frame
1482 */
1483u_int32_t
1484ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt,
1485 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt)
1486{
1487 struct ath_hal_9300 *ahp = AH9300(ah);
1488 u_int32_t good = 1;
1489
1490 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT);
1491 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT);
1492 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT);
1493 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
1494
1495 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) {
1496 /*
1497 * Cycle counter wrap (or initial call); it's not possible
1498 * to accurately calculate a value because the registers
1499 * right shift rather than wrap--so punt and return 0.
1500 */
1501 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1502 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1503 good = 0;
1504 } else {
1505 u_int32_t cc_d = cc - ahp->ah_cycles;
1506 u_int32_t rc_d = rc - ahp->ah_rx_clear;
1507 u_int32_t rf_d = rf - ahp->ah_rx_frame;
1508 u_int32_t tf_d = tf - ahp->ah_tx_frame;
1509
1510 if (cc_d != 0) {
1511 *rxc_pcnt = rc_d * 100 / cc_d;
1512 *rxf_pcnt = rf_d * 100 / cc_d;
1513 *txf_pcnt = tf_d * 100 / cc_d;
1514 } else {
1515 good = 0;
1516 }
1517 }
1518
1519 ahp->ah_cycles = cc;
1520 ahp->ah_rx_frame = rf;
1521 ahp->ah_rx_clear = rc;
1522 ahp->ah_tx_frame = tf;
1523
1524 return good;
1525}
1526
1527/*
1528 * Return approximation of extension channel busy over an time interval
1529 * 0% (clear) -> 100% (busy)
1530 * -1 for invalid estimate
1531 */
1532uint32_t
1533ar9300_get_11n_ext_busy(struct ath_hal *ah)
1534{
1535 /*
1536 * Overflow condition to check before multiplying to get %
1537 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1538 */
1539#define OVERFLOW_LIMIT 0x28F5C28
1540#define ERROR_CODE -1
1541
1542 struct ath_hal_9300 *ahp = AH9300(ah);
1543 u_int32_t busy = 0; /* percentage */
1544 int8_t busyper = 0;
1545 u_int32_t cycle_count, ctl_busy, ext_busy;
1546
1547 /* cycle_count will always be the first to wrap; therefore, read it last
1548 * This sequence of reads is not atomic, and MIB counter wrap
1549 * could happen during it ?
1550 */
1551 ctl_busy = OS_REG_READ(ah, AR_RCCNT);
1552 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT);
1553 cycle_count = OS_REG_READ(ah, AR_CCCNT);
1554
1555 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) ||
1556 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy))
1557 {
1558 /*
1559 * Cycle counter wrap (or initial call); it's not possible
1560 * to accurately calculate a value because the registers
1561 * right shift rather than wrap--so punt and return 0.
1562 */
1563 busyper = ERROR_CODE;
1564 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1565 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1566 } else {
1567 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count;
1568 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy;
1569
1570 /*
1571 * Compute extension channel busy percentage
1572 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100
1573 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0
1574 * Will never happen, since (ext_busy_delta < cycle_delta) always,
1575 * and shift necessitated by large ext_busy_delta.
1576 * Due to timing difference to read the registers and counter overflow,
1577 * it may still happen that cycle_delta >> 7 = 0.
1578 *
1579 */
1580 if (cycle_delta) {
1581 if (ext_busy_delta > OVERFLOW_LIMIT) {
1582 if (cycle_delta >> 7) {
1583 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7);
1584 } else {
1585 busyper = ERROR_CODE;
1586 }
1587 } else {
1588 busy = (ext_busy_delta * 100) / cycle_delta;
1589 }
1590 } else {
1591 busyper = ERROR_CODE;
1592 }
1593
1594 if (busy > 100) {
1595 busy = 100;
1596 }
1597 if ( busyper != ERROR_CODE ) {
1598 busyper = busy;
1599 }
1600 }
1601
1602 ahp->ah_cycle_count = cycle_count;
1603 ahp->ah_ctl_busy = ctl_busy;
1604 ahp->ah_ext_busy = ext_busy;
1605
1606 return busyper;
1607#undef OVERFLOW_LIMIT
1608#undef ERROR_CODE
1609}
1610
1611/* BB Panic Watchdog declarations */
1612#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1613#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1614
1615void
1616ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1617{
1618#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1619 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1620 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1621 u_int32_t val, idle_count;
1622
1623 if (idle_tmo_ms != 0) {
1624 /* enable IRQ, disable chip-reset for BB panic */
1625 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1626 AR_PHY_BB_PANIC_CNTL2_MASK;
1627 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1628 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1629 /* bound limit to 10 secs */
1630 if (idle_tmo_ms > 10000) {
1631 idle_tmo_ms = 10000;
1632 }
1633 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1634 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1635 } else {
1636 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1637 }
1638 /*
1639 * enable panic in non-IDLE mode,
1640 * disable in IDLE mode,
1641 * set idle time-out
1642 */
1643
1644 // EV92527 : Enable IDLE mode panic
1645
1646 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1647 AR_PHY_BB_PANIC_NON_IDLE_ENABLE |
1648 AR_PHY_BB_PANIC_IDLE_ENABLE |
1649 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) |
1650 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2)));
1651 } else {
1652 /* disable IRQ, disable chip-reset for BB panic */
1653 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1654 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1655 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1656 /* disable panic in non-IDLE mode, disable in IDLE mode */
1657 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1658 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1659 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1660 }
1661
1662 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1663 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1664#undef HAL_BB_PANIC_IDLE_TIME_OUT
1665}
1666
1667
1668void
1669ar9300_handle_bb_panic(struct ath_hal *ah)
1670{
1671 u_int32_t status;
1672 /*
1673 * we want to avoid printing in ISR context so we save
1674 * panic watchdog status to be printed later in DPC context
1675 */
1676 AH9300(ah)->ah_bb_panic_last_status = status =
1677 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1678 /*
1679 * panic watchdog timer should reset on status read
1680 * but to make sure we write 0 to the watchdog status bit
1681 */
1682 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1683}
1684
1685int
1686ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1687{
1688 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1689
1690 /*
1691 * For signature 04000539 do not print anything.
1692 * This is a very common occurence as a compromise between
1693 * BB Panic and AH_FALSE detects (EV71009). It indicates
1694 * radar hang, which can be cleared by reprogramming
1695 * radar related register and does not requre a chip reset
1696 */
1697
1698 /* Suppress BB Status mesg following signature */
1699 switch (bb_panic->status) {
| 1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "opt_ah.h"
18
19#include "ah.h"
20#include "ah_internal.h"
21#include "ah_devid.h"
22#ifdef AH_DEBUG
23#include "ah_desc.h" /* NB: for HAL_PHYERR* */
24#endif
25
26#include "ar9300/ar9300.h"
27#include "ar9300/ar9300reg.h"
28#include "ar9300/ar9300phy.h"
29
30
31void
32ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs)
33{
34 struct ath_hal_9300 *ahp = AH9300(ah);
35 *hangs = 0;
36
37 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) {
38 *hangs |= HAL_RIFS_BB_HANG_WAR;
39 }
40 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) {
41 *hangs |= HAL_DFS_BB_HANG_WAR;
42 }
43 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL)
44 == HAL_OK)
45 {
46 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR;
47 }
48 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) {
49 *hangs |= HAL_MAC_HANG_WAR;
50 }
51 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
52 == HAL_OK)
53 {
54 *hangs |= HAL_PHYRESTART_CLR_WAR;
55 }
56
57 ahp->ah_hang_wars = *hangs;
58}
59
60/*
61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
62 * HT20, HT40, fast-clock, turbo mode, etc.
63 */
64static u_int
65ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
66{
67#if 0
68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
69
70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71 return (ath_hal_mac_usec(ah, clks) / 2);
72 } else {
73 return (ath_hal_mac_usec(ah, clks));
74 }
75#endif
76 return (ath_hal_mac_usec(ah, clks));
77}
78
79u_int
80ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
81{
82#if 0
83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
84
85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
86 return (ath_hal_mac_clks(ah, usecs) * 2);
87 } else {
88 return (ath_hal_mac_clks(ah, usecs));
89 }
90#endif
91 return (ath_hal_mac_clks(ah, usecs));
92}
93
94void
95ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
96{
97 struct ath_hal_9300 *ahp = AH9300(ah);
98
99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
100}
101
102HAL_BOOL
103ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac)
104{
105 struct ath_hal_9300 *ahp = AH9300(ah);
106
107 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
108 return AH_TRUE;
109}
110
111void
112ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask)
113{
114 struct ath_hal_9300 *ahp = AH9300(ah);
115
116 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN);
117}
118
119HAL_BOOL
120ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask)
121{
122 struct ath_hal_9300 *ahp = AH9300(ah);
123
124 /* save it since it must be rewritten on reset */
125 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN);
126
127 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
128 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
129 return AH_TRUE;
130}
131
132/*
133 * Attempt to change the cards operating regulatory domain to the given value
134 * Returns: A_EINVAL for an unsupported regulatory domain.
135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
136 */
137HAL_BOOL
138ar9300_set_regulatory_domain(struct ath_hal *ah,
139 u_int16_t reg_domain, HAL_STATUS *status)
140{
141 HAL_STATUS ecode;
142
143 if (AH_PRIVATE(ah)->ah_currentRD == 0) {
144 AH_PRIVATE(ah)->ah_currentRD = reg_domain;
145 return AH_TRUE;
146 }
147 ecode = HAL_EIO;
148
149#if 0
150bad:
151#endif
152 if (status) {
153 *status = ecode;
154 }
155 return AH_FALSE;
156}
157
158/*
159 * Return the wireless modes (a,b,g,t) supported by hardware.
160 *
161 * This value is what is actually supported by the hardware
162 * and is unaffected by regulatory/country code settings.
163 *
164 */
165u_int
166ar9300_get_wireless_modes(struct ath_hal *ah)
167{
168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
169}
170
171/*
172 * Set the interrupt and GPIO values so the ISR can disable RF
173 * on a switch signal. Assumes GPIO port and interrupt polarity
174 * are set prior to call.
175 */
176void
177ar9300_enable_rf_kill(struct ath_hal *ah)
178{
179 /* TODO - can this really be above the hal on the GPIO interface for
180 * TODO - the client only?
181 */
182 struct ath_hal_9300 *ahp = AH9300(ah);
183
184 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
185 /* Check RF kill GPIO before set/clear RFSILENT bits. */
186 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) {
187 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
188 AR_RFSILENT_FORCE);
189 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
190 }
191 else {
192 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
193 AR_RFSILENT_FORCE);
194 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
195 }
196 }
197 else {
198 /* Connect rfsilent_bb_l to baseband */
199 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
200 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
201
202 /* Set input mux for rfsilent_bb_l to GPIO #0 */
203 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
204 AR_GPIO_INPUT_MUX2_RFSILENT);
205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206 (ahp->ah_gpio_select & 0x0f) << 4);
207
208 /*
209 * Configure the desired GPIO port for input and
210 * enable baseband rf silence
211 */
212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
214 }
215
216 /*
217 * If radio disable switch connection to GPIO bit x is enabled
218 * program GPIO interrupt.
219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
220 * verified that it is a later version of eeprom, it has a place for
221 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
222 * connection is present.
223 */
224 /*
225 * RFKill uses polling not interrupt,
226 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue
227 */
228 if (ath_hal_hasrfkill_int(ah)) {
229 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) {
230 /* switch already closed, set to interrupt upon open */
231 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit);
232 } else {
233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit);
234 }
235 }
236}
237
238/*
239 * Change the LED blinking pattern to correspond to the connectivity
240 */
241void
242ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state)
243{
244 static const u_int32_t ledbits[8] = {
245 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */
246 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */
247 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */
248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */
249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */
250 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */
251 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */
252 AR_CFG_LED_ASSOC_NONE,
253 };
254
255 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]);
256}
257
258/*
259 * Sets the Power LED on the cardbus without affecting the Network LED.
260 */
261void
262ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled)
263{
264 u_int32_t val;
265
266 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF;
267 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val);
268}
269
270/*
271 * Sets the Network LED on the cardbus without affecting the Power LED.
272 */
273void
274ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled)
275{
276 u_int32_t val;
277
278 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF;
279 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val);
280}
281
282/*
283 * Change association related fields programmed into the hardware.
284 * Writing a valid BSSID to the hardware effectively enables the hardware
285 * to synchronize its TSF to the correct beacons and receive frames coming
286 * from that BSSID. It is called by the SME JOIN operation.
287 */
288void
289ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
290 u_int16_t assoc_id)
291{
292 struct ath_hal_9300 *ahp = AH9300(ah);
293
294 /* save bssid and assoc_id for restore on reset */
295 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
296 ahp->ah_assoc_id = assoc_id;
297
298 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
299 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
300 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S));
301}
302
303/*
304 * Get the current hardware tsf for stamlme
305 */
306u_int64_t
307ar9300_get_tsf64(struct ath_hal *ah)
308{
309 u_int64_t tsf;
310
311 /* XXX sync multi-word read? */
312 tsf = OS_REG_READ(ah, AR_TSF_U32);
313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
314 return tsf;
315}
316
317void
318ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf)
319{
320 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff));
321 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff));
322}
323
324/*
325 * Get the current hardware tsf for stamlme
326 */
327u_int32_t
328ar9300_get_tsf32(struct ath_hal *ah)
329{
330 return OS_REG_READ(ah, AR_TSF_L32);
331}
332
333u_int32_t
334ar9300_get_tsf2_32(struct ath_hal *ah)
335{
336 return OS_REG_READ(ah, AR_TSF2_L32);
337}
338
339/*
340 * Reset the current hardware tsf for stamlme.
341 */
342void
343ar9300_reset_tsf(struct ath_hal *ah)
344{
345 int count;
346
347 count = 0;
348 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
349 count++;
350 if (count > 10) {
351 HALDEBUG(ah, HAL_DEBUG_RESET,
352 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__);
353 break;
354 }
355 OS_DELAY(10);
356 }
357 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
358}
359
360/*
361 * Set or clear hardware basic rate bit
362 * Set hardware basic rate set if basic rate is found
363 * and basic rate is equal or less than 2Mbps
364 */
365void
366ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
367{
368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
369 u_int32_t reg;
370 u_int8_t xset;
371 int i;
372
373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
374 return;
375 }
376 xset = 0;
377 for (i = 0; i < rs->rs_count; i++) {
378 u_int8_t rset = rs->rs_rates[i];
379 /* Basic rate defined? */
380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
381 xset = rset;
382 }
383 }
384 /*
385 * Set the h/w bit to reflect whether or not the basic
386 * rate is found to be equal or less than 2Mbps.
387 */
388 reg = OS_REG_READ(ah, AR_STA_ID1);
389 if (xset && xset / 2 <= 2) {
390 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
391 } else {
392 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
393 }
394}
395
396/*
397 * Grab a semi-random value from hardware registers - may not
398 * change often
399 */
400u_int32_t
401ar9300_get_random_seed(struct ath_hal *ah)
402{
403 u_int32_t nf;
404
405 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
406 if (nf & 0x100) {
407 nf = 0 - ((nf ^ 0x1ff) + 1);
408 }
409 return (OS_REG_READ(ah, AR_TSF_U32) ^
410 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
411}
412
413/*
414 * Detect if our card is present
415 */
416HAL_BOOL
417ar9300_detect_card_present(struct ath_hal *ah)
418{
419 u_int16_t mac_version, mac_rev;
420 u_int32_t v;
421
422 /*
423 * Read the Silicon Revision register and compare that
424 * to what we read at attach time. If the same, we say
425 * a card/device is present.
426 */
427 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID;
428 if (v == 0xFF) {
429 /* new SREV format */
430 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
431 /*
432 * Include 6-bit Chip Type (masked to 0) to differentiate
433 * from pre-Sowl versions
434 */
435 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
436 mac_rev = MS(v, AR_SREV_REVISION2);
437 } else {
438 mac_version = MS(v, AR_SREV_VERSION);
439 mac_rev = v & AR_SREV_REVISION;
440 }
441 return (AH_PRIVATE(ah)->ah_macVersion == mac_version &&
442 AH_PRIVATE(ah)->ah_macRev == mac_rev);
443}
444
445/*
446 * Update MIB Counters
447 */
448void
449ar9300_update_mib_mac_stats(struct ath_hal *ah)
450{
451 struct ath_hal_9300 *ahp = AH9300(ah);
452 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats;
453
454 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
455 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
456 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
457 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
458 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
459}
460
461void
462ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats)
463{
464 struct ath_hal_9300 *ahp = AH9300(ah);
465 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats;
466
467 stats->ackrcv_bad = istats->ackrcv_bad;
468 stats->rts_bad = istats->rts_bad;
469 stats->fcs_bad = istats->fcs_bad;
470 stats->rts_good = istats->rts_good;
471 stats->beacons = istats->beacons;
472}
473
474/*
475 * Detect if the HW supports spreading a CCK signal on channel 14
476 */
477HAL_BOOL
478ar9300_is_japan_channel_spread_supported(struct ath_hal *ah)
479{
480 return AH_TRUE;
481}
482
483/*
484 * Get the rssi of frame curently being received.
485 */
486u_int32_t
487ar9300_get_cur_rssi(struct ath_hal *ah)
488{
489 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */
490 /* get combined RSSI */
491 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff);
492}
493
494#if ATH_GEN_RANDOMNESS
495/*
496 * Get the rssi value from BB on ctl chain0.
497 */
498u_int32_t
499ar9300_get_rssi_chain0(struct ath_hal *ah)
500{
501 /* get ctl chain0 RSSI */
502 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff;
503}
504#endif
505
506u_int
507ar9300_get_def_antenna(struct ath_hal *ah)
508{
509 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
510}
511
512/* Setup coverage class */
513void
514ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now)
515{
516}
517
518void
519ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
520{
521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
522}
523
524HAL_BOOL
525ar9300_set_antenna_switch(struct ath_hal *ah,
526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
528{
529 struct ath_hal_9300 *ahp = AH9300(ah);
530
531 /*
532 * Owl does not support diversity or changing antennas.
533 *
534 * Instead this API and function are defined differently for AR9300.
535 * To support Tablet PC's, this interface allows the system
536 * to dramatically reduce the TX power on a particular chain.
537 *
538 * Based on the value of (redefined) diversity_control, the
539 * reset code will decrease power on chain 0 or chain 1/2.
540 *
541 * Based on the value of bit 0 of antenna_switch_swap,
542 * the mapping between OID call and chain is defined as:
543 * 0: map A -> 0, B -> 1;
544 * 1: map A -> 1, B -> 0;
545 *
546 * NOTE:
547 * The devices that use this OID should use a tx_chain_mask and
548 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is
549 * used in order to ensure an active transmit antenna. This
550 * API will allow the host to turn off the only transmitting
551 * antenna to ensure the antenna closest to the user's body is
552 * powered-down.
553 */
554 /*
555 * Set antenna control for use during reset sequence by
556 * ar9300_decrease_chain_power()
557 */
558 ahp->ah_diversity_control = settings;
559
560 return AH_TRUE;
561}
562
563HAL_BOOL
564ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah)
565{
566 return AH_TRUE;
567}
568
569HAL_BOOL
570ar9300_set_slot_time(struct ath_hal *ah, u_int us)
571{
572 struct ath_hal_9300 *ahp = AH9300(ah);
573 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) {
574 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us);
575 ahp->ah_slot_time = (u_int) -1; /* restore default handling */
576 return AH_FALSE;
577 } else {
578 /* convert to system clocks */
579 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us));
580 ahp->ah_slot_time = us;
581 return AH_TRUE;
582 }
583}
584
585HAL_BOOL
586ar9300_set_ack_timeout(struct ath_hal *ah, u_int us)
587{
588 struct ath_hal_9300 *ahp = AH9300(ah);
589
590 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
591 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us);
592 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */
593 return AH_FALSE;
594 } else {
595 /* convert to system clocks */
596 OS_REG_RMW_FIELD(ah,
597 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us));
598 ahp->ah_ack_timeout = us;
599 return AH_TRUE;
600 }
601}
602
603u_int
604ar9300_get_ack_timeout(struct ath_hal *ah)
605{
606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
608}
609
610HAL_STATUS
611ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
612 u_int32_t next_start, HAL_QUIET_FLAG flag)
613{
614#define TU_TO_USEC(_tu) ((_tu) << 10)
615 HAL_STATUS status = HAL_EIO;
616 u_int32_t tsf = 0, j, next_start_us = 0;
617 if (flag & HAL_QUIET_ENABLE) {
618 for (j = 0; j < 2; j++) {
619 next_start_us = TU_TO_USEC(next_start);
620 tsf = OS_REG_READ(ah, AR_TSF_L32);
621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
622 next_start_us += tsf;
623 }
624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
625 next_start_us +=
626 ah->ah_config.ah_sw_beacon_response_time;
627 }
628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
634 status = HAL_OK;
635 break;
636 }
637 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved "
638 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf);
639 /* TSF shouldn't count twice or reg access is taking forever */
640 HALASSERT(j < 1);
641 }
642 } else {
643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
644 status = HAL_OK;
645 }
646
647 return status;
648#undef TU_TO_USEC
649}
650#ifdef ATH_SUPPORT_DFS
651void
652ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
653{
654 u32 reg1, reg2;
655
656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));
657 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1));
658 AH9300(ah)->ah_cac_quiet_enabled = enable;
659
660 if (enable) {
661 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
662 reg1 | AR_PCU_FORCE_QUIET_COLL);
663 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
664 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE);
665 } else {
666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
667 reg1 & ~AR_PCU_FORCE_QUIET_COLL);
668 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
669 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE);
670 }
671}
672#endif /* ATH_SUPPORT_DFS */
673
674void
675ar9300_set_pcu_config(struct ath_hal *ah)
676{
677 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode);
678}
679
680HAL_STATUS
681ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
682 u_int32_t capability, u_int32_t *result)
683{
684 struct ath_hal_9300 *ahp = AH9300(ah);
685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
686
687 switch (type) {
688 case HAL_CAP_CIPHER: /* cipher handled in hardware */
689 switch (capability) {
690 case HAL_CIPHER_AES_CCM:
691 case HAL_CIPHER_AES_OCB:
692 case HAL_CIPHER_TKIP:
693 case HAL_CIPHER_WEP:
694 case HAL_CIPHER_MIC:
695 case HAL_CIPHER_CLR:
696 return HAL_OK;
697 default:
698 return HAL_ENOTSUPP;
699 }
700 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
701 switch (capability) {
702 case 0: /* hardware capability */
703 return HAL_OK;
704 case 1:
705 return (ahp->ah_sta_id1_defaults &
706 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
707 default:
708 return HAL_ENOTSUPP;
709 }
710 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
711 switch (capability) {
712 case 0: /* hardware capability */
713 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
714 case 1: /* current setting */
715 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
716 HAL_ENXIO : HAL_OK;
717 default:
718 return HAL_ENOTSUPP;
719 }
720 case HAL_CAP_WME_TKIPMIC:
721 /* hardware can do TKIP MIC when WMM is turned on */
722 return HAL_OK;
723 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
724 return HAL_OK;
725 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
726 switch (capability) {
727 case 0: /* hardware capability */
728 return HAL_OK;
729 case 1: /* current setting */
730 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) &
731 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
732 HAL_OK : HAL_ENXIO;
733 }
734 return HAL_EINVAL;
735 case HAL_CAP_TPC:
736 switch (capability) {
737 case 0: /* hardware capability */
738 return HAL_OK;
739 case 1:
740 return ah->ah_config.ath_hal_desc_tpc ?
741 HAL_OK : HAL_ENXIO;
742 }
743 return HAL_OK;
744 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
745 return HAL_OK;
746 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
747 switch (capability) {
748 case 0: /* hardware capability */
749 return HAL_OK;
750 case 1:
751 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
752 /*
753 * Owl and Merlin have problems in mcast key search.
754 * Disable this cap. in Ad-hoc mode. see Bug 25776 and
755 * 26802
756 */
757 return HAL_ENXIO;
758 } else {
759 return (ahp->ah_sta_id1_defaults &
760 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
761 }
762 }
763 return HAL_EINVAL;
764 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
765 switch (capability) {
766 case 0: /* hardware capability */
767 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
768 case 1:
769 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
770 HAL_OK : HAL_ENXIO;
771 }
772 return HAL_EINVAL;
773 case HAL_CAP_RFSILENT: /* rfsilent support */
774 if (capability == 3) { /* rfkill interrupt */
775 /*
776 * XXX: Interrupt-based notification of RF Kill state
777 * changes not working yet. Report that this feature
778 * is not supported so that polling is used instead.
779 */
780 return (HAL_ENOTSUPP);
781 }
782 return ath_hal_getcapability(ah, type, capability, result);
783 case HAL_CAP_4ADDR_AGGR:
784 return HAL_OK;
785 case HAL_CAP_BB_RIFS_HANG:
786 return HAL_ENOTSUPP;
787 case HAL_CAP_BB_DFS_HANG:
788 return HAL_ENOTSUPP;
789 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG:
790 /* Track chips that are known to have BB hangs related
791 * to rx_clear stuck low.
792 */
793 return HAL_ENOTSUPP;
794 case HAL_CAP_MAC_HANG:
795 /* Track chips that are known to have MAC hangs.
796 */
797 return HAL_OK;
798 case HAL_CAP_RIFS_RX_ENABLED:
799 /* Is RIFS RX currently enabled */
800 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
801#if 0
802 case HAL_CAP_ANT_CFG_2GHZ:
803 *result = p_cap->halNumAntCfg2Ghz;
804 return HAL_OK;
805 case HAL_CAP_ANT_CFG_5GHZ:
806 *result = p_cap->halNumAntCfg5Ghz;
807 return HAL_OK;
808 case HAL_CAP_RX_STBC:
809 *result = p_cap->hal_rx_stbc_support;
810 return HAL_OK;
811 case HAL_CAP_TX_STBC:
812 *result = p_cap->hal_tx_stbc_support;
813 return HAL_OK;
814#endif
815 case HAL_CAP_LDPC:
816 *result = p_cap->halLDPCSupport;
817 return HAL_OK;
818 case HAL_CAP_DYNAMIC_SMPS:
819 return HAL_OK;
820 case HAL_CAP_DS:
821 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
822 (p_cap->halTxChainMask & 0x3) != 0x3 ||
823 (p_cap->halRxChainMask & 0x3) != 0x3) ?
824 HAL_ENOTSUPP : HAL_OK;
825 case HAL_CAP_TS:
826 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
827 (p_cap->halTxChainMask & 0x7) != 0x7 ||
828 (p_cap->halRxChainMask & 0x7) != 0x7) ?
829 HAL_ENOTSUPP : HAL_OK;
830 case HAL_CAP_OL_PWRCTRL:
831 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
832 HAL_OK : HAL_ENOTSUPP;
833 case HAL_CAP_CRDC:
834#if ATH_SUPPORT_CRDC
835 return (AR_SREV_WASP(ah) &&
836 ah->ah_config.ath_hal_crdc_enable) ?
837 HAL_OK : HAL_ENOTSUPP;
838#else
839 return HAL_ENOTSUPP;
840#endif
841#if 0
842 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
843 *result = (u_int32_t)(-1);
844 return HAL_OK;
845 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
846 *result = (u_int32_t)(-1);
847 return HAL_OK;
848#endif
849 case HAL_CAP_BB_PANIC_WATCHDOG:
850 return HAL_OK;
851 case HAL_CAP_PHYRESTART_CLR_WAR:
852 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
853 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
854 {
855 return HAL_OK;
856 }
857 else
858 {
859 return HAL_ENOTSUPP;
860 }
861 case HAL_CAP_ENTERPRISE_MODE:
862 *result = ahp->ah_enterprise_mode >> 16;
863 /*
864 * WAR for EV 77658 - Add delimiters to first sub-frame when using
865 * RTS/CTS with aggregation and non-enterprise Osprey.
866 *
867 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
868 */
869 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
870 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
871 AR_SREV_WASP_10(ah))) {
872 *result |= AH_ENT_RTSCTS_DELIM_WAR;
873 }
874 return HAL_OK;
875 case HAL_CAP_LDPCWAR:
876 /* WAR for RIFS+LDPC issue is required for all chips currently
877 * supported by ar9300 HAL.
878 */
879 return HAL_OK;
880 case HAL_CAP_ENABLE_APM:
881 *result = p_cap->halApmEnable;
882 return HAL_OK;
883 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
884 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
885 case HAL_CAP_PCIE_LCR_OFFSET:
886 *result = p_cap->hal_pcie_lcr_offset;
887 return HAL_OK;
888 case HAL_CAP_SMARTANTENNA:
889 /* FIXME A request is pending with h/w team to add feature bit in
890 * caldata to detect if board has smart antenna or not, once added
891 * we need to fix his piece of code to read and return value without
892 * any compile flags
893 */
894#if UMAC_SUPPORT_SMARTANTENNA
895 /* enable smart antenna for Peacock, Wasp and scorpion
896 for future chips need to modify */
897 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) {
898 return HAL_OK;
899 } else {
900 return HAL_ENOTSUPP;
901 }
902#else
903 return HAL_ENOTSUPP;
904#endif
905
906#ifdef ATH_TRAFFIC_FAST_RECOVER
907 case HAL_CAP_TRAFFIC_FAST_RECOVER:
908 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) {
909 return HAL_OK;
910 } else {
911 return HAL_ENOTSUPP;
912 }
913#endif
914 default:
915 return ath_hal_getcapability(ah, type, capability, result);
916 }
917}
918
919HAL_BOOL
920ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
921 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
922{
923 struct ath_hal_9300 *ahp = AH9300(ah);
924 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
925 u_int32_t v;
926
927 switch (type) {
928 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
929 if (! p_cap->halTkipMicTxRxKeySupport)
930 return AH_FALSE;
931
932 if (setting)
933 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
934 else
935 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
936
937 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
938 return AH_TRUE;
939
940 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
941 if (setting) {
942 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
943 } else {
944 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
945 }
946 return AH_TRUE;
947 case HAL_CAP_DIVERSITY:
948 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
949 if (setting) {
950 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
951 } else {
952 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
953 }
954 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
955 return AH_TRUE;
956 case HAL_CAP_DIAG: /* hardware diagnostic support */
957 /*
958 * NB: could split this up into virtual capabilities,
959 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
960 * seems worth the additional complexity.
961 */
962#ifdef AH_DEBUG
963 AH_PRIVATE(ah)->ah_diagreg = setting;
964#else
965 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
966#endif
967 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
968 return AH_TRUE;
969 case HAL_CAP_TPC:
970 ah->ah_config.ath_hal_desc_tpc = (setting != 0);
971 return AH_TRUE;
972 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
973 if (setting) {
974 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
975 } else {
976 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
977 }
978 return AH_TRUE;
979 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
980 if (p_cap->halTsfAddSupport) {
981 if (setting) {
982 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
983 } else {
984 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
985 }
986 return AH_TRUE;
987 }
988 return AH_FALSE;
989 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */
990 ahp->rx_buf_size = setting & AR_DATABUF_MASK;
991 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
992 return AH_TRUE;
993
994 /* fall thru... */
995 default:
996 return ath_hal_setcapability(ah, type, capability, setting, status);
997 }
998}
999
1000#ifdef AH_DEBUG
1001static void
1002ar9300_print_reg(struct ath_hal *ah, u_int32_t args)
1003{
1004 u_int32_t i = 0;
1005
1006 /* Read 0x80d0 to trigger pcie analyzer */
1007 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1008 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0));
1009
1010 if (args & HAL_DIAG_PRINT_REG_COUNTER) {
1011 struct ath_hal_9300 *ahp = AH9300(ah);
1012 u_int32_t tf, rf, rc, cc;
1013
1014 tf = OS_REG_READ(ah, AR_TFCNT);
1015 rf = OS_REG_READ(ah, AR_RFCNT);
1016 rc = OS_REG_READ(ah, AR_RCCNT);
1017 cc = OS_REG_READ(ah, AR_CCCNT);
1018
1019 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1020 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf);
1021 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1022 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf);
1023 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1024 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc);
1025 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1026 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc);
1027
1028 ahp->last_tf = tf;
1029 ahp->last_rf = rf;
1030 ahp->last_rc = rc;
1031 ahp->last_cc = cc;
1032
1033 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1034 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0));
1035 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1036 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1));
1037 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1038 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2));
1039 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1040 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3));
1041 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1042 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4));
1043 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1044 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5));
1045 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1046 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6));
1047 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1048 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7));
1049 }
1050
1051 if (args & HAL_DIAG_PRINT_REG_ALL) {
1052 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) {
1053 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1054 i, OS_REG_READ(ah, i));
1055 }
1056
1057 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) {
1058 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1059 i, OS_REG_READ(ah, i));
1060 }
1061
1062 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1063 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i));
1064
1065 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1066 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i));
1067
1068 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) {
1069 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1070 i, OS_REG_READ(ah, i));
1071 }
1072
1073 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) {
1074 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1075 i, OS_REG_READ(ah, i));
1076 }
1077
1078 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) {
1079 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1080 i, OS_REG_READ(ah, i));
1081 }
1082
1083 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) {
1084 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1085 i, OS_REG_READ(ah, i));
1086 }
1087
1088 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) {
1089 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1090 i, OS_REG_READ(ah, i));
1091 }
1092
1093 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) {
1094 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1095 i, OS_REG_READ(ah, i));
1096 }
1097
1098 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) {
1099 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1100 i, OS_REG_READ(ah, i));
1101 }
1102
1103 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) {
1104 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1105 i, OS_REG_READ(ah, i));
1106 }
1107
1108 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) {
1109 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1110 i, OS_REG_READ(ah, i));
1111 }
1112
1113 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) {
1114 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1115 i, OS_REG_READ(ah, i));
1116 }
1117
1118 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) {
1119 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1120 i, OS_REG_READ(ah, i));
1121 }
1122 }
1123}
1124#endif
1125
1126HAL_BOOL
1127ar9300_get_diag_state(struct ath_hal *ah, int request,
1128 const void *args, u_int32_t argsize,
1129 void **result, u_int32_t *resultsize)
1130{
1131 struct ath_hal_9300 *ahp = AH9300(ah);
1132
1133 (void) ahp;
1134 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) {
1135 return AH_TRUE;
1136 }
1137 switch (request) {
1138#ifdef AH_PRIVATE_DIAG
1139 case HAL_DIAG_EEPROM:
1140 *result = &ahp->ah_eeprom;
1141 *resultsize = sizeof(ar9300_eeprom_t);
1142 return AH_TRUE;
1143
1144#if 0 /* XXX - TODO */
1145 case HAL_DIAG_EEPROM_EXP_11A:
1146 case HAL_DIAG_EEPROM_EXP_11B:
1147 case HAL_DIAG_EEPROM_EXP_11G:
1148 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A];
1149 *result = pe->p_channels;
1150 *resultsize = (*result == AH_NULL) ? 0 :
1151 roundup(sizeof(u_int16_t) * pe->num_channels,
1152 sizeof(u_int32_t)) +
1153 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels;
1154 return AH_TRUE;
1155#endif
1156 case HAL_DIAG_RFGAIN:
1157 *result = &ahp->ah_gain_values;
1158 *resultsize = sizeof(GAIN_VALUES);
1159 return AH_TRUE;
1160 case HAL_DIAG_RFGAIN_CURSTEP:
1161 *result = (void *) ahp->ah_gain_values.curr_step;
1162 *resultsize = (*result == AH_NULL) ?
1163 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1164 return AH_TRUE;
1165#if 0 /* XXX - TODO */
1166 case HAL_DIAG_PCDAC:
1167 *result = ahp->ah_pcdac_table;
1168 *resultsize = ahp->ah_pcdac_table_size;
1169 return AH_TRUE;
1170#endif
1171 case HAL_DIAG_ANI_CURRENT:
1172 *result = ar9300_ani_get_current_state(ah);
1173 *resultsize = (*result == AH_NULL) ?
1174 0 : sizeof(struct ar9300_ani_state);
1175 return AH_TRUE;
1176 case HAL_DIAG_ANI_STATS:
1177 *result = ar9300_ani_get_current_stats(ah);
1178 *resultsize = (*result == AH_NULL) ?
1179 0 : sizeof(struct ar9300_stats);
1180 return AH_TRUE;
1181 case HAL_DIAG_ANI_CMD:
1182 if (argsize != 2*sizeof(u_int32_t)) {
1183 return AH_FALSE;
1184 }
1185 ar9300_ani_control(
1186 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1187 return AH_TRUE;
1188#if 0
1189 case HAL_DIAG_TXCONT:
1190 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1191 return AH_TRUE;
1192#endif /* 0 */
1193#endif /* AH_PRIVATE_DIAG */
1194 case HAL_DIAG_CHANNELS:
1195#if 0
1196 *result = &(ahp->ah_priv.ah_channels[0]);
1197 *resultsize =
1198 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1199#endif
1200 return AH_TRUE;
1201#ifdef AH_DEBUG
1202 case HAL_DIAG_PRINT_REG:
1203 ar9300_print_reg(ah, *((const u_int32_t *)args));
1204 return AH_TRUE;
1205#endif
1206 default:
1207 break;
1208 }
1209
1210 return AH_FALSE;
1211}
1212
1213void
1214ar9300_dma_reg_dump(struct ath_hal *ah)
1215{
1216#ifdef AH_DEBUG
1217#define NUM_DMA_DEBUG_REGS 8
1218#define NUM_QUEUES 10
1219
1220 u_int32_t val[NUM_DMA_DEBUG_REGS];
1221 int qcu_offset = 0, dcu_offset = 0;
1222 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1223 int i, j, k;
1224 int16_t nfarray[HAL_NUM_NF_READINGS];
1225#ifdef ATH_NF_PER_CHAN
1226 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1227#endif /* ATH_NF_PER_CHAN */
1228 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1229
1230 /* selecting DMA OBS 8 */
1231 OS_REG_WRITE(ah, AR_MACMISC,
1232 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1233 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1234
1235 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1236 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {
1237 if (i % 4 == 0) {
1238 ath_hal_printf(ah, "\n");
1239 }
1240
1241 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1242 ath_hal_printf(ah, "%d: %08x ", i, val[i]);
1243 }
1244
1245 ath_hal_printf(ah, "\n\n");
1246 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1247
1248 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) {
1249 if (i == 8) {
1250 /* only 8 QCU entries in val[0] */
1251 qcu_offset = 0;
1252 qcu_base++;
1253 }
1254
1255 if (i == 6) {
1256 /* only 6 DCU entries in val[4] */
1257 dcu_offset = 0;
1258 dcu_base++;
1259 }
1260
1261 ath_hal_printf(ah,
1262 "%2d %2x %1x %2x %2x\n",
1263 i,
1264 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset,
1265 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3),
1266 val[2] & (0x7 << (i * 3)) >> (i * 3),
1267 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset);
1268 }
1269
1270 ath_hal_printf(ah, "\n");
1271 ath_hal_printf(ah,
1272 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1273 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1274 ath_hal_printf(ah,
1275 "qcu_complete state: %2x dcu_complete state: %2x\n",
1276 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1277 ath_hal_printf(ah,
1278 "dcu_arb state: %2x dcu_fp state: %2x\n",
1279 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1280 ath_hal_printf(ah,
1281 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1282 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1283 ath_hal_printf(ah,
1284 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1285 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1286 ath_hal_printf(ah,
1287 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1288 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1289 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1));
1290 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR));
1291
1292 ar9300_upload_noise_floor(ah, 1, nfarray);
1293 ath_hal_printf(ah, "2G:\n");
1294 ath_hal_printf(ah, "Min CCA Out:\n");
1295 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1296 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1297 nfarray[0], nfarray[1], nfarray[2]);
1298 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1299 nfarray[3], nfarray[4], nfarray[5]);
1300
1301 ar9300_upload_noise_floor(ah, 0, nfarray);
1302 ath_hal_printf(ah, "5G:\n");
1303 ath_hal_printf(ah, "Min CCA Out:\n");
1304 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1305 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1306 nfarray[0], nfarray[1], nfarray[2]);
1307 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1308 nfarray[3], nfarray[4], nfarray[5]);
1309
1310 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1311 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1312 ((i < 3) ? "Control " : "Extension "), i%3);
1313 for (j = 0, k = h->base.curr_index;
1314 j < HAL_NF_CAL_HIST_LEN_FULL;
1315 j++, k++) {
1316 ath_hal_printf(ah, "Element %d: %d\n",
1317 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1318 }
1319 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]);
1320 }
1321
1322 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW);
1323 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n",
1324 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
1325 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
1326 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ);
1327 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n",
1328 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES),
1329 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES));
1330 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n",
1331 MS(reg, AR_PHY_DESIRED_SZ_ADC),
1332 MS(reg, AR_PHY_DESIRED_SZ_ADC));
1333 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG);
1334 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n",
1335 MS(reg, AR_PHY_FIND_SIG_FIRSTEP),
1336 MS(reg, AR_PHY_FIND_SIG_FIRSTEP));
1337 reg = OS_REG_READ(ah, AR_PHY_AGC);
1338 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n",
1339 MS(reg, AR_PHY_AGC_COARSE_HIGH),
1340 MS(reg, AR_PHY_AGC_COARSE_HIGH));
1341 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n",
1342 MS(reg, AR_PHY_AGC_COARSE_LOW),
1343 MS(reg, AR_PHY_AGC_COARSE_LOW));
1344 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n",
1345 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST),
1346 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST));
1347 reg = OS_REG_READ(ah, AR_PHY_TIMING5);
1348 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n",
1349 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE));
1350 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n",
1351 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1),
1352 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1));
1353 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n",
1354 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A),
1355 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A));
1356 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK);
1357 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n",
1358 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR));
1359 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n",
1360 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR),
1361 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR));
1362
1363
1364 /* Step 1a: Set bit 23 of register 0xa360 to 0 */
1365 reg = OS_REG_READ(ah, 0xa360);
1366 reg &= ~0x00800000;
1367 OS_REG_WRITE(ah, 0xa360, reg);
1368
1369 /* Step 2a: Set register 0xa364 to 0x1000 */
1370 reg = 0x1000;
1371 OS_REG_WRITE(ah, 0xa364, reg);
1372
1373 /* Step 3a: Read bits 17:0 of register 0x9c20 */
1374 reg = OS_REG_READ(ah, 0x9c20);
1375 reg &= 0x0003ffff;
1376 ath_hal_printf(ah,
1377 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n",
1378 __func__, reg);
1379
1380 /* Step 1b: Set bit 23 of register 0xa360 to 0 */
1381 reg = OS_REG_READ(ah, 0xa360);
1382 reg &= ~0x00800000;
1383 OS_REG_WRITE(ah, 0xa360, reg);
1384
1385 /* Step 2b: Set register 0xa364 to 0x1400 */
1386 reg = 0x1400;
1387 OS_REG_WRITE(ah, 0xa364, reg);
1388
1389 /* Step 3b: Read bits 17:0 of register 0x9c20 */
1390 reg = OS_REG_READ(ah, 0x9c20);
1391 reg &= 0x0003ffff;
1392 ath_hal_printf(ah,
1393 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n",
1394 __func__, reg);
1395
1396 /* Step 1c: Set bit 23 of register 0xa360 to 0 */
1397 reg = OS_REG_READ(ah, 0xa360);
1398 reg &= ~0x00800000;
1399 OS_REG_WRITE(ah, 0xa360, reg);
1400
1401 /* Step 2c: Set register 0xa364 to 0x3C00 */
1402 reg = 0x3c00;
1403 OS_REG_WRITE(ah, 0xa364, reg);
1404
1405 /* Step 3c: Read bits 17:0 of register 0x9c20 */
1406 reg = OS_REG_READ(ah, 0x9c20);
1407 reg &= 0x0003ffff;
1408 ath_hal_printf(ah,
1409 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n",
1410 __func__, reg);
1411
1412 /* Step 1d: Set bit 24 of register 0xa360 to 0 */
1413 reg = OS_REG_READ(ah, 0xa360);
1414 reg &= ~0x001040000;
1415 OS_REG_WRITE(ah, 0xa360, reg);
1416
1417 /* Step 2d: Set register 0xa364 to 0x5005D */
1418 reg = 0x5005D;
1419 OS_REG_WRITE(ah, 0xa364, reg);
1420
1421 /* Step 3d: Read bits 17:0 of register 0xa368 */
1422 reg = OS_REG_READ(ah, 0xa368);
1423 reg &= 0x0003ffff;
1424 ath_hal_printf(ah,
1425 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n",
1426 __func__, reg);
1427
1428 /* Step 1e: Set bit 24 of register 0xa360 to 0 */
1429 reg = OS_REG_READ(ah, 0xa360);
1430 reg &= ~0x001040000;
1431 OS_REG_WRITE(ah, 0xa360, reg);
1432
1433 /* Step 2e: Set register 0xa364 to 0x7005D */
1434 reg = 0x7005D;
1435 OS_REG_WRITE(ah, 0xa364, reg);
1436
1437 /* Step 3e: Read bits 17:0 of register 0xa368 */
1438 reg = OS_REG_READ(ah, 0xa368);
1439 reg &= 0x0003ffff;
1440 ath_hal_printf(ah,
1441 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n",
1442 __func__, reg);
1443
1444 /* Step 1f: Set bit 24 of register 0xa360 to 0 */
1445 reg = OS_REG_READ(ah, 0xa360);
1446 reg &= ~0x001000000;
1447 reg |= 0x40000;
1448 OS_REG_WRITE(ah, 0xa360, reg);
1449
1450 /* Step 2f: Set register 0xa364 to 0x3005D */
1451 reg = 0x3005D;
1452 OS_REG_WRITE(ah, 0xa364, reg);
1453
1454 /* Step 3f: Read bits 17:0 of register 0xa368 */
1455 reg = OS_REG_READ(ah, 0xa368);
1456 reg &= 0x0003ffff;
1457 ath_hal_printf(ah,
1458 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n",
1459 __func__, reg);
1460
1461 /* Step 1g: Set bit 24 of register 0xa360 to 0 */
1462 reg = OS_REG_READ(ah, 0xa360);
1463 reg &= ~0x001000000;
1464 reg |= 0x40000;
1465 OS_REG_WRITE(ah, 0xa360, reg);
1466
1467 /* Step 2g: Set register 0xa364 to 0x6005D */
1468 reg = 0x6005D;
1469 OS_REG_WRITE(ah, 0xa364, reg);
1470
1471 /* Step 3g: Read bits 17:0 of register 0xa368 */
1472 reg = OS_REG_READ(ah, 0xa368);
1473 reg &= 0x0003ffff;
1474 ath_hal_printf(ah,
1475 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n",
1476 __func__, reg);
1477#endif /* AH_DEBUG */
1478}
1479
1480/*
1481 * Return the busy for rx_frame, rx_clear, and tx_frame
1482 */
1483u_int32_t
1484ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt,
1485 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt)
1486{
1487 struct ath_hal_9300 *ahp = AH9300(ah);
1488 u_int32_t good = 1;
1489
1490 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT);
1491 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT);
1492 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT);
1493 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
1494
1495 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) {
1496 /*
1497 * Cycle counter wrap (or initial call); it's not possible
1498 * to accurately calculate a value because the registers
1499 * right shift rather than wrap--so punt and return 0.
1500 */
1501 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1502 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1503 good = 0;
1504 } else {
1505 u_int32_t cc_d = cc - ahp->ah_cycles;
1506 u_int32_t rc_d = rc - ahp->ah_rx_clear;
1507 u_int32_t rf_d = rf - ahp->ah_rx_frame;
1508 u_int32_t tf_d = tf - ahp->ah_tx_frame;
1509
1510 if (cc_d != 0) {
1511 *rxc_pcnt = rc_d * 100 / cc_d;
1512 *rxf_pcnt = rf_d * 100 / cc_d;
1513 *txf_pcnt = tf_d * 100 / cc_d;
1514 } else {
1515 good = 0;
1516 }
1517 }
1518
1519 ahp->ah_cycles = cc;
1520 ahp->ah_rx_frame = rf;
1521 ahp->ah_rx_clear = rc;
1522 ahp->ah_tx_frame = tf;
1523
1524 return good;
1525}
1526
1527/*
1528 * Return approximation of extension channel busy over an time interval
1529 * 0% (clear) -> 100% (busy)
1530 * -1 for invalid estimate
1531 */
1532uint32_t
1533ar9300_get_11n_ext_busy(struct ath_hal *ah)
1534{
1535 /*
1536 * Overflow condition to check before multiplying to get %
1537 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1538 */
1539#define OVERFLOW_LIMIT 0x28F5C28
1540#define ERROR_CODE -1
1541
1542 struct ath_hal_9300 *ahp = AH9300(ah);
1543 u_int32_t busy = 0; /* percentage */
1544 int8_t busyper = 0;
1545 u_int32_t cycle_count, ctl_busy, ext_busy;
1546
1547 /* cycle_count will always be the first to wrap; therefore, read it last
1548 * This sequence of reads is not atomic, and MIB counter wrap
1549 * could happen during it ?
1550 */
1551 ctl_busy = OS_REG_READ(ah, AR_RCCNT);
1552 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT);
1553 cycle_count = OS_REG_READ(ah, AR_CCCNT);
1554
1555 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) ||
1556 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy))
1557 {
1558 /*
1559 * Cycle counter wrap (or initial call); it's not possible
1560 * to accurately calculate a value because the registers
1561 * right shift rather than wrap--so punt and return 0.
1562 */
1563 busyper = ERROR_CODE;
1564 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1565 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1566 } else {
1567 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count;
1568 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy;
1569
1570 /*
1571 * Compute extension channel busy percentage
1572 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100
1573 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0
1574 * Will never happen, since (ext_busy_delta < cycle_delta) always,
1575 * and shift necessitated by large ext_busy_delta.
1576 * Due to timing difference to read the registers and counter overflow,
1577 * it may still happen that cycle_delta >> 7 = 0.
1578 *
1579 */
1580 if (cycle_delta) {
1581 if (ext_busy_delta > OVERFLOW_LIMIT) {
1582 if (cycle_delta >> 7) {
1583 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7);
1584 } else {
1585 busyper = ERROR_CODE;
1586 }
1587 } else {
1588 busy = (ext_busy_delta * 100) / cycle_delta;
1589 }
1590 } else {
1591 busyper = ERROR_CODE;
1592 }
1593
1594 if (busy > 100) {
1595 busy = 100;
1596 }
1597 if ( busyper != ERROR_CODE ) {
1598 busyper = busy;
1599 }
1600 }
1601
1602 ahp->ah_cycle_count = cycle_count;
1603 ahp->ah_ctl_busy = ctl_busy;
1604 ahp->ah_ext_busy = ext_busy;
1605
1606 return busyper;
1607#undef OVERFLOW_LIMIT
1608#undef ERROR_CODE
1609}
1610
1611/* BB Panic Watchdog declarations */
1612#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1613#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1614
1615void
1616ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1617{
1618#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1619 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1620 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1621 u_int32_t val, idle_count;
1622
1623 if (idle_tmo_ms != 0) {
1624 /* enable IRQ, disable chip-reset for BB panic */
1625 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1626 AR_PHY_BB_PANIC_CNTL2_MASK;
1627 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1628 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1629 /* bound limit to 10 secs */
1630 if (idle_tmo_ms > 10000) {
1631 idle_tmo_ms = 10000;
1632 }
1633 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1634 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1635 } else {
1636 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1637 }
1638 /*
1639 * enable panic in non-IDLE mode,
1640 * disable in IDLE mode,
1641 * set idle time-out
1642 */
1643
1644 // EV92527 : Enable IDLE mode panic
1645
1646 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1647 AR_PHY_BB_PANIC_NON_IDLE_ENABLE |
1648 AR_PHY_BB_PANIC_IDLE_ENABLE |
1649 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) |
1650 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2)));
1651 } else {
1652 /* disable IRQ, disable chip-reset for BB panic */
1653 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1654 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1655 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1656 /* disable panic in non-IDLE mode, disable in IDLE mode */
1657 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1658 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1659 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1660 }
1661
1662 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1663 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1664#undef HAL_BB_PANIC_IDLE_TIME_OUT
1665}
1666
1667
1668void
1669ar9300_handle_bb_panic(struct ath_hal *ah)
1670{
1671 u_int32_t status;
1672 /*
1673 * we want to avoid printing in ISR context so we save
1674 * panic watchdog status to be printed later in DPC context
1675 */
1676 AH9300(ah)->ah_bb_panic_last_status = status =
1677 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1678 /*
1679 * panic watchdog timer should reset on status read
1680 * but to make sure we write 0 to the watchdog status bit
1681 */
1682 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1683}
1684
1685int
1686ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1687{
1688 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1689
1690 /*
1691 * For signature 04000539 do not print anything.
1692 * This is a very common occurence as a compromise between
1693 * BB Panic and AH_FALSE detects (EV71009). It indicates
1694 * radar hang, which can be cleared by reprogramming
1695 * radar related register and does not requre a chip reset
1696 */
1697
1698 /* Suppress BB Status mesg following signature */
1699 switch (bb_panic->status) {
|
1704 return -1;
1705 }
1706
1707 bb_panic->tsf = ar9300_get_tsf32(ah);
1708 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS);
1709 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG);
1710 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM);
1711 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM);
1712 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM);
1713 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM);
1714 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM);
1715 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM);
1716 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM);
1717 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1);
1718 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1719 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1720 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1721 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1722 &bb_panic->rxc_pcnt,
1723 &bb_panic->rxf_pcnt,
1724 &bb_panic->txf_pcnt);
1725
1726 if (ah->ah_config.ath_hal_show_bb_panic) {
1727 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1728 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1729 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1730 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1731 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1732 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1733 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1734 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1735 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2);
1736 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n",
1737 bb_panic->phy_gen_ctrl);
1738 if (bb_panic->cycles) {
1739 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, "
1740 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt,
1741 bb_panic->rxf_pcnt, bb_panic->txf_pcnt);
1742 }
1743 ath_hal_printf(ah, "==== BB update: done ====\n\n");
1744 }
1745
1746 return 0; //The returned data will be stored for athstats to retrieve it
1747}
1748
1749/* set the reason for HAL reset */
1750void
1751ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1752{
1753 AH9300(ah)->ah_reset_reason = resetreason;
1754}
1755
1756/*
1757 * Configure 20/40 operation
1758 *
1759 * 20/40 = joint rx clear (control and extension)
1760 * 20 = rx clear (control)
1761 *
1762 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1763 * when changing from 20/40 => 20 only
1764 */
1765void
1766ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1767{
1768 u_int32_t macmode;
1769
1770 /* Configure MAC for 20/40 operation */
1771 if (mode == HAL_HT_MACMODE_2040 &&
1772 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1773 macmode = AR_2040_JOINED_RX_CLEAR;
1774 } else {
1775 macmode = 0;
1776 }
1777 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1778}
1779
1780/*
1781 * Get Rx clear (control/extension channel)
1782 *
1783 * Returns active low (busy) for ctrl/ext channel
1784 * Owl 2.0
1785 */
1786HAL_HT_RXCLEAR
1787ar9300_get_11n_rx_clear(struct ath_hal *ah)
1788{
1789 HAL_HT_RXCLEAR rxclear = 0;
1790 u_int32_t val;
1791
1792 val = OS_REG_READ(ah, AR_DIAG_SW);
1793
1794 /* control channel */
1795 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) {
1796 rxclear |= HAL_RX_CLEAR_CTL_LOW;
1797 }
1798 /* extension channel */
1799 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) {
1800 rxclear |= HAL_RX_CLEAR_EXT_LOW;
1801 }
1802 return rxclear;
1803}
1804
1805/*
1806 * Set Rx clear (control/extension channel)
1807 *
1808 * Useful for forcing the channel to appear busy for
1809 * debugging/diagnostics
1810 * Owl 2.0
1811 */
1812void
1813ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
1814{
1815 /* control channel */
1816 if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
1817 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1818 } else {
1819 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1820 }
1821 /* extension channel */
1822 if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
1823 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1824 } else {
1825 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1826 }
1827}
1828
1829
1830/*
1831 * HAL support code for force ppm tracking workaround.
1832 */
1833
1834u_int32_t
1835ar9300_ppm_get_rssi_dump(struct ath_hal *ah)
1836{
1837 u_int32_t retval;
1838 u_int32_t off1;
1839 u_int32_t off2;
1840
1841 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1842 off1 = 0x2000;
1843 off2 = 0x1000;
1844 } else {
1845 off1 = 0x1000;
1846 off2 = 0x2000;
1847 }
1848
1849 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) |
1850 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) |
1851 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16);
1852
1853 return retval;
1854}
1855
1856u_int32_t
1857ar9300_ppm_force(struct ath_hal *ah)
1858{
1859 u_int32_t data_fine;
1860 u_int32_t data4;
1861 //u_int32_t off1;
1862 //u_int32_t off2;
1863 HAL_BOOL signed_val = AH_FALSE;
1864
1865// if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1866// off1 = 0x2000;
1867// off2 = 0x1000;
1868// } else {
1869// off1 = 0x1000;
1870// off2 = 0x2000;
1871// }
1872 data_fine =
1873 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK &
1874 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF);
1875
1876 /*
1877 * bit [11-0] is new ppm value. bit 11 is the signed bit.
1878 * So check value from bit[10:0].
1879 * Now get the abs val of the ppm value read in bit[0:11].
1880 * After that do bound check on abs value.
1881 * if value is off limit, CAP the value and and restore signed bit.
1882 */
1883 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1884 {
1885 /* get the positive value */
1886 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1887 signed_val = AH_TRUE;
1888 }
1889 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1890 {
1891 HALDEBUG(ah, HAL_DEBUG_REGIO,
1892 "%s Correcting ppm out of range %x\n",
1893 __func__, (data_fine & 0x7ff));
1894 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1895 }
1896 /*
1897 * Restore signed value if changed above.
1898 * Use typecast to avoid compilation errors
1899 */
1900 if (signed_val) {
1901 data_fine = (-(int32_t)data_fine) &
1902 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1903 }
1904
1905 /* write value */
1906 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) &
1907 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1908 OS_REG_WRITE(ah, AR_PHY_TIMING2,
1909 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM);
1910
1911 return data_fine;
1912}
1913
1914void
1915ar9300_ppm_un_force(struct ath_hal *ah)
1916{
1917 u_int32_t data4;
1918
1919 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM;
1920 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4);
1921}
1922
1923u_int32_t
1924ar9300_ppm_arm_trigger(struct ath_hal *ah)
1925{
1926 u_int32_t val;
1927 u_int32_t ret;
1928
1929 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY);
1930 ret = OS_REG_READ(ah, AR_TSF_L32);
1931 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY,
1932 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK);
1933
1934 /* return low word of TSF at arm time */
1935 return ret;
1936}
1937
1938int
1939ar9300_ppm_get_trigger(struct ath_hal *ah)
1940{
1941 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) &
1942 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK)
1943 {
1944 /* has not triggered yet, return AH_FALSE */
1945 return 0;
1946 }
1947
1948 /* else triggered, return AH_TRUE */
1949 return 1;
1950}
1951
1952void
1953ar9300_mark_phy_inactive(struct ath_hal *ah)
1954{
1955 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1956}
1957
1958/* DEBUG */
1959u_int32_t
1960ar9300_ppm_get_force_state(struct ath_hal *ah)
1961{
1962 return
1963 OS_REG_READ(ah, AR_PHY_TIMING2) &
1964 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1965}
1966
1967/*
1968 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
1969 */
1970HAL_BOOL
1971ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
1972{
1973 /*
1974 * XXX FreeBSD todo: reimplement this
1975 */
1976#if 0
1977 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
1978 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
1979 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
1980 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
1981 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
1982 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
1983 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
1984 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
1985#endif
1986 return AH_FALSE;
1987}
1988
1989void
1990ar9300_clear_mib_counters(struct ath_hal *ah)
1991{
1992 u_int32_t reg_val;
1993
1994 reg_val = OS_REG_READ(ah, AR_MIBC);
1995 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
1996 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
1997}
1998
1999
2000/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
2001HAL_BOOL
2002ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2003{
2004 struct ath_hal_9300 *ahp = AH9300(ah);
2005 HAL_CHANNEL_INTERNAL *ichan =
2006 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2007 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2008 u_int32_t tmp = 0;
2009
2010 if (enable) {
2011 if (ahp->ah_rifs_enabled == AH_TRUE) {
2012 return AH_TRUE;
2013 }
2014
2015 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2016 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2017 ahp->ah_rifs_reg[1]);
2018
2019 ahp->ah_rifs_enabled = AH_TRUE;
2020 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg));
2021 } else {
2022 if (ahp->ah_rifs_enabled == AH_TRUE) {
2023 ahp->ah_rifs_reg[0] = OS_REG_READ(ah,
2024 AR_PHY_SEARCH_START_DELAY);
2025 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2026 }
2027 /* Change rifs init delay to 0 */
2028 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2029 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2030 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2031 if (is_chan_2g) {
2032 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2033 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2034 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2035 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2036 }
2037 } else {
2038 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2039 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2040 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2041 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2042 }
2043 }
2044
2045 ahp->ah_rifs_enabled = AH_FALSE;
2046 }
2047 return AH_TRUE;
2048
2049} /* ar9300_set_rifs_delay () */
2050
2051/* Set the current RIFS Rx setting */
2052HAL_BOOL
2053ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable)
2054{
2055 /* Non-Owl 11n chips */
2056 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) {
2057 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) {
2058 return ar9300_set_rifs_delay(ah, enable);
2059 }
2060 return AH_FALSE;
2061 }
2062
2063 return AH_TRUE;
2064} /* ar9300_set_11n_rx_rifs () */
2065
2066static hal_mac_hangs_t
2067ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg,
2068 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain)
2069{
2070 int i = 0;
2071 hal_mac_hangs_t found_hangs = 0;
2072
2073 if (hangs & dcu_chain_state) {
2074 for (i = 0; i < 6; i++) {
2075 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) ==
2076 hang_check.dcu_chain_state)
2077 {
2078 found_hangs |= dcu_chain_state;
2079 *dcu_chain = i;
2080 }
2081 }
2082 for (i = 0; i < 4; i++) {
2083 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) ==
2084 hang_check.dcu_chain_state)
2085 {
2086 found_hangs |= dcu_chain_state;
2087 *dcu_chain = i + 6;
2088 }
2089 }
2090 }
2091
2092 if (hangs & dcu_complete_state) {
2093 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) {
2094 found_hangs |= dcu_complete_state;
2095 }
2096 }
2097
2098 return found_hangs;
2099
2100} /* end - ar9300_compare_dbg_hang */
2101
2102#define NUM_STATUS_READS 50
2103HAL_BOOL
2104ar9300_detect_mac_hang(struct ath_hal *ah)
2105{
2106 struct ath_hal_9300 *ahp = AH9300(ah);
2107 mac_dbg_regs_t mac_dbg;
2108 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0};
2109 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state);
2110 int i = 0;
2111 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val;
2112
2113 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) {
2114 return AH_FALSE;
2115 }
2116
2117 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg));
2118
2119 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2120 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2121 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2122
2123 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n",
2124 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
2125 mac_dbg.dma_dbg_6);
2126
2127 if (hang_sig1 !=
2128 ar9300_compare_dbg_hang(ah, mac_dbg,
2129 hang_sig1_val, hang_sig1, &dcu_chain))
2130 {
2131 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n");
2132 return AH_FALSE;
2133 }
2134
2135 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain);
2136 shift_val *= 5;
2137
2138 for (i = 1; i <= NUM_STATUS_READS; i++) {
2139 if (dcu_chain < 6) {
2140 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2141 current_dcu_chain_state =
2142 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f);
2143 } else {
2144 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2145 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f);
2146 }
2147 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2148
2149 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state)
2150 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) {
2151 return AH_FALSE;
2152 }
2153 }
2154 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__,
2155 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]);
2156 ahp->ah_hang[MAC_HANG_SIG1]++;
2157 return AH_TRUE;
2158
2159} /* end - ar9300_detect_mac_hang */
2160
2161/* Determine if the baseband is hung by reading the Observation Bus Register */
2162HAL_BOOL
2163ar9300_detect_bb_hang(struct ath_hal *ah)
2164{
2165#define N(a) (sizeof(a) / sizeof(a[0]))
2166 struct ath_hal_9300 *ahp = AH9300(ah);
2167 u_int32_t hang_sig = 0;
2168 int i = 0;
2169 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times
2170 *
2171 * 4 known BB hang signatures -
2172 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
2173 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52
2174 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18
2175 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
2176 * Rx State (bits 20-24) is 0x7.
2177 */
2178 hal_hw_hang_check_t hang_list [] =
2179 {
2180 /* Offset Reg Value Reg Mask Hang Offset */
2181 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1},
2182 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2},
2183 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3},
2184 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4}
2185 };
2186
2187 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR |
2188 HAL_DFS_BB_HANG_WAR |
2189 HAL_RX_STUCK_LOW_BB_HANG_WAR))) {
2190 return AH_FALSE;
2191 }
2192
2193 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1);
2194 for (i = 1; i <= NUM_STATUS_READS; i++) {
2195 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) {
2196 return AH_FALSE;
2197 }
2198 }
2199
2200 for (i = 0; i < N(hang_list); i++) {
2201 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) {
2202 ahp->ah_hang[hang_list[i].hang_offset]++;
2203 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d "
2204 "sig3count=%d sig4count=%d\n", __func__,
2205 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2],
2206 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]);
2207 return AH_TRUE;
2208 }
2209 }
2210
2211 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! "
2212 "<0x806c>=0x%x\n", __func__, hang_sig);
2213
2214 return AH_FALSE;
2215
2216#undef N
2217} /* end - ar9300_detect_bb_hang () */
2218
2219#undef NUM_STATUS_READS
2220
2221HAL_STATUS
2222ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2223{
2224 struct ath_hal_9300 *ahp = AH9300(ah);
2225 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2226 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2227 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2228 u_int16_t ant_config;
2229 u_int32_t hal_num_ant_config;
2230
2231 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2232 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2233
2234 if (cfg < hal_num_ant_config) {
2235 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2236 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2237 return HAL_OK;
2238 }
2239 }
2240
2241 return HAL_EINVAL;
2242}
2243
2244/*
2245 * Functions to get/set DCS mode
2246 */
2247void
2248ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2249{
2250 AH9300(ah)->ah_dcs_enable = mode;
2251}
2252
2253u_int32_t
2254ar9300_get_dcs_mode(struct ath_hal *ah)
2255{
2256 return AH9300(ah)->ah_dcs_enable;
2257}
2258
2259#if ATH_BT_COEX
2260void
2261ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2262{
2263 struct ath_hal_9300 *ahp = AH9300(ah);
2264
2265 ahp->ah_bt_module = btinfo->bt_module;
2266 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2267 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;
2268 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority;
2269 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active;
2270 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity;
2271 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant;
2272 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation;
2273}
2274
2275void
2276ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf)
2277{
2278 struct ath_hal_9300 *ahp = AH9300(ah);
2279 HAL_BOOL rx_clear_polarity;
2280
2281 /*
2282 * For Kiwi and Osprey, the polarity of rx_clear is active high.
2283 * The bt_rxclear_polarity flag from ath_dev needs to be inverted.
2284 */
2285 rx_clear_polarity = !btconf->bt_rxclear_polarity;
2286
2287 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) |
2288 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) |
2289 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
2290 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
2291 SM(btconf->bt_mode, AR_BT_MODE) |
2292 SM(btconf->bt_quiet_collision, AR_BT_QUIET) |
2293 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) |
2294 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) |
2295 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME);
2296
2297 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR);
2298
2299 if (ahp->ah_bt_coex_single_ant == AH_FALSE) {
2300 /* Enable ACK to go out even though BT has higher priority. */
2301 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT;
2302 }
2303}
2304
2305void
2306ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum)
2307{
2308 struct ath_hal_9300 *ahp = AH9300(ah);
2309
2310 /* clear the old value, then set the new value */
2311 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH;
2312 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH);
2313}
2314
2315void
2316ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
2317{
2318 struct ath_hal_9300 *ahp = AH9300(ah);
2319
2320 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT;
2321 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT;
2322 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT;
2323 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT;
2324
2325 switch (stomp_type) {
2326 case HAL_BT_COEX_STOMP_ALL:
2327 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
2328 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
2329 break;
2330 case HAL_BT_COEX_STOMP_LOW:
2331 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
2332 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
2333 break;
2334 case HAL_BT_COEX_STOMP_ALL_FORCE:
2335 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0;
2336 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1;
2337 break;
2338 case HAL_BT_COEX_STOMP_LOW_FORCE:
2339 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0;
2340 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1;
2341 break;
2342 case HAL_BT_COEX_STOMP_NONE:
2343 case HAL_BT_COEX_NO_STOMP:
2344 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
2345 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
2346 break;
2347 default:
2348 /* There is a force_weight from registry */
2349 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
2350 ahp->ah_bt_coex_wlan_weight[1] = stomp_type;
2351 break;
2352 }
2353}
2354
2355void
2356ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh)
2357{
2358 struct ath_hal_9300 *ahp = AH9300(ah);
2359
2360 /* clear the old value, then set the new value */
2361 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH;
2362 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2363}
2364
2365static void
2366ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2367{
2368 struct ath_hal_9300 *ahp = AH9300(ah);
2369#if ATH_ANT_DIV_COMB
2370 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2371 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2372#endif
2373
2374 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2375 {
2376 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2377 {
2378 /* Config antenna diversity */
2379#if ATH_ANT_DIV_COMB
2380 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan);
2381#endif
2382 }
2383 }
2384}
2385
2386
2387void
2388ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
2389 u_int32_t value)
2390{
2391 struct ath_hal_9300 *ahp = AH9300(ah);
2392 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2393
2394 switch (type) {
2395 case HAL_BT_COEX_SET_ACK_PWR:
2396 if (value) {
2397 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2398 } else {
2399 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2400 }
2401 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2402 ahpriv->ah_extraTxPow, 0);
2403 break;
2404
2405 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2406 if (AR_SREV_POSEIDON(ah)) {
2407 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2408 if (value) {
2409 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2410 }
2411 else {
2412 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2413 }
2414 ar9300_bt_coex_antenna_diversity(ah, value);
2415 }
2416 break;
2417 case HAL_BT_COEX_LOWER_TX_PWR:
2418 if (value) {
2419 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2420 }
2421 else {
2422 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2423 }
2424 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2425 ahpriv->ah_extraTxPow, 0);
2426 break;
2427#if ATH_SUPPORT_MCI
2428 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2429 if ((ah->ah_config.ath_hal_mci_config &
2430 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2431 {
2432 if (value) {
2433 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2434 ahp->ah_mci_concur_tx_en = AH_TRUE;
2435 }
2436 else {
2437 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2438 ahp->ah_mci_concur_tx_en = AH_FALSE;
2439 }
2440 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2441 ahpriv->ah_extraTxPow, 0);
2442 }
2443 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2444 ahp->ah_mci_concur_tx_en);
2445 break;
2446 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2447 if (value) {
2448 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2449 }
2450 else {
2451 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2452 }
2453 break;
2454#endif
2455 default:
2456 break;
2457 }
2458}
2459
2460void
2461ar9300_bt_coex_disable(struct ath_hal *ah)
2462{
2463 struct ath_hal_9300 *ahp = AH9300(ah);
2464
2465 /* Always drive rx_clear_external output as 0 */
2466 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2467 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2468
2469 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2470 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2471 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2472 }
2473
2474 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
2475 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
2476 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
2477 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
2478 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
2479 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
2480 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
2481 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
2482
2483 ahp->ah_bt_coex_enabled = AH_FALSE;
2484}
2485
2486int
2487ar9300_bt_coex_enable(struct ath_hal *ah)
2488{
2489 struct ath_hal_9300 *ahp = AH9300(ah);
2490
2491 /* Program coex mode and weight registers to actually enable coex */
2492 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode);
2493 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2);
2494 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]);
2495 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]);
2496 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]);
2497 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]);
2498 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]);
2499 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]);
2500
2501 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) {
2502 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);
2503 } else {
2504 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);
2505 }
2506
2507 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2508 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2509 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2510 } else {
2511 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2512 }
2513
2514 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2515 /* For 3-wire, configure the desired GPIO port for rx_clear */
2516 ath_hal_gpioCfgOutput(ah,
2517 ahp->ah_wlan_active_gpio_select,
2518 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2519 }
2520 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2521 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2522 {
2523 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2524 ath_hal_gpioCfgOutput(ah,
2525 ahp->ah_wlan_active_gpio_select,
2526 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2527 }
2528
2529 /*
2530 * Enable a weak pull down on BT_ACTIVE.
2531 * When BT device is disabled, BT_ACTIVE might be floating.
2532 */
2533 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU),
2534 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)),
2535 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2)));
2536
2537 ahp->ah_bt_coex_enabled = AH_TRUE;
2538
2539 return 0;
2540}
2541
2542u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg)
2543{
2544 return 0;
2545}
2546
2547u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn)
2548{
2549 return bOn;
2550}
2551
2552void
2553ar9300_init_bt_coex(struct ath_hal *ah)
2554{
2555 struct ath_hal_9300 *ahp = AH9300(ah);
2556
2557 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2558 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2559 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
2560 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
2561
2562 /*
2563 * Set input mux for bt_prority_async and
2564 * bt_active_async to GPIO pins
2565 */
2566 OS_REG_RMW_FIELD(ah,
2567 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2568 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2569 ahp->ah_bt_active_gpio_select);
2570 OS_REG_RMW_FIELD(ah,
2571 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2572 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2573 ahp->ah_bt_priority_gpio_select);
2574
2575 /* Configure the desired GPIO ports for input */
2576 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2577 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2578
2579 if (ahp->ah_bt_coex_enabled) {
2580 ar9300_bt_coex_enable(ah);
2581 } else {
2582 ar9300_bt_coex_disable(ah);
2583 }
2584 }
2585 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2586 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2587 {
2588 /* 2-wire */
2589 if (ahp->ah_bt_coex_enabled) {
2590 /* Connect bt_active_async to baseband */
2591 OS_REG_CLR_BIT(ah,
2592 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2593 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
2594 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
2595 OS_REG_SET_BIT(ah,
2596 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2597 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
2598
2599 /*
2600 * Set input mux for bt_prority_async and
2601 * bt_active_async to GPIO pins
2602 */
2603 OS_REG_RMW_FIELD(ah,
2604 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2605 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2606 ahp->ah_bt_active_gpio_select);
2607
2608 /* Configure the desired GPIO ports for input */
2609 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2610
2611 /* Enable coexistence on initialization */
2612 ar9300_bt_coex_enable(ah);
2613 }
2614 }
2615#if ATH_SUPPORT_MCI
2616 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2617 if (ahp->ah_bt_coex_enabled) {
2618 ar9300_mci_bt_coex_enable(ah);
2619 }
2620 else {
2621 ar9300_mci_bt_coex_disable(ah);
2622 }
2623 }
2624#endif /* ATH_SUPPORT_MCI */
2625}
2626
2627#endif /* ATH_BT_COEX */
2628
2629HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable)
2630{
2631 u_int32_t val;
2632 int wasp_mm_rev;
2633
2634#define AR_SOC_RST_REVISION_ID 0xB8060090
2635#define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
2636 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) &
2637 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >>
2638 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT;
2639#undef AR_SOC_RST_REVISION_ID
2640#undef REG_READ
2641
2642 /*
2643 * Azimuth (ProxySTA) Mode is only supported correctly by
2644 * Peacock or WASP 1.3.0.1 or later (hopefully) chips.
2645 *
2646 * Enable this feature for Scorpion at this time. The silicon
2647 * still needs to be validated.
2648 */
2649 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) &&
2650 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) &&
2651 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) &&
2652 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) ||
2653 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 &&
2654 wasp_mm_rev >= 0 /* 1 */))))
2655 {
2656 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, "
2657 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n",
2658 __func__, AH_PRIVATE((ah))->ah_macVersion,
2659 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev);
2660 return HAL_ENOTSUPP;
2661 }
2662
2663 OS_REG_WRITE(ah,
2664 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996);
2665
2666 /* turn on mode bit[24] for proxy sta */
2667 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2,
2668 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA);
2669
2670 val = OS_REG_READ(ah, AR_AZIMUTH_MODE);
2671 if (enable) {
2672 val |= AR_AZIMUTH_KEY_SEARCH_AD1 |
2673 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2674 AR_AZIMUTH_BA_USES_AD1;
2675 /* turn off filter pass hold (bit 9) */
2676 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD;
2677 } else {
2678 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 |
2679 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2680 AR_AZIMUTH_BA_USES_AD1);
2681 }
2682 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val);
2683
2684 /* enable promiscous mode */
2685 OS_REG_WRITE(ah, AR_RX_FILTER,
2686 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM);
2687 /* enable promiscous in azimuth mode */
2688 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE);
2689 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE);
2690
2691 /* turn on filter pass hold (bit 9) */
2692 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2693 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2694
2695 return HAL_OK;
2696}
2697
2698#if 0
2699void ar9300_mat_enable(struct ath_hal *ah, int enable)
2700{
2701 /*
2702 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2703 * mitigation and turn on key search always for better performance.
2704 */
2705 struct ath_hal_9300 *ahp = AH9300(ah);
2706 struct ath_hal_private *ap = AH_PRIVATE(ah);
2707
2708 ahp->ah_intr_mitigation_rx = !enable;
2709 if (ahp->ah_intr_mitigation_rx) {
2710 /*
2711 * Enable Interrupt Mitigation for Rx.
2712 * If no build-specific limits for the rx interrupt mitigation
2713 * timer have been specified, use conservative defaults.
2714 */
2715 #ifndef AH_RIMT_VAL_LAST
2716 #define AH_RIMT_LAST_MICROSEC 500
2717 #endif
2718 #ifndef AH_RIMT_VAL_FIRST
2719 #define AH_RIMT_FIRST_MICROSEC 2000
2720 #endif
2721 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2722 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2723 } else {
2724 OS_REG_WRITE(ah, AR_RIMT, 0);
2725 }
2726
2727 ahp->ah_enable_keysearch_always = !!enable;
2728 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2729}
2730#endif
2731
2732void ar9300_enable_tpc(struct ath_hal *ah)
2733{
2734 u_int32_t val = 0;
2735
2736 ah->ah_config.ath_hal_desc_tpc = 1;
2737
2738 /* Enable TPC */
2739 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2740
2741 /*
2742 * Disable per chain power reduction since we are already
2743 * accounting for this in our calculations
2744 */
2745 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB);
2746 if (AR_SREV_WASP(ah)) {
2747 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2748 val & AR_PHY_POWER_TX_SUB_2_DISABLE);
2749 } else {
2750 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2751 val & AR_PHY_POWER_TX_SUB_3_DISABLE);
2752 }
2753}
2754
2755
2756/*
2757 * ar9300_force_tsf_sync
2758 * This function forces the TSF sync to the given bssid, this is implemented
2759 * as a temp hack to get the AoW demo, and is primarily used in the WDS client
2760 * mode of operation, where we sync the TSF to RootAP TSF values
2761 */
2762void
2763ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid,
2764 u_int16_t assoc_id)
2765{
2766 ar9300_set_operating_mode(ah, HAL_M_STA);
2767 ar9300_write_associd(ah, bssid, assoc_id);
2768}
2769
2770void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
2771{
2772 struct ath_hal_9300 *ahp = AH9300(ah);
2773 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val;
2774 u_int32_t temp_powertx_rate9_reg_val;
2775 int8_t olpc_power_offset = 0;
2776 int8_t tmp_olpc_val = 0;
2777 HAL_RSSI_TX_POWER old_greentx_status;
2778 u_int8_t target_power_val_t[ar9300_rate_size];
2779 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2780
2781 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2782 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2783 return;
2784 }
2785
2786 old_greentx_status = AH9300(ah)->green_tx_status;
2787 if (ahp->ah_hw_green_tx_enable) {
2788 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2789 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2790 } else {
2791 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2792 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2793 }
2794
2795 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2796 && (rssi > tmp_rss1_thr1))
2797 {
2798 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2799 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2800 }
2801 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2802 && (rssi > tmp_rss1_thr2))
2803 {
2804 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2805 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2806 }
2807 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2808 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2809 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2810 }
2811 }
2812
2813 /* If status is not change, don't do anything */
2814 if (old_greentx_status == AH9300(ah)->green_tx_status) {
2815 return;
2816 }
2817
2818 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2819 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2820 && AR_SREV_POSEIDON(ah))
2821 {
2822 if (ahp->ah_hw_green_tx_enable) {
2823 switch (AH9300(ah)->green_tx_status) {
2824 case HAL_RSSI_TX_POWER_SHORT:
2825 /* 1. TxPower Config */
2826 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2827 sizeof(target_power_val_t));
2828 /* 1.1 Store OLPC Delta Calibration Offset*/
2829 olpc_power_offset = 0;
2830 /* 2. Store OB/DB */
2831 /* 3. Store TPC settting */
2832 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
2833 SM(14, AR_TPC_CTS) |
2834 SM(14, AR_TPC_CHIRP) |
2835 SM(14, AR_TPC_RPT));
2836 /* 4. Store BB_powertx_rate9 value */
2837 temp_powertx_rate9_reg_val =
2838 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE;
2839 break;
2840 case HAL_RSSI_TX_POWER_MIDDLE:
2841 /* 1. TxPower Config */
2842 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle,
2843 sizeof(target_power_val_t));
2844 /* 1.1 Store OLPC Delta Calibration Offset*/
2845 olpc_power_offset = 0;
2846 /* 2. Store OB/DB */
2847 /* 3. Store TPC settting */
2848 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) |
2849 SM(18, AR_TPC_CTS) |
2850 SM(18, AR_TPC_CHIRP) |
2851 SM(18, AR_TPC_RPT));
2852 /* 4. Store BB_powertx_rate9 value */
2853 temp_powertx_rate9_reg_val =
2854 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE;
2855 break;
2856 case HAL_RSSI_TX_POWER_LONG:
2857 default:
2858 /* 1. TxPower Config */
2859 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2860 sizeof(target_power_val_t));
2861 /* 1.1 Store OLPC Delta Calibration Offset*/
2862 olpc_power_offset = 0;
2863 /* 2. Store OB/DB1/DB2 */
2864 /* 3. Store TPC settting */
2865 temp_tcp_reg_val =
2866 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2867 /* 4. Store BB_powertx_rate9 value */
2868 temp_powertx_rate9_reg_val =
2869 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2870 break;
2871 }
2872 } else {
2873 switch (AH9300(ah)->green_tx_status) {
2874 case HAL_RSSI_TX_POWER_SHORT:
2875 /* 1. TxPower Config */
2876 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2877 sizeof(target_power_val_t));
2878 /* 1.1 Store OLPC Delta Calibration Offset*/
2879 olpc_power_offset =
2880 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2881 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2882 /* 2. Store OB/DB */
2883 temp_obdb_reg_val =
2884 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2885 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2886 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2887 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2888 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2889 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2890 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2891 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2892 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2893 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
2894 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2895 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
2896 /* 3. Store TPC settting */
2897 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) |
2898 SM(6, AR_TPC_CTS) |
2899 SM(6, AR_TPC_CHIRP) |
2900 SM(6, AR_TPC_RPT));
2901 /* 4. Store BB_powertx_rate9 value */
2902 temp_powertx_rate9_reg_val =
2903 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE;
2904 break;
2905 case HAL_RSSI_TX_POWER_MIDDLE:
2906 /* 1. TxPower Config */
2907 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
2908 sizeof(target_power_val_t));
2909 /* 1.1 Store OLPC Delta Calibration Offset*/
2910 olpc_power_offset =
2911 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
2912 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2913 /* 2. Store OB/DB */
2914 temp_obdb_reg_val =
2915 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2916 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2917 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2918 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2919 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2920 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2921 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2922 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2923 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2924 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
2925 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2926 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
2927 /* 3. Store TPC settting */
2928 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
2929 SM(14, AR_TPC_CTS) |
2930 SM(14, AR_TPC_CHIRP) |
2931 SM(14, AR_TPC_RPT));
2932 /* 4. Store BB_powertx_rate9 value */
2933 temp_powertx_rate9_reg_val =
2934 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE;
2935 break;
2936 case HAL_RSSI_TX_POWER_LONG:
2937 default:
2938 /* 1. TxPower Config */
2939 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2940 sizeof(target_power_val_t));
2941 /* 1.1 Store OLPC Delta Calibration Offset*/
2942 olpc_power_offset =
2943 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
2944 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2945 /* 2. Store OB/DB1/DB2 */
2946 temp_obdb_reg_val =
2947 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2948 /* 3. Store TPC settting */
2949 temp_tcp_reg_val =
2950 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2951 /* 4. Store BB_powertx_rate9 value */
2952 temp_powertx_rate9_reg_val =
2953 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2954 break;
2955 }
2956 }
2957 /* 1.1 Do OLPC Delta Calibration Offset */
2958 tmp_olpc_val =
2959 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
2960 tmp_olpc_val += olpc_power_offset;
2961 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
2962 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
2963 AR_PHY_TPC_OLPC_GAIN_DELTA);
2964
2965 /* 1.2 TxPower Config */
2966 ar9300_transmit_power_reg_write(ah, target_power_val_t);
2967 /* 2. Config OB/DB */
2968 if (!ahp->ah_hw_green_tx_enable) {
2969 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
2970 }
2971 /* 3. config TPC settting */
2972 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
2973 /* 4. config BB_powertx_rate9 value */
2974 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
2975 }
2976}
2977
2978#if 0
2979void
2980ar9300_get_vow_stats(
2981 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
2982{
2983 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
2984 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2985 }
2986 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {
2987 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
2988 }
2989 if (vow_reg_flags & AR_REG_RX_CLR_CNT) {
2990 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
2991 }
2992 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
2993 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2994 }
2995 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
2996 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
2997 }
2998}
2999#endif
3000
3001/*
3002 * ar9300_is_skip_paprd_by_greentx
3003 *
3004 * This function check if we need to skip PAPRD tuning
3005 * when GreenTx in specific state.
3006 */
3007HAL_BOOL
3008ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3009{
3010 if (AR_SREV_POSEIDON(ah) &&
3011 ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3012 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3013 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3014 {
3015 return AH_TRUE;
3016 }
3017 return AH_FALSE;
3018}
3019
3020void
3021ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)
3022{
3023 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3]
3024 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3]
3025 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3]
3026 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3]
3027 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3]
3028 struct ath_hal_9300 *ahp = AH9300(ah);
3029
3030 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3031 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3032 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0);
3033 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3034 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0);
3035 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3036 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0);
3037 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3038 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0);
3039 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3040 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0);
3041 }
3042}
3043
3044void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value)
3045{
3046 struct ath_hal_9300 *ahp = AH9300(ah);
3047
3048 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3049 if ((value == 0) || (value == 1)) {
3050 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
3051 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value);
3052 }
3053 }
3054}
3055
3056void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah)
3057{
3058 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC);
3059}
3060
3061int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah)
3062{
3063 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL);
3064
3065 /* RSSI format is 8.4. Ignore lowest four bits */
3066 val = val >> 4;
3067 return val;
3068}
3069
3070void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah,
3071 u_int32_t rssi_threshold)
3072{
3073 struct ath_hal_9300 *ahp = AH9300(ah);
3074
3075 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold);
3076
3077 /* save value for restoring after chip reset */
3078 ahp->ah_beacon_rssi_threshold = rssi_threshold;
3079}
3080
3081void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah)
3082{
3083 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST);
3084}
3085
3086void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on)
3087{
3088 if (on) {
3089 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3090 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3091 }
3092 else {
3093 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3094 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3095 }
3096}
3097/*
3098 * Gets the contents of the specified key cache entry.
3099 */
3100HAL_BOOL
3101ar9300_print_keycache(struct ath_hal *ah)
3102{
3103
3104 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3105 u_int32_t key0, key1, key2, key3, key4;
3106 u_int32_t mac_hi, mac_lo;
3107 u_int16_t entry = 0;
3108 u_int32_t valid = 0;
3109 u_int32_t key_type;
3110
3111 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3112
3113 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3114 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3115 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3116 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3117 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3118 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3119
3120 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3121
3122 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry));
3123 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
3124
3125 if (mac_hi & AR_KEYTABLE_VALID) {
3126 valid = 1;
3127 } else {
3128 valid = 0;
3129 }
3130
3131 if ((mac_hi != 0) && (mac_lo != 0)) {
3132 mac_hi &= ~0x8000;
3133 mac_hi <<= 1;
3134 mac_hi |= ((mac_lo & (1 << 31) )) >> 31;
3135 mac_lo <<= 1;
3136 }
3137
3138 ath_hal_printf(ah,
3139 "%03d "
3140 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
3141 " %02d %02d "
3142 "%02x:%02x:%02x:%02x:%02x:%02x \n",
3143 entry,
3144 (key0 << 24) >> 24, (key0 << 16) >> 24,
3145 (key0 << 8) >> 24, key0 >> 24,
3146 (key1 << 24) >> 24, (key1 << 16) >> 24,
3147 //(key1 << 8) >> 24, key1 >> 24,
3148 (key2 << 24) >> 24, (key2 << 16) >> 24,
3149 (key2 << 8) >> 24, key2 >> 24,
3150 (key3 << 24) >> 24, (key3 << 16) >> 24,
3151 //(key3 << 8) >> 24, key3 >> 24,
3152 (key4 << 24) >> 24, (key4 << 16) >> 24,
3153 (key4 << 8) >> 24, key4 >> 24,
3154 valid, key_type,
3155 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3156 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3157 }
3158
3159 return AH_TRUE;
3160}
3161
3162/* enable/disable smart antenna mode */
3163HAL_BOOL
3164ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3165{
3166 struct ath_hal_9300 *ahp = AH9300(ah);
3167
3168 if (enable) {
3169 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3170 } else {
3171 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3172 }
3173
3174 /* if scropion and smart antenna is enabled, write swcom1 with 0x440
3175 * and swcom2 with 0
3176 * FIXME Ideally these registers need to be made read from caldata.
3177 * Until the calibration team gets them, keep them along with board
3178 * configuration.
3179 */
3180 if (enable && AR_SREV_SCORPION(ah) &&
3181 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) {
3182
3183 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440);
3184 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0);
3185 }
3186
3187 ahp->ah_smartantenna_enable = enable;
3188 return 1;
3189}
3190
3191#ifdef ATH_TX99_DIAG
3192#ifndef ATH_SUPPORT_HTC
3193void
3194ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3195 u_int32_t txpower)
3196{
3197#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3198 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3199 int32_t i;
3200
3201 /* The max power is limited to 63 */
3202 if (txpower <= AR9300_MAX_RATE_POWER) {
3203 for (i = 0; i < ar9300_rate_size; i++) {
3204 p_pwr_array[i] = txpower;
3205 }
3206 } else {
3207 for (i = 0; i < ar9300_rate_size; i++) {
3208 p_pwr_array[i] = AR9300_MAX_RATE_POWER;
3209 }
3210 }
3211
3212 OS_REG_WRITE(ah, 0xa458, 0);
3213
3214 /* Write the OFDM power per rate set */
3215 /* 6 (LSB), 9, 12, 18 (MSB) */
3216 OS_REG_WRITE(ah, 0xa3c0,
3217 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24)
3218 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16)
3219 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8)
3220 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3221 );
3222 /* 24 (LSB), 36, 48, 54 (MSB) */
3223 OS_REG_WRITE(ah, 0xa3c4,
3224 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24)
3225 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16)
3226 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8)
3227 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3228 );
3229
3230 /* Write the CCK power per rate set */
3231 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3232 OS_REG_WRITE(ah, 0xa3c8,
3233 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24)
3234 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16)
3235 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */
3236 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3237 );
3238 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3239 OS_REG_WRITE(ah, 0xa3cc,
3240 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24)
3241 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16)
3242 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8)
3243 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3244 );
3245
3246 /* Write the HT20 power per rate set */
3247 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3248 OS_REG_WRITE(ah, 0xa3d0,
3249 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24)
3250 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16)
3251 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)
3252 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0)
3253 );
3254
3255 /* 6 (LSB), 7, 12, 13 (MSB) */
3256 OS_REG_WRITE(ah, 0xa3d4,
3257 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24)
3258 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16)
3259 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8)
3260 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0)
3261 );
3262
3263 /* 14 (LSB), 15, 20, 21 */
3264 OS_REG_WRITE(ah, 0xa3e4,
3265 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24)
3266 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16)
3267 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8)
3268 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0)
3269 );
3270
3271 /* Mixed HT20 and HT40 rates */
3272 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3273 OS_REG_WRITE(ah, 0xa3e8,
3274 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24)
3275 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16)
3276 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8)
3277 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0)
3278 );
3279
3280 /* Write the HT40 power per rate set */
3281 /* correct PAR difference between HT40 and HT20/LEGACY */
3282 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3283 OS_REG_WRITE(ah, 0xa3d8,
3284 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24)
3285 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16)
3286 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8)
3287 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0)
3288 );
3289
3290 /* 6 (LSB), 7, 12, 13 (MSB) */
3291 OS_REG_WRITE(ah, 0xa3dc,
3292 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24)
3293 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16)
3294 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8)
3295 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0)
3296 );
3297
3298 /* 14 (LSB), 15, 20, 21 */
3299 OS_REG_WRITE(ah, 0xa3ec,
3300 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24)
3301 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16)
3302 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8)
3303 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0)
3304 );
3305#undef PWR_MAS
3306}
3307
3308void
3309ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask)
3310{
3311 if (tx_chainmask == 0x5) {
3312 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3313 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3314 }
3315 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask);
3316 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask);
3317
3318 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
3319 if (tx_chainmask == 0x5) {
3320 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3321 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3322 }
3323}
3324
3325void
3326ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask,
3327 int chtype)
3328{
3329 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff);
3330 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1));
3331 OS_REG_WRITE(ah, 0xa350,
3332 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13));
3333
3334 /* 11G mode */
3335 if (!chtype) {
3336 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3337 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2));
3338 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3339 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3340 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3341 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3342 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3343 | (0x1 << 26) | (0x7 << 24))
3344 & ~(0x1 << 22));
3345 } else {
3346 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3347 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3348 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3349 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3350 | (0x1 << 26) | (0x7 << 24))
3351 & ~(0x1 << 22));
3352 }
3353
3354 /* chain zero */
3355 if ((tx_chain_mask & 0x01) == 0x01) {
3356 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3357 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3358 | (0x1 << 31) | (0x5 << 15)
3359 | (0x3 << 9)) & ~(0x1 << 27)
3360 & ~(0x1 << 12));
3361 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3362 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3363 | (0x1 << 12) | (0x1 << 10)
3364 | (0x1 << 9) | (0x1 << 8)
3365 | (0x1 << 7)) & ~(0x1 << 11));
3366 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3367 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3368 | (0x1 << 29) | (0x1 << 25)
3369 | (0x1 << 23) | (0x1 << 19)
3370 | (0x1 << 10) | (0x1 << 9)
3371 | (0x1 << 8) | (0x1 << 3))
3372 & ~(0x1 << 28)& ~(0x1 << 24)
3373 & ~(0x1 << 22)& ~(0x1 << 7));
3374 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3375 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3376 | (0x1 << 23))& ~(0x1 << 21));
3377 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3378 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3379 | (0x1 << 12) | (0x1 << 10)
3380 | (0x1 << 9) | (0x1 << 8)
3381 | (0x1 << 6) | (0x1 << 5)
3382 | (0x1 << 4) | (0x1 << 3)
3383 | (0x1 << 2));
3384 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3385 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3386 }
3387 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3388 /* chain one */
3389 if ((tx_chain_mask & 0x02) == 0x02 ) {
3390 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3391 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3392 | (0x1 << 31) | (0x5 << 15)
3393 | (0x3 << 9)) & ~(0x1 << 27)
3394 & ~(0x1 << 12));
3395 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3396 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3397 | (0x1 << 12) | (0x1 << 10)
3398 | (0x1 << 9) | (0x1 << 8)
3399 | (0x1 << 7)) & ~(0x1 << 11));
3400 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3401 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3402 | (0x1 << 29) | (0x1 << 25)
3403 | (0x1 << 23) | (0x1 << 19)
3404 | (0x1 << 10) | (0x1 << 9)
3405 | (0x1 << 8) | (0x1 << 3))
3406 & ~(0x1 << 28)& ~(0x1 << 24)
3407 & ~(0x1 << 22)& ~(0x1 << 7));
3408 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3409 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3410 | (0x1 << 23))& ~(0x1 << 21));
3411 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3412 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3413 | (0x1 << 12) | (0x1 << 10)
3414 | (0x1 << 9) | (0x1 << 8)
3415 | (0x1 << 6) | (0x1 << 5)
3416 | (0x1 << 4) | (0x1 << 3)
3417 | (0x1 << 2));
3418 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3419 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3420 }
3421 }
3422 if (AR_SREV_OSPREY(ah)) {
3423 /* chain two */
3424 if ((tx_chain_mask & 0x04) == 0x04 ) {
3425 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3426 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3427 | (0x1 << 31) | (0x5 << 15)
3428 | (0x3 << 9)) & ~(0x1 << 27)
3429 & ~(0x1 << 12));
3430 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3431 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3432 | (0x1 << 12) | (0x1 << 10)
3433 | (0x1 << 9) | (0x1 << 8)
3434 | (0x1 << 7)) & ~(0x1 << 11));
3435 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3436 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3437 | (0x1 << 29) | (0x1 << 25)
3438 | (0x1 << 23) | (0x1 << 19)
3439 | (0x1 << 10) | (0x1 << 9)
3440 | (0x1 << 8) | (0x1 << 3))
3441 & ~(0x1 << 28)& ~(0x1 << 24)
3442 & ~(0x1 << 22)& ~(0x1 << 7));
3443 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3444 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3445 | (0x1 << 23))& ~(0x1 << 21));
3446 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3447 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3448 | (0x1 << 12) | (0x1 << 10)
3449 | (0x1 << 9) | (0x1 << 8)
3450 | (0x1 << 6) | (0x1 << 5)
3451 | (0x1 << 4) | (0x1 << 3)
3452 | (0x1 << 2));
3453 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3454 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3455 }
3456 }
3457
3458 OS_REG_WRITE(ah, 0xa28c, 0x11111);
3459 OS_REG_WRITE(ah, 0xa288, 0x111);
3460 } else {
3461 /* chain zero */
3462 if ((tx_chain_mask & 0x01) == 0x01) {
3463 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3464 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3465 | (0x1 << 31) | (0x1 << 27)
3466 | (0x3 << 23) | (0x1 << 19)
3467 | (0x1 << 15) | (0x3 << 9))
3468 & ~(0x1 << 12));
3469 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3470 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3471 | (0x1 << 12) | (0x1 << 10)
3472 | (0x1 << 9) | (0x1 << 8)
3473 | (0x1 << 7) | (0x1 << 3)
3474 | (0x1 << 2) | (0x1 << 1))
3475 & ~(0x1 << 11)& ~(0x1 << 0));
3476 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3477 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3478 | (0x1 << 29) | (0x1 << 25)
3479 | (0x1 << 23) | (0x1 << 19)
3480 | (0x1 << 10) | (0x1 << 9)
3481 | (0x1 << 8) | (0x1 << 3))
3482 & ~(0x1 << 28)& ~(0x1 << 24)
3483 & ~(0x1 << 22)& ~(0x1 << 7));
3484 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3485 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3486 | (0x1 << 23))& ~(0x1 << 21));
3487 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2,
3488 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
3489 | (0x3 << 3) | (0x3 << 0));
3490 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3,
3491 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
3492 | (0x3 << 29) | (0x3 << 26)
3493 | (0x2 << 23) | (0x2 << 20)
3494 | (0x2 << 17))& ~(0x1 << 14));
3495 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3496 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3497 | (0x1 << 12) | (0x1 << 10)
3498 | (0x1 << 9) | (0x1 << 8)
3499 | (0x1 << 6) | (0x1 << 5)
3500 | (0x1 << 4) | (0x1 << 3)
3501 | (0x1 << 2));
3502 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3503 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3504 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3505 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3506 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3507 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3508 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3509 | (0x1 << 26) | (0x7 << 24)
3510 | (0x3 << 22));
3511 } else {
3512 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3513 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3514 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3515 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3516 | (0x1 << 26) | (0x7 << 24)
3517 | (0x3 << 22));
3518 }
3519
3520 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3521 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3522 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3523 | (0x1 << 3) | (0x1 << 2)
3524 | (0x1 << 1)) & ~(0x1 << 0));
3525 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3526 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3527 | (0x1 << 19) | (0x1 << 3));
3528 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3529 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3530 }
3531 if (AR_SREV_OSPREY(ah)) {
3532 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3533 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3534 | (0x1 << 3) | (0x1 << 2)
3535 | (0x1 << 1)) & ~(0x1 << 0));
3536 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3537 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3538 | (0x1 << 19) | (0x1 << 3));
3539 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3540 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3541 }
3542 }
3543 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3544 /* chain one */
3545 if ((tx_chain_mask & 0x02) == 0x02 ) {
3546 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3547 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3548 | (0x1 << 3) | (0x1 << 2)
3549 | (0x1 << 1)) & ~(0x1 << 0));
3550 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3551 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3552 | (0x1 << 19) | (0x1 << 3));
3553 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3554 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3555 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3556 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3557 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3558 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3559 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3560 | (0x1 << 26) | (0x7 << 24)
3561 | (0x3 << 22));
3562 } else {
3563 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3564 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3565 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3566 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3567 | (0x1 << 26) | (0x7 << 24)
3568 | (0x3 << 22));
3569 }
3570
3571 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3572 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3573 | (0x1 << 31) | (0x1 << 27)
3574 | (0x3 << 23) | (0x1 << 19)
3575 | (0x1 << 15) | (0x3 << 9))
3576 & ~(0x1 << 12));
3577 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3578 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3579 | (0x1 << 12) | (0x1 << 10)
3580 | (0x1 << 9) | (0x1 << 8)
3581 | (0x1 << 7) | (0x1 << 3)
3582 | (0x1 << 2) | (0x1 << 1))
3583 & ~(0x1 << 11)& ~(0x1 << 0));
3584 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3585 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3586 | (0x1 << 29) | (0x1 << 25)
3587 | (0x1 << 23) | (0x1 << 19)
3588 | (0x1 << 10) | (0x1 << 9)
3589 | (0x1 << 8) | (0x1 << 3))
3590 & ~(0x1 << 28)& ~(0x1 << 24)
3591 & ~(0x1 << 22)& ~(0x1 << 7));
3592 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3593 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3594 | (0x1 << 23))& ~(0x1 << 21));
3595 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2,
3596 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
3597 | (0x3 << 3) | (0x3 << 0));
3598 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3,
3599 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
3600 | (0x3 << 29) | (0x3 << 26)
3601 | (0x2 << 23) | (0x2 << 20)
3602 | (0x2 << 17))& ~(0x1 << 14));
3603 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3604 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3605 | (0x1 << 12) | (0x1 << 10)
3606 | (0x1 << 9) | (0x1 << 8)
3607 | (0x1 << 6) | (0x1 << 5)
3608 | (0x1 << 4) | (0x1 << 3)
3609 | (0x1 << 2));
3610 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3611 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3612
3613 if (AR_SREV_OSPREY(ah)) {
3614 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3615 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3616 | (0x1 << 3) | (0x1 << 2)
3617 | (0x1 << 1)) & ~(0x1 << 0));
3618 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3619 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3620 | (0x1 << 19) | (0x1 << 3));
3621 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3622 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3623 }
3624 }
3625 }
3626 if (AR_SREV_OSPREY(ah)) {
3627 /* chain two */
3628 if ((tx_chain_mask & 0x04) == 0x04 ) {
3629 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3630 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3631 | (0x1 << 3) | (0x1 << 2)
3632 | (0x1 << 1)) & ~(0x1 << 0));
3633 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3634 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3635 | (0x1 << 19) | (0x1 << 3));
3636 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3637 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3638 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3639 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3640 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3641 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3642 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3643 | (0x1 << 26) | (0x7 << 24)
3644 | (0x3 << 22));
3645 } else {
3646 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3647 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3648 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3649 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3650 | (0x1 << 26) | (0x7 << 24)
3651 | (0x3 << 22));
3652 }
3653
3654 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3655 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3656 | (0x1 << 3) | (0x1 << 2)
3657 | (0x1 << 1)) & ~(0x1 << 0));
3658 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3659 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3660 | (0x1 << 19) | (0x1 << 3));
3661 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3662 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3663
3664 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3665 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3666 | (0x1 << 31) | (0x1 << 27)
3667 | (0x3 << 23) | (0x1 << 19)
3668 | (0x1 << 15) | (0x3 << 9))
3669 & ~(0x1 << 12));
3670 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3671 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3672 | (0x1 << 12) | (0x1 << 10)
3673 | (0x1 << 9) | (0x1 << 8)
3674 | (0x1 << 7) | (0x1 << 3)
3675 | (0x1 << 2) | (0x1 << 1))
3676 & ~(0x1 << 11)& ~(0x1 << 0));
3677 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3678 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3679 | (0x1 << 29) | (0x1 << 25)
3680 | (0x1 << 23) | (0x1 << 19)
3681 | (0x1 << 10) | (0x1 << 9)
3682 | (0x1 << 8) | (0x1 << 3))
3683 & ~(0x1 << 28)& ~(0x1 << 24)
3684 & ~(0x1 << 22)& ~(0x1 << 7));
3685 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3686 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3687 | (0x1 << 23))& ~(0x1 << 21));
3688 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2,
3689 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
3690 | (0x3 << 3) | (0x3 << 0));
3691 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3,
3692 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
3693 | (0x3 << 29) | (0x3 << 26)
3694 | (0x2 << 23) | (0x2 << 20)
3695 | (0x2 << 17))& ~(0x1 << 14));
3696 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3697 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3698 | (0x1 << 12) | (0x1 << 10)
3699 | (0x1 << 9) | (0x1 << 8)
3700 | (0x1 << 6) | (0x1 << 5)
3701 | (0x1 << 4) | (0x1 << 3)
3702 | (0x1 << 2));
3703 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3704 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3705 }
3706 }
3707
3708 OS_REG_WRITE(ah, 0xa28c, 0x22222);
3709 OS_REG_WRITE(ah, 0xa288, 0x222);
3710 }
3711}
3712
3713void
3714ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data)
3715{
3716 u_int32_t val;
3717 u_int32_t qnum = (u_int32_t)data;
3718
3719 /* Disable AGC to A2 */
3720 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR));
| 1704 return -1;
1705 }
1706
1707 bb_panic->tsf = ar9300_get_tsf32(ah);
1708 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS);
1709 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG);
1710 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM);
1711 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM);
1712 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM);
1713 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM);
1714 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM);
1715 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM);
1716 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM);
1717 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1);
1718 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1719 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1720 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1721 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1722 &bb_panic->rxc_pcnt,
1723 &bb_panic->rxf_pcnt,
1724 &bb_panic->txf_pcnt);
1725
1726 if (ah->ah_config.ath_hal_show_bb_panic) {
1727 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1728 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1729 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1730 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1731 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1732 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1733 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1734 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1735 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2);
1736 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n",
1737 bb_panic->phy_gen_ctrl);
1738 if (bb_panic->cycles) {
1739 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, "
1740 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt,
1741 bb_panic->rxf_pcnt, bb_panic->txf_pcnt);
1742 }
1743 ath_hal_printf(ah, "==== BB update: done ====\n\n");
1744 }
1745
1746 return 0; //The returned data will be stored for athstats to retrieve it
1747}
1748
1749/* set the reason for HAL reset */
1750void
1751ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1752{
1753 AH9300(ah)->ah_reset_reason = resetreason;
1754}
1755
1756/*
1757 * Configure 20/40 operation
1758 *
1759 * 20/40 = joint rx clear (control and extension)
1760 * 20 = rx clear (control)
1761 *
1762 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1763 * when changing from 20/40 => 20 only
1764 */
1765void
1766ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1767{
1768 u_int32_t macmode;
1769
1770 /* Configure MAC for 20/40 operation */
1771 if (mode == HAL_HT_MACMODE_2040 &&
1772 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1773 macmode = AR_2040_JOINED_RX_CLEAR;
1774 } else {
1775 macmode = 0;
1776 }
1777 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1778}
1779
1780/*
1781 * Get Rx clear (control/extension channel)
1782 *
1783 * Returns active low (busy) for ctrl/ext channel
1784 * Owl 2.0
1785 */
1786HAL_HT_RXCLEAR
1787ar9300_get_11n_rx_clear(struct ath_hal *ah)
1788{
1789 HAL_HT_RXCLEAR rxclear = 0;
1790 u_int32_t val;
1791
1792 val = OS_REG_READ(ah, AR_DIAG_SW);
1793
1794 /* control channel */
1795 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) {
1796 rxclear |= HAL_RX_CLEAR_CTL_LOW;
1797 }
1798 /* extension channel */
1799 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) {
1800 rxclear |= HAL_RX_CLEAR_EXT_LOW;
1801 }
1802 return rxclear;
1803}
1804
1805/*
1806 * Set Rx clear (control/extension channel)
1807 *
1808 * Useful for forcing the channel to appear busy for
1809 * debugging/diagnostics
1810 * Owl 2.0
1811 */
1812void
1813ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
1814{
1815 /* control channel */
1816 if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
1817 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1818 } else {
1819 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1820 }
1821 /* extension channel */
1822 if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
1823 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1824 } else {
1825 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1826 }
1827}
1828
1829
1830/*
1831 * HAL support code for force ppm tracking workaround.
1832 */
1833
1834u_int32_t
1835ar9300_ppm_get_rssi_dump(struct ath_hal *ah)
1836{
1837 u_int32_t retval;
1838 u_int32_t off1;
1839 u_int32_t off2;
1840
1841 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1842 off1 = 0x2000;
1843 off2 = 0x1000;
1844 } else {
1845 off1 = 0x1000;
1846 off2 = 0x2000;
1847 }
1848
1849 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) |
1850 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) |
1851 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16);
1852
1853 return retval;
1854}
1855
1856u_int32_t
1857ar9300_ppm_force(struct ath_hal *ah)
1858{
1859 u_int32_t data_fine;
1860 u_int32_t data4;
1861 //u_int32_t off1;
1862 //u_int32_t off2;
1863 HAL_BOOL signed_val = AH_FALSE;
1864
1865// if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1866// off1 = 0x2000;
1867// off2 = 0x1000;
1868// } else {
1869// off1 = 0x1000;
1870// off2 = 0x2000;
1871// }
1872 data_fine =
1873 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK &
1874 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF);
1875
1876 /*
1877 * bit [11-0] is new ppm value. bit 11 is the signed bit.
1878 * So check value from bit[10:0].
1879 * Now get the abs val of the ppm value read in bit[0:11].
1880 * After that do bound check on abs value.
1881 * if value is off limit, CAP the value and and restore signed bit.
1882 */
1883 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1884 {
1885 /* get the positive value */
1886 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1887 signed_val = AH_TRUE;
1888 }
1889 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1890 {
1891 HALDEBUG(ah, HAL_DEBUG_REGIO,
1892 "%s Correcting ppm out of range %x\n",
1893 __func__, (data_fine & 0x7ff));
1894 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1895 }
1896 /*
1897 * Restore signed value if changed above.
1898 * Use typecast to avoid compilation errors
1899 */
1900 if (signed_val) {
1901 data_fine = (-(int32_t)data_fine) &
1902 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1903 }
1904
1905 /* write value */
1906 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) &
1907 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1908 OS_REG_WRITE(ah, AR_PHY_TIMING2,
1909 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM);
1910
1911 return data_fine;
1912}
1913
1914void
1915ar9300_ppm_un_force(struct ath_hal *ah)
1916{
1917 u_int32_t data4;
1918
1919 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM;
1920 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4);
1921}
1922
1923u_int32_t
1924ar9300_ppm_arm_trigger(struct ath_hal *ah)
1925{
1926 u_int32_t val;
1927 u_int32_t ret;
1928
1929 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY);
1930 ret = OS_REG_READ(ah, AR_TSF_L32);
1931 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY,
1932 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK);
1933
1934 /* return low word of TSF at arm time */
1935 return ret;
1936}
1937
1938int
1939ar9300_ppm_get_trigger(struct ath_hal *ah)
1940{
1941 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) &
1942 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK)
1943 {
1944 /* has not triggered yet, return AH_FALSE */
1945 return 0;
1946 }
1947
1948 /* else triggered, return AH_TRUE */
1949 return 1;
1950}
1951
1952void
1953ar9300_mark_phy_inactive(struct ath_hal *ah)
1954{
1955 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1956}
1957
1958/* DEBUG */
1959u_int32_t
1960ar9300_ppm_get_force_state(struct ath_hal *ah)
1961{
1962 return
1963 OS_REG_READ(ah, AR_PHY_TIMING2) &
1964 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1965}
1966
1967/*
1968 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
1969 */
1970HAL_BOOL
1971ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
1972{
1973 /*
1974 * XXX FreeBSD todo: reimplement this
1975 */
1976#if 0
1977 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
1978 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
1979 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
1980 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
1981 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
1982 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
1983 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
1984 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
1985#endif
1986 return AH_FALSE;
1987}
1988
1989void
1990ar9300_clear_mib_counters(struct ath_hal *ah)
1991{
1992 u_int32_t reg_val;
1993
1994 reg_val = OS_REG_READ(ah, AR_MIBC);
1995 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
1996 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
1997}
1998
1999
2000/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
2001HAL_BOOL
2002ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2003{
2004 struct ath_hal_9300 *ahp = AH9300(ah);
2005 HAL_CHANNEL_INTERNAL *ichan =
2006 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2007 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2008 u_int32_t tmp = 0;
2009
2010 if (enable) {
2011 if (ahp->ah_rifs_enabled == AH_TRUE) {
2012 return AH_TRUE;
2013 }
2014
2015 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2016 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2017 ahp->ah_rifs_reg[1]);
2018
2019 ahp->ah_rifs_enabled = AH_TRUE;
2020 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg));
2021 } else {
2022 if (ahp->ah_rifs_enabled == AH_TRUE) {
2023 ahp->ah_rifs_reg[0] = OS_REG_READ(ah,
2024 AR_PHY_SEARCH_START_DELAY);
2025 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2026 }
2027 /* Change rifs init delay to 0 */
2028 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2029 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2030 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2031 if (is_chan_2g) {
2032 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2033 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2034 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2035 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2036 }
2037 } else {
2038 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2039 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2040 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2041 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2042 }
2043 }
2044
2045 ahp->ah_rifs_enabled = AH_FALSE;
2046 }
2047 return AH_TRUE;
2048
2049} /* ar9300_set_rifs_delay () */
2050
2051/* Set the current RIFS Rx setting */
2052HAL_BOOL
2053ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable)
2054{
2055 /* Non-Owl 11n chips */
2056 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) {
2057 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) {
2058 return ar9300_set_rifs_delay(ah, enable);
2059 }
2060 return AH_FALSE;
2061 }
2062
2063 return AH_TRUE;
2064} /* ar9300_set_11n_rx_rifs () */
2065
2066static hal_mac_hangs_t
2067ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg,
2068 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain)
2069{
2070 int i = 0;
2071 hal_mac_hangs_t found_hangs = 0;
2072
2073 if (hangs & dcu_chain_state) {
2074 for (i = 0; i < 6; i++) {
2075 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) ==
2076 hang_check.dcu_chain_state)
2077 {
2078 found_hangs |= dcu_chain_state;
2079 *dcu_chain = i;
2080 }
2081 }
2082 for (i = 0; i < 4; i++) {
2083 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) ==
2084 hang_check.dcu_chain_state)
2085 {
2086 found_hangs |= dcu_chain_state;
2087 *dcu_chain = i + 6;
2088 }
2089 }
2090 }
2091
2092 if (hangs & dcu_complete_state) {
2093 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) {
2094 found_hangs |= dcu_complete_state;
2095 }
2096 }
2097
2098 return found_hangs;
2099
2100} /* end - ar9300_compare_dbg_hang */
2101
2102#define NUM_STATUS_READS 50
2103HAL_BOOL
2104ar9300_detect_mac_hang(struct ath_hal *ah)
2105{
2106 struct ath_hal_9300 *ahp = AH9300(ah);
2107 mac_dbg_regs_t mac_dbg;
2108 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0};
2109 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state);
2110 int i = 0;
2111 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val;
2112
2113 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) {
2114 return AH_FALSE;
2115 }
2116
2117 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg));
2118
2119 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2120 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2121 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2122
2123 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n",
2124 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
2125 mac_dbg.dma_dbg_6);
2126
2127 if (hang_sig1 !=
2128 ar9300_compare_dbg_hang(ah, mac_dbg,
2129 hang_sig1_val, hang_sig1, &dcu_chain))
2130 {
2131 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n");
2132 return AH_FALSE;
2133 }
2134
2135 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain);
2136 shift_val *= 5;
2137
2138 for (i = 1; i <= NUM_STATUS_READS; i++) {
2139 if (dcu_chain < 6) {
2140 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2141 current_dcu_chain_state =
2142 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f);
2143 } else {
2144 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2145 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f);
2146 }
2147 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2148
2149 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state)
2150 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) {
2151 return AH_FALSE;
2152 }
2153 }
2154 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__,
2155 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]);
2156 ahp->ah_hang[MAC_HANG_SIG1]++;
2157 return AH_TRUE;
2158
2159} /* end - ar9300_detect_mac_hang */
2160
2161/* Determine if the baseband is hung by reading the Observation Bus Register */
2162HAL_BOOL
2163ar9300_detect_bb_hang(struct ath_hal *ah)
2164{
2165#define N(a) (sizeof(a) / sizeof(a[0]))
2166 struct ath_hal_9300 *ahp = AH9300(ah);
2167 u_int32_t hang_sig = 0;
2168 int i = 0;
2169 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times
2170 *
2171 * 4 known BB hang signatures -
2172 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
2173 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52
2174 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18
2175 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
2176 * Rx State (bits 20-24) is 0x7.
2177 */
2178 hal_hw_hang_check_t hang_list [] =
2179 {
2180 /* Offset Reg Value Reg Mask Hang Offset */
2181 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1},
2182 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2},
2183 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3},
2184 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4}
2185 };
2186
2187 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR |
2188 HAL_DFS_BB_HANG_WAR |
2189 HAL_RX_STUCK_LOW_BB_HANG_WAR))) {
2190 return AH_FALSE;
2191 }
2192
2193 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1);
2194 for (i = 1; i <= NUM_STATUS_READS; i++) {
2195 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) {
2196 return AH_FALSE;
2197 }
2198 }
2199
2200 for (i = 0; i < N(hang_list); i++) {
2201 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) {
2202 ahp->ah_hang[hang_list[i].hang_offset]++;
2203 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d "
2204 "sig3count=%d sig4count=%d\n", __func__,
2205 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2],
2206 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]);
2207 return AH_TRUE;
2208 }
2209 }
2210
2211 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! "
2212 "<0x806c>=0x%x\n", __func__, hang_sig);
2213
2214 return AH_FALSE;
2215
2216#undef N
2217} /* end - ar9300_detect_bb_hang () */
2218
2219#undef NUM_STATUS_READS
2220
2221HAL_STATUS
2222ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2223{
2224 struct ath_hal_9300 *ahp = AH9300(ah);
2225 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2226 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2227 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2228 u_int16_t ant_config;
2229 u_int32_t hal_num_ant_config;
2230
2231 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2232 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2233
2234 if (cfg < hal_num_ant_config) {
2235 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2236 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2237 return HAL_OK;
2238 }
2239 }
2240
2241 return HAL_EINVAL;
2242}
2243
2244/*
2245 * Functions to get/set DCS mode
2246 */
2247void
2248ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2249{
2250 AH9300(ah)->ah_dcs_enable = mode;
2251}
2252
2253u_int32_t
2254ar9300_get_dcs_mode(struct ath_hal *ah)
2255{
2256 return AH9300(ah)->ah_dcs_enable;
2257}
2258
2259#if ATH_BT_COEX
2260void
2261ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2262{
2263 struct ath_hal_9300 *ahp = AH9300(ah);
2264
2265 ahp->ah_bt_module = btinfo->bt_module;
2266 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2267 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;
2268 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority;
2269 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active;
2270 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity;
2271 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant;
2272 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation;
2273}
2274
2275void
2276ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf)
2277{
2278 struct ath_hal_9300 *ahp = AH9300(ah);
2279 HAL_BOOL rx_clear_polarity;
2280
2281 /*
2282 * For Kiwi and Osprey, the polarity of rx_clear is active high.
2283 * The bt_rxclear_polarity flag from ath_dev needs to be inverted.
2284 */
2285 rx_clear_polarity = !btconf->bt_rxclear_polarity;
2286
2287 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) |
2288 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) |
2289 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
2290 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
2291 SM(btconf->bt_mode, AR_BT_MODE) |
2292 SM(btconf->bt_quiet_collision, AR_BT_QUIET) |
2293 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) |
2294 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) |
2295 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME);
2296
2297 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR);
2298
2299 if (ahp->ah_bt_coex_single_ant == AH_FALSE) {
2300 /* Enable ACK to go out even though BT has higher priority. */
2301 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT;
2302 }
2303}
2304
2305void
2306ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum)
2307{
2308 struct ath_hal_9300 *ahp = AH9300(ah);
2309
2310 /* clear the old value, then set the new value */
2311 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH;
2312 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH);
2313}
2314
2315void
2316ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
2317{
2318 struct ath_hal_9300 *ahp = AH9300(ah);
2319
2320 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT;
2321 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT;
2322 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT;
2323 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT;
2324
2325 switch (stomp_type) {
2326 case HAL_BT_COEX_STOMP_ALL:
2327 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
2328 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
2329 break;
2330 case HAL_BT_COEX_STOMP_LOW:
2331 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
2332 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
2333 break;
2334 case HAL_BT_COEX_STOMP_ALL_FORCE:
2335 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0;
2336 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1;
2337 break;
2338 case HAL_BT_COEX_STOMP_LOW_FORCE:
2339 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0;
2340 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1;
2341 break;
2342 case HAL_BT_COEX_STOMP_NONE:
2343 case HAL_BT_COEX_NO_STOMP:
2344 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
2345 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
2346 break;
2347 default:
2348 /* There is a force_weight from registry */
2349 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
2350 ahp->ah_bt_coex_wlan_weight[1] = stomp_type;
2351 break;
2352 }
2353}
2354
2355void
2356ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh)
2357{
2358 struct ath_hal_9300 *ahp = AH9300(ah);
2359
2360 /* clear the old value, then set the new value */
2361 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH;
2362 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2363}
2364
2365static void
2366ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2367{
2368 struct ath_hal_9300 *ahp = AH9300(ah);
2369#if ATH_ANT_DIV_COMB
2370 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2371 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2372#endif
2373
2374 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2375 {
2376 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2377 {
2378 /* Config antenna diversity */
2379#if ATH_ANT_DIV_COMB
2380 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan);
2381#endif
2382 }
2383 }
2384}
2385
2386
2387void
2388ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
2389 u_int32_t value)
2390{
2391 struct ath_hal_9300 *ahp = AH9300(ah);
2392 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2393
2394 switch (type) {
2395 case HAL_BT_COEX_SET_ACK_PWR:
2396 if (value) {
2397 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2398 } else {
2399 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2400 }
2401 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2402 ahpriv->ah_extraTxPow, 0);
2403 break;
2404
2405 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2406 if (AR_SREV_POSEIDON(ah)) {
2407 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2408 if (value) {
2409 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2410 }
2411 else {
2412 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2413 }
2414 ar9300_bt_coex_antenna_diversity(ah, value);
2415 }
2416 break;
2417 case HAL_BT_COEX_LOWER_TX_PWR:
2418 if (value) {
2419 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2420 }
2421 else {
2422 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2423 }
2424 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2425 ahpriv->ah_extraTxPow, 0);
2426 break;
2427#if ATH_SUPPORT_MCI
2428 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2429 if ((ah->ah_config.ath_hal_mci_config &
2430 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2431 {
2432 if (value) {
2433 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2434 ahp->ah_mci_concur_tx_en = AH_TRUE;
2435 }
2436 else {
2437 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2438 ahp->ah_mci_concur_tx_en = AH_FALSE;
2439 }
2440 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2441 ahpriv->ah_extraTxPow, 0);
2442 }
2443 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2444 ahp->ah_mci_concur_tx_en);
2445 break;
2446 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2447 if (value) {
2448 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2449 }
2450 else {
2451 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2452 }
2453 break;
2454#endif
2455 default:
2456 break;
2457 }
2458}
2459
2460void
2461ar9300_bt_coex_disable(struct ath_hal *ah)
2462{
2463 struct ath_hal_9300 *ahp = AH9300(ah);
2464
2465 /* Always drive rx_clear_external output as 0 */
2466 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2467 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2468
2469 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2470 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2471 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2472 }
2473
2474 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
2475 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
2476 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
2477 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
2478 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
2479 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
2480 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
2481 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
2482
2483 ahp->ah_bt_coex_enabled = AH_FALSE;
2484}
2485
2486int
2487ar9300_bt_coex_enable(struct ath_hal *ah)
2488{
2489 struct ath_hal_9300 *ahp = AH9300(ah);
2490
2491 /* Program coex mode and weight registers to actually enable coex */
2492 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode);
2493 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2);
2494 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]);
2495 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]);
2496 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]);
2497 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]);
2498 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]);
2499 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]);
2500
2501 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) {
2502 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);
2503 } else {
2504 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);
2505 }
2506
2507 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2508 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2509 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2510 } else {
2511 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2512 }
2513
2514 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2515 /* For 3-wire, configure the desired GPIO port for rx_clear */
2516 ath_hal_gpioCfgOutput(ah,
2517 ahp->ah_wlan_active_gpio_select,
2518 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2519 }
2520 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2521 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2522 {
2523 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2524 ath_hal_gpioCfgOutput(ah,
2525 ahp->ah_wlan_active_gpio_select,
2526 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2527 }
2528
2529 /*
2530 * Enable a weak pull down on BT_ACTIVE.
2531 * When BT device is disabled, BT_ACTIVE might be floating.
2532 */
2533 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU),
2534 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)),
2535 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2)));
2536
2537 ahp->ah_bt_coex_enabled = AH_TRUE;
2538
2539 return 0;
2540}
2541
2542u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg)
2543{
2544 return 0;
2545}
2546
2547u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn)
2548{
2549 return bOn;
2550}
2551
2552void
2553ar9300_init_bt_coex(struct ath_hal *ah)
2554{
2555 struct ath_hal_9300 *ahp = AH9300(ah);
2556
2557 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2558 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2559 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
2560 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
2561
2562 /*
2563 * Set input mux for bt_prority_async and
2564 * bt_active_async to GPIO pins
2565 */
2566 OS_REG_RMW_FIELD(ah,
2567 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2568 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2569 ahp->ah_bt_active_gpio_select);
2570 OS_REG_RMW_FIELD(ah,
2571 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2572 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2573 ahp->ah_bt_priority_gpio_select);
2574
2575 /* Configure the desired GPIO ports for input */
2576 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2577 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2578
2579 if (ahp->ah_bt_coex_enabled) {
2580 ar9300_bt_coex_enable(ah);
2581 } else {
2582 ar9300_bt_coex_disable(ah);
2583 }
2584 }
2585 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2586 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2587 {
2588 /* 2-wire */
2589 if (ahp->ah_bt_coex_enabled) {
2590 /* Connect bt_active_async to baseband */
2591 OS_REG_CLR_BIT(ah,
2592 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2593 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
2594 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
2595 OS_REG_SET_BIT(ah,
2596 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2597 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
2598
2599 /*
2600 * Set input mux for bt_prority_async and
2601 * bt_active_async to GPIO pins
2602 */
2603 OS_REG_RMW_FIELD(ah,
2604 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2605 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2606 ahp->ah_bt_active_gpio_select);
2607
2608 /* Configure the desired GPIO ports for input */
2609 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2610
2611 /* Enable coexistence on initialization */
2612 ar9300_bt_coex_enable(ah);
2613 }
2614 }
2615#if ATH_SUPPORT_MCI
2616 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2617 if (ahp->ah_bt_coex_enabled) {
2618 ar9300_mci_bt_coex_enable(ah);
2619 }
2620 else {
2621 ar9300_mci_bt_coex_disable(ah);
2622 }
2623 }
2624#endif /* ATH_SUPPORT_MCI */
2625}
2626
2627#endif /* ATH_BT_COEX */
2628
2629HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable)
2630{
2631 u_int32_t val;
2632 int wasp_mm_rev;
2633
2634#define AR_SOC_RST_REVISION_ID 0xB8060090
2635#define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
2636 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) &
2637 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >>
2638 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT;
2639#undef AR_SOC_RST_REVISION_ID
2640#undef REG_READ
2641
2642 /*
2643 * Azimuth (ProxySTA) Mode is only supported correctly by
2644 * Peacock or WASP 1.3.0.1 or later (hopefully) chips.
2645 *
2646 * Enable this feature for Scorpion at this time. The silicon
2647 * still needs to be validated.
2648 */
2649 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) &&
2650 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) &&
2651 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) &&
2652 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) ||
2653 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 &&
2654 wasp_mm_rev >= 0 /* 1 */))))
2655 {
2656 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, "
2657 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n",
2658 __func__, AH_PRIVATE((ah))->ah_macVersion,
2659 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev);
2660 return HAL_ENOTSUPP;
2661 }
2662
2663 OS_REG_WRITE(ah,
2664 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996);
2665
2666 /* turn on mode bit[24] for proxy sta */
2667 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2,
2668 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA);
2669
2670 val = OS_REG_READ(ah, AR_AZIMUTH_MODE);
2671 if (enable) {
2672 val |= AR_AZIMUTH_KEY_SEARCH_AD1 |
2673 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2674 AR_AZIMUTH_BA_USES_AD1;
2675 /* turn off filter pass hold (bit 9) */
2676 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD;
2677 } else {
2678 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 |
2679 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2680 AR_AZIMUTH_BA_USES_AD1);
2681 }
2682 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val);
2683
2684 /* enable promiscous mode */
2685 OS_REG_WRITE(ah, AR_RX_FILTER,
2686 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM);
2687 /* enable promiscous in azimuth mode */
2688 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE);
2689 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE);
2690
2691 /* turn on filter pass hold (bit 9) */
2692 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2693 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2694
2695 return HAL_OK;
2696}
2697
2698#if 0
2699void ar9300_mat_enable(struct ath_hal *ah, int enable)
2700{
2701 /*
2702 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2703 * mitigation and turn on key search always for better performance.
2704 */
2705 struct ath_hal_9300 *ahp = AH9300(ah);
2706 struct ath_hal_private *ap = AH_PRIVATE(ah);
2707
2708 ahp->ah_intr_mitigation_rx = !enable;
2709 if (ahp->ah_intr_mitigation_rx) {
2710 /*
2711 * Enable Interrupt Mitigation for Rx.
2712 * If no build-specific limits for the rx interrupt mitigation
2713 * timer have been specified, use conservative defaults.
2714 */
2715 #ifndef AH_RIMT_VAL_LAST
2716 #define AH_RIMT_LAST_MICROSEC 500
2717 #endif
2718 #ifndef AH_RIMT_VAL_FIRST
2719 #define AH_RIMT_FIRST_MICROSEC 2000
2720 #endif
2721 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2722 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2723 } else {
2724 OS_REG_WRITE(ah, AR_RIMT, 0);
2725 }
2726
2727 ahp->ah_enable_keysearch_always = !!enable;
2728 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2729}
2730#endif
2731
2732void ar9300_enable_tpc(struct ath_hal *ah)
2733{
2734 u_int32_t val = 0;
2735
2736 ah->ah_config.ath_hal_desc_tpc = 1;
2737
2738 /* Enable TPC */
2739 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2740
2741 /*
2742 * Disable per chain power reduction since we are already
2743 * accounting for this in our calculations
2744 */
2745 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB);
2746 if (AR_SREV_WASP(ah)) {
2747 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2748 val & AR_PHY_POWER_TX_SUB_2_DISABLE);
2749 } else {
2750 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2751 val & AR_PHY_POWER_TX_SUB_3_DISABLE);
2752 }
2753}
2754
2755
2756/*
2757 * ar9300_force_tsf_sync
2758 * This function forces the TSF sync to the given bssid, this is implemented
2759 * as a temp hack to get the AoW demo, and is primarily used in the WDS client
2760 * mode of operation, where we sync the TSF to RootAP TSF values
2761 */
2762void
2763ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid,
2764 u_int16_t assoc_id)
2765{
2766 ar9300_set_operating_mode(ah, HAL_M_STA);
2767 ar9300_write_associd(ah, bssid, assoc_id);
2768}
2769
2770void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
2771{
2772 struct ath_hal_9300 *ahp = AH9300(ah);
2773 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val;
2774 u_int32_t temp_powertx_rate9_reg_val;
2775 int8_t olpc_power_offset = 0;
2776 int8_t tmp_olpc_val = 0;
2777 HAL_RSSI_TX_POWER old_greentx_status;
2778 u_int8_t target_power_val_t[ar9300_rate_size];
2779 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2780
2781 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2782 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2783 return;
2784 }
2785
2786 old_greentx_status = AH9300(ah)->green_tx_status;
2787 if (ahp->ah_hw_green_tx_enable) {
2788 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2789 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2790 } else {
2791 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2792 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2793 }
2794
2795 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2796 && (rssi > tmp_rss1_thr1))
2797 {
2798 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2799 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2800 }
2801 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2802 && (rssi > tmp_rss1_thr2))
2803 {
2804 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2805 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2806 }
2807 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2808 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2809 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2810 }
2811 }
2812
2813 /* If status is not change, don't do anything */
2814 if (old_greentx_status == AH9300(ah)->green_tx_status) {
2815 return;
2816 }
2817
2818 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2819 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2820 && AR_SREV_POSEIDON(ah))
2821 {
2822 if (ahp->ah_hw_green_tx_enable) {
2823 switch (AH9300(ah)->green_tx_status) {
2824 case HAL_RSSI_TX_POWER_SHORT:
2825 /* 1. TxPower Config */
2826 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2827 sizeof(target_power_val_t));
2828 /* 1.1 Store OLPC Delta Calibration Offset*/
2829 olpc_power_offset = 0;
2830 /* 2. Store OB/DB */
2831 /* 3. Store TPC settting */
2832 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
2833 SM(14, AR_TPC_CTS) |
2834 SM(14, AR_TPC_CHIRP) |
2835 SM(14, AR_TPC_RPT));
2836 /* 4. Store BB_powertx_rate9 value */
2837 temp_powertx_rate9_reg_val =
2838 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE;
2839 break;
2840 case HAL_RSSI_TX_POWER_MIDDLE:
2841 /* 1. TxPower Config */
2842 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle,
2843 sizeof(target_power_val_t));
2844 /* 1.1 Store OLPC Delta Calibration Offset*/
2845 olpc_power_offset = 0;
2846 /* 2. Store OB/DB */
2847 /* 3. Store TPC settting */
2848 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) |
2849 SM(18, AR_TPC_CTS) |
2850 SM(18, AR_TPC_CHIRP) |
2851 SM(18, AR_TPC_RPT));
2852 /* 4. Store BB_powertx_rate9 value */
2853 temp_powertx_rate9_reg_val =
2854 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE;
2855 break;
2856 case HAL_RSSI_TX_POWER_LONG:
2857 default:
2858 /* 1. TxPower Config */
2859 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2860 sizeof(target_power_val_t));
2861 /* 1.1 Store OLPC Delta Calibration Offset*/
2862 olpc_power_offset = 0;
2863 /* 2. Store OB/DB1/DB2 */
2864 /* 3. Store TPC settting */
2865 temp_tcp_reg_val =
2866 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2867 /* 4. Store BB_powertx_rate9 value */
2868 temp_powertx_rate9_reg_val =
2869 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2870 break;
2871 }
2872 } else {
2873 switch (AH9300(ah)->green_tx_status) {
2874 case HAL_RSSI_TX_POWER_SHORT:
2875 /* 1. TxPower Config */
2876 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2877 sizeof(target_power_val_t));
2878 /* 1.1 Store OLPC Delta Calibration Offset*/
2879 olpc_power_offset =
2880 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2881 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2882 /* 2. Store OB/DB */
2883 temp_obdb_reg_val =
2884 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2885 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2886 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2887 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2888 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2889 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2890 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2891 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2892 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2893 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
2894 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2895 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
2896 /* 3. Store TPC settting */
2897 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) |
2898 SM(6, AR_TPC_CTS) |
2899 SM(6, AR_TPC_CHIRP) |
2900 SM(6, AR_TPC_RPT));
2901 /* 4. Store BB_powertx_rate9 value */
2902 temp_powertx_rate9_reg_val =
2903 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE;
2904 break;
2905 case HAL_RSSI_TX_POWER_MIDDLE:
2906 /* 1. TxPower Config */
2907 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
2908 sizeof(target_power_val_t));
2909 /* 1.1 Store OLPC Delta Calibration Offset*/
2910 olpc_power_offset =
2911 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
2912 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2913 /* 2. Store OB/DB */
2914 temp_obdb_reg_val =
2915 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2916 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2917 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2918 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2919 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2920 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2921 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2922 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2923 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2924 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
2925 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
2926 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
2927 /* 3. Store TPC settting */
2928 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
2929 SM(14, AR_TPC_CTS) |
2930 SM(14, AR_TPC_CHIRP) |
2931 SM(14, AR_TPC_RPT));
2932 /* 4. Store BB_powertx_rate9 value */
2933 temp_powertx_rate9_reg_val =
2934 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE;
2935 break;
2936 case HAL_RSSI_TX_POWER_LONG:
2937 default:
2938 /* 1. TxPower Config */
2939 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2940 sizeof(target_power_val_t));
2941 /* 1.1 Store OLPC Delta Calibration Offset*/
2942 olpc_power_offset =
2943 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
2944 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2945 /* 2. Store OB/DB1/DB2 */
2946 temp_obdb_reg_val =
2947 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2948 /* 3. Store TPC settting */
2949 temp_tcp_reg_val =
2950 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2951 /* 4. Store BB_powertx_rate9 value */
2952 temp_powertx_rate9_reg_val =
2953 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2954 break;
2955 }
2956 }
2957 /* 1.1 Do OLPC Delta Calibration Offset */
2958 tmp_olpc_val =
2959 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
2960 tmp_olpc_val += olpc_power_offset;
2961 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
2962 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
2963 AR_PHY_TPC_OLPC_GAIN_DELTA);
2964
2965 /* 1.2 TxPower Config */
2966 ar9300_transmit_power_reg_write(ah, target_power_val_t);
2967 /* 2. Config OB/DB */
2968 if (!ahp->ah_hw_green_tx_enable) {
2969 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
2970 }
2971 /* 3. config TPC settting */
2972 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
2973 /* 4. config BB_powertx_rate9 value */
2974 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
2975 }
2976}
2977
2978#if 0
2979void
2980ar9300_get_vow_stats(
2981 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
2982{
2983 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
2984 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2985 }
2986 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {
2987 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
2988 }
2989 if (vow_reg_flags & AR_REG_RX_CLR_CNT) {
2990 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
2991 }
2992 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
2993 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2994 }
2995 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
2996 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
2997 }
2998}
2999#endif
3000
3001/*
3002 * ar9300_is_skip_paprd_by_greentx
3003 *
3004 * This function check if we need to skip PAPRD tuning
3005 * when GreenTx in specific state.
3006 */
3007HAL_BOOL
3008ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3009{
3010 if (AR_SREV_POSEIDON(ah) &&
3011 ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3012 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3013 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3014 {
3015 return AH_TRUE;
3016 }
3017 return AH_FALSE;
3018}
3019
3020void
3021ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)
3022{
3023 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3]
3024 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3]
3025 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3]
3026 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3]
3027 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3]
3028 struct ath_hal_9300 *ahp = AH9300(ah);
3029
3030 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3031 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3032 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0);
3033 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3034 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0);
3035 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3036 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0);
3037 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3038 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0);
3039 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3040 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0);
3041 }
3042}
3043
3044void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value)
3045{
3046 struct ath_hal_9300 *ahp = AH9300(ah);
3047
3048 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3049 if ((value == 0) || (value == 1)) {
3050 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
3051 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value);
3052 }
3053 }
3054}
3055
3056void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah)
3057{
3058 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC);
3059}
3060
3061int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah)
3062{
3063 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL);
3064
3065 /* RSSI format is 8.4. Ignore lowest four bits */
3066 val = val >> 4;
3067 return val;
3068}
3069
3070void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah,
3071 u_int32_t rssi_threshold)
3072{
3073 struct ath_hal_9300 *ahp = AH9300(ah);
3074
3075 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold);
3076
3077 /* save value for restoring after chip reset */
3078 ahp->ah_beacon_rssi_threshold = rssi_threshold;
3079}
3080
3081void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah)
3082{
3083 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST);
3084}
3085
3086void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on)
3087{
3088 if (on) {
3089 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3090 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3091 }
3092 else {
3093 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3094 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3095 }
3096}
3097/*
3098 * Gets the contents of the specified key cache entry.
3099 */
3100HAL_BOOL
3101ar9300_print_keycache(struct ath_hal *ah)
3102{
3103
3104 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3105 u_int32_t key0, key1, key2, key3, key4;
3106 u_int32_t mac_hi, mac_lo;
3107 u_int16_t entry = 0;
3108 u_int32_t valid = 0;
3109 u_int32_t key_type;
3110
3111 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3112
3113 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3114 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3115 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3116 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3117 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3118 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3119
3120 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3121
3122 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry));
3123 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
3124
3125 if (mac_hi & AR_KEYTABLE_VALID) {
3126 valid = 1;
3127 } else {
3128 valid = 0;
3129 }
3130
3131 if ((mac_hi != 0) && (mac_lo != 0)) {
3132 mac_hi &= ~0x8000;
3133 mac_hi <<= 1;
3134 mac_hi |= ((mac_lo & (1 << 31) )) >> 31;
3135 mac_lo <<= 1;
3136 }
3137
3138 ath_hal_printf(ah,
3139 "%03d "
3140 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
3141 " %02d %02d "
3142 "%02x:%02x:%02x:%02x:%02x:%02x \n",
3143 entry,
3144 (key0 << 24) >> 24, (key0 << 16) >> 24,
3145 (key0 << 8) >> 24, key0 >> 24,
3146 (key1 << 24) >> 24, (key1 << 16) >> 24,
3147 //(key1 << 8) >> 24, key1 >> 24,
3148 (key2 << 24) >> 24, (key2 << 16) >> 24,
3149 (key2 << 8) >> 24, key2 >> 24,
3150 (key3 << 24) >> 24, (key3 << 16) >> 24,
3151 //(key3 << 8) >> 24, key3 >> 24,
3152 (key4 << 24) >> 24, (key4 << 16) >> 24,
3153 (key4 << 8) >> 24, key4 >> 24,
3154 valid, key_type,
3155 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3156 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3157 }
3158
3159 return AH_TRUE;
3160}
3161
3162/* enable/disable smart antenna mode */
3163HAL_BOOL
3164ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3165{
3166 struct ath_hal_9300 *ahp = AH9300(ah);
3167
3168 if (enable) {
3169 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3170 } else {
3171 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3172 }
3173
3174 /* if scropion and smart antenna is enabled, write swcom1 with 0x440
3175 * and swcom2 with 0
3176 * FIXME Ideally these registers need to be made read from caldata.
3177 * Until the calibration team gets them, keep them along with board
3178 * configuration.
3179 */
3180 if (enable && AR_SREV_SCORPION(ah) &&
3181 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) {
3182
3183 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440);
3184 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0);
3185 }
3186
3187 ahp->ah_smartantenna_enable = enable;
3188 return 1;
3189}
3190
3191#ifdef ATH_TX99_DIAG
3192#ifndef ATH_SUPPORT_HTC
3193void
3194ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3195 u_int32_t txpower)
3196{
3197#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3198 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3199 int32_t i;
3200
3201 /* The max power is limited to 63 */
3202 if (txpower <= AR9300_MAX_RATE_POWER) {
3203 for (i = 0; i < ar9300_rate_size; i++) {
3204 p_pwr_array[i] = txpower;
3205 }
3206 } else {
3207 for (i = 0; i < ar9300_rate_size; i++) {
3208 p_pwr_array[i] = AR9300_MAX_RATE_POWER;
3209 }
3210 }
3211
3212 OS_REG_WRITE(ah, 0xa458, 0);
3213
3214 /* Write the OFDM power per rate set */
3215 /* 6 (LSB), 9, 12, 18 (MSB) */
3216 OS_REG_WRITE(ah, 0xa3c0,
3217 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24)
3218 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16)
3219 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8)
3220 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3221 );
3222 /* 24 (LSB), 36, 48, 54 (MSB) */
3223 OS_REG_WRITE(ah, 0xa3c4,
3224 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24)
3225 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16)
3226 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8)
3227 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3228 );
3229
3230 /* Write the CCK power per rate set */
3231 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3232 OS_REG_WRITE(ah, 0xa3c8,
3233 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24)
3234 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16)
3235 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */
3236 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3237 );
3238 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3239 OS_REG_WRITE(ah, 0xa3cc,
3240 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24)
3241 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16)
3242 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8)
3243 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3244 );
3245
3246 /* Write the HT20 power per rate set */
3247 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3248 OS_REG_WRITE(ah, 0xa3d0,
3249 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24)
3250 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16)
3251 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)
3252 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0)
3253 );
3254
3255 /* 6 (LSB), 7, 12, 13 (MSB) */
3256 OS_REG_WRITE(ah, 0xa3d4,
3257 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24)
3258 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16)
3259 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8)
3260 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0)
3261 );
3262
3263 /* 14 (LSB), 15, 20, 21 */
3264 OS_REG_WRITE(ah, 0xa3e4,
3265 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24)
3266 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16)
3267 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8)
3268 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0)
3269 );
3270
3271 /* Mixed HT20 and HT40 rates */
3272 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3273 OS_REG_WRITE(ah, 0xa3e8,
3274 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24)
3275 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16)
3276 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8)
3277 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0)
3278 );
3279
3280 /* Write the HT40 power per rate set */
3281 /* correct PAR difference between HT40 and HT20/LEGACY */
3282 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3283 OS_REG_WRITE(ah, 0xa3d8,
3284 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24)
3285 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16)
3286 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8)
3287 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0)
3288 );
3289
3290 /* 6 (LSB), 7, 12, 13 (MSB) */
3291 OS_REG_WRITE(ah, 0xa3dc,
3292 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24)
3293 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16)
3294 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8)
3295 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0)
3296 );
3297
3298 /* 14 (LSB), 15, 20, 21 */
3299 OS_REG_WRITE(ah, 0xa3ec,
3300 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24)
3301 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16)
3302 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8)
3303 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0)
3304 );
3305#undef PWR_MAS
3306}
3307
3308void
3309ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask)
3310{
3311 if (tx_chainmask == 0x5) {
3312 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3313 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3314 }
3315 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask);
3316 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask);
3317
3318 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
3319 if (tx_chainmask == 0x5) {
3320 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3321 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3322 }
3323}
3324
3325void
3326ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask,
3327 int chtype)
3328{
3329 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff);
3330 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1));
3331 OS_REG_WRITE(ah, 0xa350,
3332 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13));
3333
3334 /* 11G mode */
3335 if (!chtype) {
3336 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3337 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2));
3338 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3339 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3340 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3341 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3342 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3343 | (0x1 << 26) | (0x7 << 24))
3344 & ~(0x1 << 22));
3345 } else {
3346 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3347 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3348 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3349 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3350 | (0x1 << 26) | (0x7 << 24))
3351 & ~(0x1 << 22));
3352 }
3353
3354 /* chain zero */
3355 if ((tx_chain_mask & 0x01) == 0x01) {
3356 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3357 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3358 | (0x1 << 31) | (0x5 << 15)
3359 | (0x3 << 9)) & ~(0x1 << 27)
3360 & ~(0x1 << 12));
3361 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3362 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3363 | (0x1 << 12) | (0x1 << 10)
3364 | (0x1 << 9) | (0x1 << 8)
3365 | (0x1 << 7)) & ~(0x1 << 11));
3366 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3367 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3368 | (0x1 << 29) | (0x1 << 25)
3369 | (0x1 << 23) | (0x1 << 19)
3370 | (0x1 << 10) | (0x1 << 9)
3371 | (0x1 << 8) | (0x1 << 3))
3372 & ~(0x1 << 28)& ~(0x1 << 24)
3373 & ~(0x1 << 22)& ~(0x1 << 7));
3374 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3375 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3376 | (0x1 << 23))& ~(0x1 << 21));
3377 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3378 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3379 | (0x1 << 12) | (0x1 << 10)
3380 | (0x1 << 9) | (0x1 << 8)
3381 | (0x1 << 6) | (0x1 << 5)
3382 | (0x1 << 4) | (0x1 << 3)
3383 | (0x1 << 2));
3384 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3385 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3386 }
3387 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3388 /* chain one */
3389 if ((tx_chain_mask & 0x02) == 0x02 ) {
3390 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3391 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3392 | (0x1 << 31) | (0x5 << 15)
3393 | (0x3 << 9)) & ~(0x1 << 27)
3394 & ~(0x1 << 12));
3395 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3396 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3397 | (0x1 << 12) | (0x1 << 10)
3398 | (0x1 << 9) | (0x1 << 8)
3399 | (0x1 << 7)) & ~(0x1 << 11));
3400 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3401 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3402 | (0x1 << 29) | (0x1 << 25)
3403 | (0x1 << 23) | (0x1 << 19)
3404 | (0x1 << 10) | (0x1 << 9)
3405 | (0x1 << 8) | (0x1 << 3))
3406 & ~(0x1 << 28)& ~(0x1 << 24)
3407 & ~(0x1 << 22)& ~(0x1 << 7));
3408 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3409 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3410 | (0x1 << 23))& ~(0x1 << 21));
3411 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3412 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3413 | (0x1 << 12) | (0x1 << 10)
3414 | (0x1 << 9) | (0x1 << 8)
3415 | (0x1 << 6) | (0x1 << 5)
3416 | (0x1 << 4) | (0x1 << 3)
3417 | (0x1 << 2));
3418 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3419 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3420 }
3421 }
3422 if (AR_SREV_OSPREY(ah)) {
3423 /* chain two */
3424 if ((tx_chain_mask & 0x04) == 0x04 ) {
3425 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3426 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3427 | (0x1 << 31) | (0x5 << 15)
3428 | (0x3 << 9)) & ~(0x1 << 27)
3429 & ~(0x1 << 12));
3430 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3431 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3432 | (0x1 << 12) | (0x1 << 10)
3433 | (0x1 << 9) | (0x1 << 8)
3434 | (0x1 << 7)) & ~(0x1 << 11));
3435 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3436 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3437 | (0x1 << 29) | (0x1 << 25)
3438 | (0x1 << 23) | (0x1 << 19)
3439 | (0x1 << 10) | (0x1 << 9)
3440 | (0x1 << 8) | (0x1 << 3))
3441 & ~(0x1 << 28)& ~(0x1 << 24)
3442 & ~(0x1 << 22)& ~(0x1 << 7));
3443 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3444 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3445 | (0x1 << 23))& ~(0x1 << 21));
3446 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3447 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3448 | (0x1 << 12) | (0x1 << 10)
3449 | (0x1 << 9) | (0x1 << 8)
3450 | (0x1 << 6) | (0x1 << 5)
3451 | (0x1 << 4) | (0x1 << 3)
3452 | (0x1 << 2));
3453 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3454 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3455 }
3456 }
3457
3458 OS_REG_WRITE(ah, 0xa28c, 0x11111);
3459 OS_REG_WRITE(ah, 0xa288, 0x111);
3460 } else {
3461 /* chain zero */
3462 if ((tx_chain_mask & 0x01) == 0x01) {
3463 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3464 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3465 | (0x1 << 31) | (0x1 << 27)
3466 | (0x3 << 23) | (0x1 << 19)
3467 | (0x1 << 15) | (0x3 << 9))
3468 & ~(0x1 << 12));
3469 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3470 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3471 | (0x1 << 12) | (0x1 << 10)
3472 | (0x1 << 9) | (0x1 << 8)
3473 | (0x1 << 7) | (0x1 << 3)
3474 | (0x1 << 2) | (0x1 << 1))
3475 & ~(0x1 << 11)& ~(0x1 << 0));
3476 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3477 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3478 | (0x1 << 29) | (0x1 << 25)
3479 | (0x1 << 23) | (0x1 << 19)
3480 | (0x1 << 10) | (0x1 << 9)
3481 | (0x1 << 8) | (0x1 << 3))
3482 & ~(0x1 << 28)& ~(0x1 << 24)
3483 & ~(0x1 << 22)& ~(0x1 << 7));
3484 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3485 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3486 | (0x1 << 23))& ~(0x1 << 21));
3487 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2,
3488 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
3489 | (0x3 << 3) | (0x3 << 0));
3490 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3,
3491 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
3492 | (0x3 << 29) | (0x3 << 26)
3493 | (0x2 << 23) | (0x2 << 20)
3494 | (0x2 << 17))& ~(0x1 << 14));
3495 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3496 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3497 | (0x1 << 12) | (0x1 << 10)
3498 | (0x1 << 9) | (0x1 << 8)
3499 | (0x1 << 6) | (0x1 << 5)
3500 | (0x1 << 4) | (0x1 << 3)
3501 | (0x1 << 2));
3502 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3503 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3504 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3505 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3506 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3507 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3508 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3509 | (0x1 << 26) | (0x7 << 24)
3510 | (0x3 << 22));
3511 } else {
3512 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3513 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3514 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3515 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3516 | (0x1 << 26) | (0x7 << 24)
3517 | (0x3 << 22));
3518 }
3519
3520 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3521 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3522 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3523 | (0x1 << 3) | (0x1 << 2)
3524 | (0x1 << 1)) & ~(0x1 << 0));
3525 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3526 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3527 | (0x1 << 19) | (0x1 << 3));
3528 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3529 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3530 }
3531 if (AR_SREV_OSPREY(ah)) {
3532 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3533 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3534 | (0x1 << 3) | (0x1 << 2)
3535 | (0x1 << 1)) & ~(0x1 << 0));
3536 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3537 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3538 | (0x1 << 19) | (0x1 << 3));
3539 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3540 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3541 }
3542 }
3543 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3544 /* chain one */
3545 if ((tx_chain_mask & 0x02) == 0x02 ) {
3546 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3547 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3548 | (0x1 << 3) | (0x1 << 2)
3549 | (0x1 << 1)) & ~(0x1 << 0));
3550 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3551 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3552 | (0x1 << 19) | (0x1 << 3));
3553 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3554 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3555 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3556 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3557 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3558 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3559 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3560 | (0x1 << 26) | (0x7 << 24)
3561 | (0x3 << 22));
3562 } else {
3563 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3564 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3565 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3566 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3567 | (0x1 << 26) | (0x7 << 24)
3568 | (0x3 << 22));
3569 }
3570
3571 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3572 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3573 | (0x1 << 31) | (0x1 << 27)
3574 | (0x3 << 23) | (0x1 << 19)
3575 | (0x1 << 15) | (0x3 << 9))
3576 & ~(0x1 << 12));
3577 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3578 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3579 | (0x1 << 12) | (0x1 << 10)
3580 | (0x1 << 9) | (0x1 << 8)
3581 | (0x1 << 7) | (0x1 << 3)
3582 | (0x1 << 2) | (0x1 << 1))
3583 & ~(0x1 << 11)& ~(0x1 << 0));
3584 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3585 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3586 | (0x1 << 29) | (0x1 << 25)
3587 | (0x1 << 23) | (0x1 << 19)
3588 | (0x1 << 10) | (0x1 << 9)
3589 | (0x1 << 8) | (0x1 << 3))
3590 & ~(0x1 << 28)& ~(0x1 << 24)
3591 & ~(0x1 << 22)& ~(0x1 << 7));
3592 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3593 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3594 | (0x1 << 23))& ~(0x1 << 21));
3595 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2,
3596 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
3597 | (0x3 << 3) | (0x3 << 0));
3598 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3,
3599 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
3600 | (0x3 << 29) | (0x3 << 26)
3601 | (0x2 << 23) | (0x2 << 20)
3602 | (0x2 << 17))& ~(0x1 << 14));
3603 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3604 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3605 | (0x1 << 12) | (0x1 << 10)
3606 | (0x1 << 9) | (0x1 << 8)
3607 | (0x1 << 6) | (0x1 << 5)
3608 | (0x1 << 4) | (0x1 << 3)
3609 | (0x1 << 2));
3610 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3611 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3612
3613 if (AR_SREV_OSPREY(ah)) {
3614 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3615 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3616 | (0x1 << 3) | (0x1 << 2)
3617 | (0x1 << 1)) & ~(0x1 << 0));
3618 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3619 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3620 | (0x1 << 19) | (0x1 << 3));
3621 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3622 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3623 }
3624 }
3625 }
3626 if (AR_SREV_OSPREY(ah)) {
3627 /* chain two */
3628 if ((tx_chain_mask & 0x04) == 0x04 ) {
3629 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3630 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3631 | (0x1 << 3) | (0x1 << 2)
3632 | (0x1 << 1)) & ~(0x1 << 0));
3633 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3634 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3635 | (0x1 << 19) | (0x1 << 3));
3636 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3637 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3638 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3639 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3640 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3641 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3642 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3643 | (0x1 << 26) | (0x7 << 24)
3644 | (0x3 << 22));
3645 } else {
3646 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3647 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3648 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3649 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3650 | (0x1 << 26) | (0x7 << 24)
3651 | (0x3 << 22));
3652 }
3653
3654 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3655 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3656 | (0x1 << 3) | (0x1 << 2)
3657 | (0x1 << 1)) & ~(0x1 << 0));
3658 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3659 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3660 | (0x1 << 19) | (0x1 << 3));
3661 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3662 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3663
3664 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3665 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3666 | (0x1 << 31) | (0x1 << 27)
3667 | (0x3 << 23) | (0x1 << 19)
3668 | (0x1 << 15) | (0x3 << 9))
3669 & ~(0x1 << 12));
3670 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3671 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3672 | (0x1 << 12) | (0x1 << 10)
3673 | (0x1 << 9) | (0x1 << 8)
3674 | (0x1 << 7) | (0x1 << 3)
3675 | (0x1 << 2) | (0x1 << 1))
3676 & ~(0x1 << 11)& ~(0x1 << 0));
3677 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3678 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3679 | (0x1 << 29) | (0x1 << 25)
3680 | (0x1 << 23) | (0x1 << 19)
3681 | (0x1 << 10) | (0x1 << 9)
3682 | (0x1 << 8) | (0x1 << 3))
3683 & ~(0x1 << 28)& ~(0x1 << 24)
3684 & ~(0x1 << 22)& ~(0x1 << 7));
3685 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3686 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3687 | (0x1 << 23))& ~(0x1 << 21));
3688 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2,
3689 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
3690 | (0x3 << 3) | (0x3 << 0));
3691 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3,
3692 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
3693 | (0x3 << 29) | (0x3 << 26)
3694 | (0x2 << 23) | (0x2 << 20)
3695 | (0x2 << 17))& ~(0x1 << 14));
3696 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3697 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3698 | (0x1 << 12) | (0x1 << 10)
3699 | (0x1 << 9) | (0x1 << 8)
3700 | (0x1 << 6) | (0x1 << 5)
3701 | (0x1 << 4) | (0x1 << 3)
3702 | (0x1 << 2));
3703 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3704 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3705 }
3706 }
3707
3708 OS_REG_WRITE(ah, 0xa28c, 0x22222);
3709 OS_REG_WRITE(ah, 0xa288, 0x222);
3710 }
3711}
3712
3713void
3714ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data)
3715{
3716 u_int32_t val;
3717 u_int32_t qnum = (u_int32_t)data;
3718
3719 /* Disable AGC to A2 */
3720 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR));
|