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ar9300_gpio.c (250008) ar9300_gpio.c (278759)
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH

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157 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 */
158 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2,
159 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_SWCOM3 */
160 AR_GPIO_OUTPUT_MUX_AS_SWCOM3,
161 };
162
163 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
164 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH

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157 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 */
158 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2,
159 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_SWCOM3 */
160 AR_GPIO_OUTPUT_MUX_AS_SWCOM3,
161 };
162
163 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
164 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
165 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
166 (gpio == AR9382_GPIO_9_INPUT_ONLY))
167 {
168 return AH_FALSE;
169 }
170
171 /* Convert HAL signal type definitions to hardware-specific values. */
172 if ((int) hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table))
173 {

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343 */
344HAL_BOOL
345ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio)
346{
347 u_int32_t gpio_shift;
348
349 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
350 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
165 (gpio == AR9382_GPIO_9_INPUT_ONLY))
166 {
167 return AH_FALSE;
168 }
169
170 /* Convert HAL signal type definitions to hardware-specific values. */
171 if ((int) hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table))
172 {

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342 */
343HAL_BOOL
344ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio)
345{
346 u_int32_t gpio_shift;
347
348 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
349 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
351 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
352 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
353 {
354 return AH_FALSE;
355 }
356
357 if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) {
358 OS_REG_SET_BIT(ah,
359 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE);

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373 * Once configured for I/O - set output lines
374 * output the level of GPio PIN without care work mode
375 */
376HAL_BOOL
377ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val)
378{
379 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
380 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
350 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
351 {
352 return AH_FALSE;
353 }
354
355 if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) {
356 OS_REG_SET_BIT(ah,
357 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE);

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371 * Once configured for I/O - set output lines
372 * output the level of GPio PIN without care work mode
373 */
374HAL_BOOL
375ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val)
376{
377 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
378 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
381 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
382 (gpio == AR9382_GPIO_9_INPUT_ONLY))
383 {
384 return AH_FALSE;
385 }
386 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT),
387 ((val & 1) << gpio), AR_GPIO_BIT(gpio));
388
389 return AH_TRUE;
390}
391
392/*
393 * Once configured for I/O - get input lines
394 */
395u_int32_t
396ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio)
397{
398 u_int32_t gpio_in;
399 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
379 (gpio == AR9382_GPIO_9_INPUT_ONLY))
380 {
381 return AH_FALSE;
382 }
383 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT),
384 ((val & 1) << gpio), AR_GPIO_BIT(gpio));
385
386 return AH_TRUE;
387}
388
389/*
390 * Once configured for I/O - get input lines
391 */
392u_int32_t
393ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio)
394{
395 u_int32_t gpio_in;
396 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
400 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
401 (gpio == AR9382_GPIO_PIN_11_RESERVED))
397 if ((gpio == AR9382_GPIO_PIN_8_RESERVED))
402 {
403 return 0xffffffff;
404 }
405
406 gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN));
407 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN),
408 (1 << gpio), AR_GPIO_BIT(gpio));
409 return (MS(gpio_in, AR_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;

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448 regs[1] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK);
449 shifts[0] = AR_INTR_SYNC_ENABLE_GPIO_S;
450 shifts[1] = AR_INTR_SYNC_MASK_GPIO_S;
451#endif
452
453 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
454
455 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
398 {
399 return 0xffffffff;
400 }
401
402 gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN));
403 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN),
404 (1 << gpio), AR_GPIO_BIT(gpio));
405 return (MS(gpio_in, AR_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;

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444 regs[1] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK);
445 shifts[0] = AR_INTR_SYNC_ENABLE_GPIO_S;
446 shifts[1] = AR_INTR_SYNC_MASK_GPIO_S;
447#endif
448
449 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
450
451 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
456 (gpio == AR9382_GPIO_PIN_11_RESERVED) ||
457 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
458 {
459 return;
460 }
461
462#ifdef AH_ASSERT
463 gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1;
464#endif

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544
545u_int32_t
546ar9300_gpio_get_mask(struct ath_hal *ah)
547{
548 u_int32_t mask = (1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1) ) - 1;
549
550 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) {
551 mask = (1 << AR9382_MAX_GPIO_PIN_NUM) - 1;
452 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
453 {
454 return;
455 }
456
457#ifdef AH_ASSERT
458 gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1;
459#endif

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539
540u_int32_t
541ar9300_gpio_get_mask(struct ath_hal *ah)
542{
543 u_int32_t mask = (1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1) ) - 1;
544
545 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) {
546 mask = (1 << AR9382_MAX_GPIO_PIN_NUM) - 1;
552 mask &= ~(1 << AR9382_GPIO_PIN_8_RESERVED |
553 1 << AR9382_GPIO_PIN_11_RESERVED);
547 mask &= ~(1 << AR9382_GPIO_PIN_8_RESERVED);
554 }
555 return mask;
556}
557
558int
559ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map)
560{
561 u_int32_t invalid = ~((1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1)) - 1);
562
563 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) {
564 invalid = ~((1 << AR9382_MAX_GPIO_PIN_NUM) - 1);
548 }
549 return mask;
550}
551
552int
553ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map)
554{
555 u_int32_t invalid = ~((1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1)) - 1);
556
557 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) {
558 invalid = ~((1 << AR9382_MAX_GPIO_PIN_NUM) - 1);
565 invalid |= 1 << AR9382_GPIO_PIN_8_RESERVED |
566 1 << AR9382_GPIO_PIN_11_RESERVED;
559 invalid |= 1 << AR9382_GPIO_PIN_8_RESERVED;
567 }
568 if (mask & invalid) {
569 ath_hal_printf(ah, "%s: invalid GPIO mask 0x%x\n", __func__, mask);
570 return -1;
571 }
572 AH9300(ah)->ah_gpio_mask = mask;
573 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), mask & pol_map);
574

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561 if (mask & invalid) {
562 ath_hal_printf(ah, "%s: invalid GPIO mask 0x%x\n", __func__, mask);
563 return -1;
564 }
565 AH9300(ah)->ah_gpio_mask = mask;
566 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), mask & pol_map);
567

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