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hwregs.c (80062) hwregs.c (82367)
1
2/*******************************************************************************
3 *
4 * Module Name: hwregs - Read/write access functions for the various ACPI
5 * control and status registers.
1
2/*******************************************************************************
3 *
4 * Module Name: hwregs - Read/write access functions for the various ACPI
5 * control and status registers.
6 * $Revision: 102 $
6 * $Revision: 104 $
7 *
8 ******************************************************************************/
9
10/******************************************************************************
11 *
12 * 1. Copyright Notice
13 *
14 * Some or all of this work - Copyright (c) 1999, 2000, 2001, Intel Corp.

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179{
180 UINT16 GpeLength;
181 UINT16 Index;
182
183
184 FUNCTION_TRACE ("HwClearAcpiStatus");
185
186
7 *
8 ******************************************************************************/
9
10/******************************************************************************
11 *
12 * 1. Copyright Notice
13 *
14 * Some or all of this work - Copyright (c) 1999, 2000, 2001, Intel Corp.

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179{
180 UINT16 GpeLength;
181 UINT16 Index;
182
183
184 FUNCTION_TRACE ("HwClearAcpiStatus");
185
186
187 DEBUG_PRINTP (TRACE_IO, ("About to write %04X to %04X\n",
187 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %04X\n",
188 ALL_FIXED_STS_BITS,
189 (UINT16) ACPI_GET_ADDRESS (AcpiGbl_FADT->XPm1aEvtBlk.Address)));
190
191
192 AcpiUtAcquireMutex (ACPI_MTX_HARDWARE);
193
194 AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK, PM1_STS, ALL_FIXED_STS_BITS);
195

--- 128 unchanged lines hidden (view full) ---

324 *Slp_TypA = (UINT8) (ObjDesc->Package.Elements[0])->Integer.Value;
325
326 *Slp_TypB = (UINT8) (ObjDesc->Package.Elements[1])->Integer.Value;
327 }
328
329
330 if (ACPI_FAILURE (Status))
331 {
188 ALL_FIXED_STS_BITS,
189 (UINT16) ACPI_GET_ADDRESS (AcpiGbl_FADT->XPm1aEvtBlk.Address)));
190
191
192 AcpiUtAcquireMutex (ACPI_MTX_HARDWARE);
193
194 AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK, PM1_STS, ALL_FIXED_STS_BITS);
195

--- 128 unchanged lines hidden (view full) ---

324 *Slp_TypA = (UINT8) (ObjDesc->Package.Elements[0])->Integer.Value;
325
326 *Slp_TypB = (UINT8) (ObjDesc->Package.Elements[1])->Integer.Value;
327 }
328
329
330 if (ACPI_FAILURE (Status))
331 {
332 DEBUG_PRINTP (ACPI_ERROR, ("Bad Sleep object %p type %X\n",
332 ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Bad Sleep object %p type %X\n",
333 ObjDesc, ObjDesc->Common.Type));
334 }
335
336 AcpiUtRemoveReference (ObjDesc);
337
338 return_ACPI_STATUS (Status);
339}
340

--- 193 unchanged lines hidden (view full) ---

534
535 /*
536 * Read the PM1 Control register.
537 * Note that at this level, the fact that there are actually TWO
538 * registers (A and B) and that B may not exist, are abstracted.
539 */
540 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, PM1_CONTROL);
541
333 ObjDesc, ObjDesc->Common.Type));
334 }
335
336 AcpiUtRemoveReference (ObjDesc);
337
338 return_ACPI_STATUS (Status);
339}
340

--- 193 unchanged lines hidden (view full) ---

534
535 /*
536 * Read the PM1 Control register.
537 * Note that at this level, the fact that there are actually TWO
538 * registers (A and B) and that B may not exist, are abstracted.
539 */
540 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, PM1_CONTROL);
541
542 DEBUG_PRINT (TRACE_IO, ("PM1 control: Read %X\n", RegisterValue));
542 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "PM1 control: Read %X\n", RegisterValue));
543
544 if (ReadWrite == ACPI_WRITE)
545 {
546 RegisterValue &= ~Mask;
547 Value <<= AcpiHwGetBitShift (Mask);
548 Value &= Mask;
549 RegisterValue |= Value;
550

--- 23 unchanged lines hidden (view full) ---

574
575 default:
576 Mask = 0;
577 break;
578 }
579
580 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, PM2_CONTROL);
581
543
544 if (ReadWrite == ACPI_WRITE)
545 {
546 RegisterValue &= ~Mask;
547 Value <<= AcpiHwGetBitShift (Mask);
548 Value &= Mask;
549 RegisterValue |= Value;
550

--- 23 unchanged lines hidden (view full) ---

574
575 default:
576 Mask = 0;
577 break;
578 }
579
580 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, PM2_CONTROL);
581
582 DEBUG_PRINT (TRACE_IO, ("PM2 control: Read %X from %p\n",
582 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "PM2 control: Read %X from %p\n",
583 RegisterValue, ACPI_GET_ADDRESS (AcpiGbl_FADT->XPm2CntBlk.Address)));
584
585 if (ReadWrite == ACPI_WRITE)
586 {
587 RegisterValue &= ~Mask;
588 Value <<= AcpiHwGetBitShift (Mask);
589 Value &= Mask;
590 RegisterValue |= Value;
591
583 RegisterValue, ACPI_GET_ADDRESS (AcpiGbl_FADT->XPm2CntBlk.Address)));
584
585 if (ReadWrite == ACPI_WRITE)
586 {
587 RegisterValue &= ~Mask;
588 Value <<= AcpiHwGetBitShift (Mask);
589 Value &= Mask;
590 RegisterValue |= Value;
591
592 DEBUG_PRINT (TRACE_IO, ("About to write %04X to %p\n", RegisterValue,
592 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %p\n", RegisterValue,
593 AcpiGbl_FADT->XPm2CntBlk.Address));
594
595 AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK,
596 PM2_CONTROL, (UINT8) (RegisterValue));
597 }
598 break;
599
600
601 case PM_TIMER:
602
603 Mask = TMR_VAL_MASK;
604 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK,
605 PM_TIMER);
593 AcpiGbl_FADT->XPm2CntBlk.Address));
594
595 AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK,
596 PM2_CONTROL, (UINT8) (RegisterValue));
597 }
598 break;
599
600
601 case PM_TIMER:
602
603 Mask = TMR_VAL_MASK;
604 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK,
605 PM_TIMER);
606 DEBUG_PRINT (TRACE_IO, ("PM_TIMER: Read %X from %p\n",
606 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "PM_TIMER: Read %X from %p\n",
607 RegisterValue, ACPI_GET_ADDRESS (AcpiGbl_FADT->XPmTmrBlk.Address)));
608
609 break;
610
611
612 case GPE1_EN_BLOCK:
613 case GPE1_STS_BLOCK:
614 case GPE0_EN_BLOCK:

--- 25 unchanged lines hidden (view full) ---

640 /*
641 * This sets the bit within EnableBit that needs to be written to
642 * the Register indicated in Mask to a 1, all others are 0
643 */
644
645 /* Now get the current Enable Bits in the selected Reg */
646
647 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, RegisterId);
607 RegisterValue, ACPI_GET_ADDRESS (AcpiGbl_FADT->XPmTmrBlk.Address)));
608
609 break;
610
611
612 case GPE1_EN_BLOCK:
613 case GPE1_STS_BLOCK:
614 case GPE0_EN_BLOCK:

--- 25 unchanged lines hidden (view full) ---

640 /*
641 * This sets the bit within EnableBit that needs to be written to
642 * the Register indicated in Mask to a 1, all others are 0
643 */
644
645 /* Now get the current Enable Bits in the selected Reg */
646
647 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, RegisterId);
648 DEBUG_PRINT (TRACE_IO, ("GPE Enable bits: Read %X from %X\n",
648 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "GPE Enable bits: Read %X from %X\n",
649 RegisterValue, RegisterId));
650
651 if (ReadWrite == ACPI_WRITE)
652 {
653 RegisterValue &= ~Mask;
654 Value <<= AcpiHwGetBitShift (Mask);
655 Value &= Mask;
656 RegisterValue |= Value;
657
658 /* This write will put the Action state into the General Purpose */
659 /* Enable Register indexed by the value in Mask */
660
649 RegisterValue, RegisterId));
650
651 if (ReadWrite == ACPI_WRITE)
652 {
653 RegisterValue &= ~Mask;
654 Value <<= AcpiHwGetBitShift (Mask);
655 Value &= Mask;
656 RegisterValue |= Value;
657
658 /* This write will put the Action state into the General Purpose */
659 /* Enable Register indexed by the value in Mask */
660
661 DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n",
661 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %04X\n",
662 RegisterValue, RegisterId));
663 AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK, RegisterId,
664 (UINT8) RegisterValue);
665 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK,
666 RegisterId);
667 }
668 break;
669

--- 11 unchanged lines hidden (view full) ---

681 if (ACPI_MTX_LOCK == UseLock) {
682 AcpiUtReleaseMutex (ACPI_MTX_HARDWARE);
683 }
684
685
686 RegisterValue &= Mask;
687 RegisterValue >>= AcpiHwGetBitShift (Mask);
688
662 RegisterValue, RegisterId));
663 AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK, RegisterId,
664 (UINT8) RegisterValue);
665 RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK,
666 RegisterId);
667 }
668 break;
669

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681 if (ACPI_MTX_LOCK == UseLock) {
682 AcpiUtReleaseMutex (ACPI_MTX_HARDWARE);
683 }
684
685
686 RegisterValue &= Mask;
687 RegisterValue >>= AcpiHwGetBitShift (Mask);
688
689 DEBUG_PRINT (TRACE_IO, ("Register I/O: returning %X\n", RegisterValue));
689 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "Register I/O: returning %X\n", RegisterValue));
690 return_VALUE (RegisterValue);
691}
692
693
694/******************************************************************************
695 *
696 * FUNCTION: AcpiHwRegisterRead
697 *

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754
755
756 case PM_TIMER: /* 32-bit access */
757
758 Value = AcpiHwLowLevelRead (32, &AcpiGbl_FADT->XPmTmrBlk, 0);
759 break;
760
761
690 return_VALUE (RegisterValue);
691}
692
693
694/******************************************************************************
695 *
696 * FUNCTION: AcpiHwRegisterRead
697 *

--- 56 unchanged lines hidden (view full) ---

754
755
756 case PM_TIMER: /* 32-bit access */
757
758 Value = AcpiHwLowLevelRead (32, &AcpiGbl_FADT->XPmTmrBlk, 0);
759 break;
760
761
762 /*
763 * For the GPE? Blocks, the lower word of RegisterId contains the
764 * byte offset for which to read, as each part of each block may be
765 * several bytes long.
766 */
762 case GPE0_STS_BLOCK: /* 8-bit access */
763
767 case GPE0_STS_BLOCK: /* 8-bit access */
768
764 Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe0Blk, 0);
769 BankOffset = REGISTER_BIT_ID(RegisterId);
770 Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe0Blk, BankOffset);
765 break;
766
771 break;
772
767
768 case GPE0_EN_BLOCK: /* 8-bit access */
769
773 case GPE0_EN_BLOCK: /* 8-bit access */
774
770 BankOffset = DIV_2 (AcpiGbl_FADT->Gpe0BlkLen);
771 Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe0Blk, BankOffset);
775 BankOffset = DIV_2 (AcpiGbl_FADT->Gpe0BlkLen) + REGISTER_BIT_ID(RegisterId);
776 Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe0Blk, BankOffset);
772 break;
773
777 break;
778
774
775 case GPE1_STS_BLOCK: /* 8-bit access */
776
779 case GPE1_STS_BLOCK: /* 8-bit access */
780
777 Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe1Blk, 0);
781 BankOffset = REGISTER_BIT_ID(RegisterId);
782 Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe1Blk, BankOffset);
778 break;
779
783 break;
784
780
781 case GPE1_EN_BLOCK: /* 8-bit access */
782
785 case GPE1_EN_BLOCK: /* 8-bit access */
786
783 BankOffset = DIV_2 (AcpiGbl_FADT->Gpe1BlkLen);
784 Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe1Blk, BankOffset);
787 BankOffset = DIV_2 (AcpiGbl_FADT->Gpe1BlkLen) + REGISTER_BIT_ID(RegisterId);
788 Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe1Blk, BankOffset);
785 break;
786
789 break;
790
787
788 case SMI_CMD_BLOCK: /* 8bit */
789
790 AcpiOsReadPort (AcpiGbl_FADT->SmiCmd, &Value, 8);
791 break;
792
791 case SMI_CMD_BLOCK: /* 8bit */
792
793 AcpiOsReadPort (AcpiGbl_FADT->SmiCmd, &Value, 8);
794 break;
795
793
794 default:
795 /* Value will be returned as 0 */
796 break;
797 }
798
799
800 if (ACPI_MTX_LOCK == UseLock)
801 {

--- 80 unchanged lines hidden (view full) ---

882 case PM_TIMER: /* 32-bit access */
883
884 AcpiHwLowLevelWrite (32, Value, &AcpiGbl_FADT->XPmTmrBlk, 0);
885 break;
886
887
888 case GPE0_STS_BLOCK: /* 8-bit access */
889
796 default:
797 /* Value will be returned as 0 */
798 break;
799 }
800
801
802 if (ACPI_MTX_LOCK == UseLock)
803 {

--- 80 unchanged lines hidden (view full) ---

884 case PM_TIMER: /* 32-bit access */
885
886 AcpiHwLowLevelWrite (32, Value, &AcpiGbl_FADT->XPmTmrBlk, 0);
887 break;
888
889
890 case GPE0_STS_BLOCK: /* 8-bit access */
891
890 AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe0Blk, 0);
892 BankOffset = REGISTER_BIT_ID(RegisterId);
893 AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe0Blk, BankOffset);
891 break;
892
893
894 case GPE0_EN_BLOCK: /* 8-bit access */
895
894 break;
895
896
897 case GPE0_EN_BLOCK: /* 8-bit access */
898
896 BankOffset = DIV_2 (AcpiGbl_FADT->Gpe0BlkLen);
899 BankOffset = DIV_2 (AcpiGbl_FADT->Gpe0BlkLen) + REGISTER_BIT_ID(RegisterId);
897 AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe0Blk, BankOffset);
898 break;
899
900
901 case GPE1_STS_BLOCK: /* 8-bit access */
902
900 AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe0Blk, BankOffset);
901 break;
902
903
904 case GPE1_STS_BLOCK: /* 8-bit access */
905
903 AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe1Blk, 0);
906 BankOffset = REGISTER_BIT_ID(RegisterId);
907 AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe1Blk, BankOffset);
904 break;
905
906
907 case GPE1_EN_BLOCK: /* 8-bit access */
908
908 break;
909
910
911 case GPE1_EN_BLOCK: /* 8-bit access */
912
909 BankOffset = DIV_2 (AcpiGbl_FADT->Gpe1BlkLen);
913 BankOffset = DIV_2 (AcpiGbl_FADT->Gpe1BlkLen) + REGISTER_BIT_ID(RegisterId);
910 AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe1Blk, BankOffset);
911 break;
912
913
914 case SMI_CMD_BLOCK: /* 8bit */
915
916 /* For 2.0, SMI_CMD is always in IO space */
917 /* TBD: what about 1.0? 0.71? */

--- 172 unchanged lines hidden --- 		914 AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe1Blk, BankOffset);
915 break;
916
917
918 case SMI_CMD_BLOCK: /* 8bit */
919
920 /* For 2.0, SMI_CMD is always in IO space */
921 /* TBD: what about 1.0? 0.71? */

--- 172 unchanged lines hidden ---