| socfpga.dtsi (271186) | socfpga.dtsi (271431) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * | 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 271186 2014-09-06 08:48:57Z br $ | 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 271431 2014-09-11 18:12:28Z br $ |
| 31 */ 32 33/ { 34 compatible = "altr,socfpga"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 interrupt-parent = <&GIC>; 39 40 aliases { 41 soc = &SOC; | 31 */ 32 33/ { 34 compatible = "altr,socfpga"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 interrupt-parent = <&GIC>; 39 40 aliases { 41 soc = &SOC; |
| 42 rstmgr = &rstmgr; 43 l3regs = &l3regs; |
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| 42 serial0 = &serial0; 43 serial1 = &serial1; 44 }; 45 46 SOC: socfpga { 47 #address-cells = <1>; 48 #size-cells = <1>; 49 compatible = "simple-bus"; --- 14 unchanged lines hidden (view full) --- 64 #address-cells = <1>; 65 #size-cells = <0>; 66 reg = < 0xfffec200 0x100 >, /* Global Timer */ 67 < 0xfffec600 0x100 >; /* Private Timer */ 68 interrupts = < 27 29 >; 69 interrupt-parent = < &GIC >; 70 }; 71 | 44 serial0 = &serial0; 45 serial1 = &serial1; 46 }; 47 48 SOC: socfpga { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 compatible = "simple-bus"; --- 14 unchanged lines hidden (view full) --- 66 #address-cells = <1>; 67 #size-cells = <0>; 68 reg = < 0xfffec200 0x100 >, /* Global Timer */ 69 < 0xfffec600 0x100 >; /* Private Timer */ 70 interrupts = < 27 29 >; 71 interrupt-parent = < &GIC >; 72 }; 73 |
| 74 rstmgr: rstmgr@ffd05000 { 75 compatible = "altr,rst-mgr"; 76 reg = <0xffd05000 0x1000>; 77 }; 78 79 l3regs: l3regs@ff800000 { 80 compatible = "altr,l3regs"; 81 reg = <0xff800000 0x1000>; 82 }; 83 |
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| 72 fpgamgr: fpgamgr@ff706000 { 73 compatible = "altr,fpga-mgr"; 74 reg = <0xff706000 0x1000>, /* FPGAMGRREGS */ 75 <0xffb90000 0x1000>; /* FPGAMGRDATA */ 76 interrupts = < 207 >; 77 interrupt-parent = <&GIC>; 78 }; 79 --- 40 unchanged lines hidden --- | 84 fpgamgr: fpgamgr@ff706000 { 85 compatible = "altr,fpga-mgr"; 86 reg = <0xff706000 0x1000>, /* FPGAMGRREGS */ 87 <0xffb90000 0x1000>; /* FPGAMGRDATA */ 88 interrupts = < 207 >; 89 interrupt-parent = <&GIC>; 90 }; 91 --- 40 unchanged lines hidden --- |