| socfpga.dtsi (271093) | socfpga.dtsi (271186) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * | 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 271093 2014-09-04 12:44:40Z br $ | 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 271186 2014-09-06 08:48:57Z br $ |
| 31 */ 32 33/ { 34 compatible = "altr,socfpga"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 interrupt-parent = <&GIC>; --- 25 unchanged lines hidden (view full) --- 64 #address-cells = <1>; 65 #size-cells = <0>; 66 reg = < 0xfffec200 0x100 >, /* Global Timer */ 67 < 0xfffec600 0x100 >; /* Private Timer */ 68 interrupts = < 27 29 >; 69 interrupt-parent = < &GIC >; 70 }; 71 | 31 */ 32 33/ { 34 compatible = "altr,socfpga"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 interrupt-parent = <&GIC>; --- 25 unchanged lines hidden (view full) --- 64 #address-cells = <1>; 65 #size-cells = <0>; 66 reg = < 0xfffec200 0x100 >, /* Global Timer */ 67 < 0xfffec600 0x100 >; /* Private Timer */ 68 interrupts = < 27 29 >; 69 interrupt-parent = < &GIC >; 70 }; 71 |
| 72 fpgamgr: fpgamgr@ff706000 { 73 compatible = "altr,fpga-mgr"; 74 reg = <0xff706000 0x1000>, /* FPGAMGRREGS */ 75 <0xffb90000 0x1000>; /* FPGAMGRDATA */ 76 interrupts = < 207 >; 77 interrupt-parent = <&GIC>; 78 }; 79 |
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| 72 serial0: serial@ffc02000 { 73 compatible = "ns16550"; 74 reg = <0xffc02000 0x1000>; 75 reg-shift = <2>; 76 interrupts = <194>; 77 interrupt-parent = <&GIC>; 78 current-speed = <115200>; 79 clock-frequency = < 100000000 >; --- 32 unchanged lines hidden --- | 80 serial0: serial@ffc02000 { 81 compatible = "ns16550"; 82 reg = <0xffc02000 0x1000>; 83 reg-shift = <2>; 84 interrupts = <194>; 85 interrupt-parent = <&GIC>; 86 current-speed = <115200>; 87 clock-frequency = < 100000000 >; --- 32 unchanged lines hidden --- |