1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
| 1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
|
30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 272120 2014-09-25 18:03:14Z br $
| 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 272712 2014-10-07 17:39:30Z br $
|
31 */
32
33/ {
34 compatible = "altr,socfpga";
35 #address-cells = <1>;
36 #size-cells = <1>;
37
38 interrupt-parent = <&GIC>;
39
40 aliases {
41 soc = &SOC;
42 rstmgr = &rstmgr;
43 l3regs = &l3regs;
44 serial0 = &serial0;
45 serial1 = &serial1;
46 };
47
48 SOC: socfpga {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "simple-bus";
52 ranges;
53 bus-frequency = <0>;
54
55 GIC: interrupt-controller@fffed000 {
56 compatible = "arm,gic";
57 reg = < 0xfffed000 0x1000 >, /* Distributor */
58 < 0xfffec100 0x100 >; /* CPU Interface */
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 };
62
63 mp_tmr@40002100 {
64 compatible = "arm,mpcore-timers";
65 clock-frequency = <200000000>;
66 #address-cells = <1>;
67 #size-cells = <0>;
68 reg = < 0xfffec200 0x100 >, /* Global Timer */
69 < 0xfffec600 0x100 >; /* Private Timer */
70 interrupts = < 27 29 >;
71 interrupt-parent = < &GIC >;
72 };
73
74 sysmgr: sysmgr@ffd08000 {
75 compatible = "altr,sys-mgr";
76 reg = <0xffd08000 0x1000>;
77 };
78
79 rstmgr: rstmgr@ffd05000 {
80 compatible = "altr,rst-mgr";
81 reg = <0xffd05000 0x1000>;
82 };
83
84 l3regs: l3regs@ff800000 {
85 compatible = "altr,l3regs";
86 reg = <0xff800000 0x1000>;
87 };
88
89 fpgamgr: fpgamgr@ff706000 {
90 compatible = "altr,fpga-mgr";
91 reg = <0xff706000 0x1000>, /* FPGAMGRREGS */
92 <0xffb90000 0x1000>; /* FPGAMGRDATA */
93 interrupts = < 207 >;
94 interrupt-parent = <&GIC>;
95 };
96
97 serial0: serial@ffc02000 {
98 compatible = "ns16550";
99 reg = <0xffc02000 0x1000>;
100 reg-shift = <2>;
101 interrupts = <194>;
102 interrupt-parent = <&GIC>;
103 current-speed = <115200>;
104 clock-frequency = < 100000000 >;
105 status = "disabled";
106 };
107
108 serial1: serial@ffc03000 {
109 compatible = "ns16550";
110 reg = <0xffc03000 0x1000>;
111 reg-shift = <2>;
112 interrupts = <195>;
113 interrupt-parent = <&GIC>;
114 current-speed = <115200>;
115 clock-frequency = < 100000000 >;
116 status = "disabled";
117 };
118
119 usb0: usb@ffb00000 {
120 compatible = "synopsys,designware-hs-otg2";
121 reg = <0xffb00000 0xffff>;
122 interrupts = <157>;
123 interrupt-parent = <&GIC>;
124 status = "disabled";
125 };
126
127 usb1: usb@ffb40000 {
128 compatible = "synopsys,designware-hs-otg2";
129 reg = <0xffb40000 0xffff>;
130 interrupts = <160>;
131 interrupt-parent = <&GIC>;
132 dr_mode = "host";
133 status = "disabled";
134 };
135
136 gmac0: ethernet@ff700000 {
137 compatible = "altr,socfpga-stmmac",
138 "snps,dwmac-3.70a", "snps,dwmac";
139 reg = <0xff700000 0x2000>;
140 interrupts = <147>;
141 interrupt-parent = <&GIC>;
142 phy-mode = "rgmii";
143 status = "disabled";
144 };
145
146 gmac1: ethernet@ff702000 {
147 compatible = "altr,socfpga-stmmac",
148 "snps,dwmac-3.70a", "snps,dwmac";
149 reg = <0xff702000 0x2000>;
150 interrupts = <152>;
151 interrupt-parent = <&GIC>;
152 phy-mode = "rgmii";
153 status = "disabled";
154 };
| 31 */
32
33/ {
34 compatible = "altr,socfpga";
35 #address-cells = <1>;
36 #size-cells = <1>;
37
38 interrupt-parent = <&GIC>;
39
40 aliases {
41 soc = &SOC;
42 rstmgr = &rstmgr;
43 l3regs = &l3regs;
44 serial0 = &serial0;
45 serial1 = &serial1;
46 };
47
48 SOC: socfpga {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "simple-bus";
52 ranges;
53 bus-frequency = <0>;
54
55 GIC: interrupt-controller@fffed000 {
56 compatible = "arm,gic";
57 reg = < 0xfffed000 0x1000 >, /* Distributor */
58 < 0xfffec100 0x100 >; /* CPU Interface */
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 };
62
63 mp_tmr@40002100 {
64 compatible = "arm,mpcore-timers";
65 clock-frequency = <200000000>;
66 #address-cells = <1>;
67 #size-cells = <0>;
68 reg = < 0xfffec200 0x100 >, /* Global Timer */
69 < 0xfffec600 0x100 >; /* Private Timer */
70 interrupts = < 27 29 >;
71 interrupt-parent = < &GIC >;
72 };
73
74 sysmgr: sysmgr@ffd08000 {
75 compatible = "altr,sys-mgr";
76 reg = <0xffd08000 0x1000>;
77 };
78
79 rstmgr: rstmgr@ffd05000 {
80 compatible = "altr,rst-mgr";
81 reg = <0xffd05000 0x1000>;
82 };
83
84 l3regs: l3regs@ff800000 {
85 compatible = "altr,l3regs";
86 reg = <0xff800000 0x1000>;
87 };
88
89 fpgamgr: fpgamgr@ff706000 {
90 compatible = "altr,fpga-mgr";
91 reg = <0xff706000 0x1000>, /* FPGAMGRREGS */
92 <0xffb90000 0x1000>; /* FPGAMGRDATA */
93 interrupts = < 207 >;
94 interrupt-parent = <&GIC>;
95 };
96
97 serial0: serial@ffc02000 {
98 compatible = "ns16550";
99 reg = <0xffc02000 0x1000>;
100 reg-shift = <2>;
101 interrupts = <194>;
102 interrupt-parent = <&GIC>;
103 current-speed = <115200>;
104 clock-frequency = < 100000000 >;
105 status = "disabled";
106 };
107
108 serial1: serial@ffc03000 {
109 compatible = "ns16550";
110 reg = <0xffc03000 0x1000>;
111 reg-shift = <2>;
112 interrupts = <195>;
113 interrupt-parent = <&GIC>;
114 current-speed = <115200>;
115 clock-frequency = < 100000000 >;
116 status = "disabled";
117 };
118
119 usb0: usb@ffb00000 {
120 compatible = "synopsys,designware-hs-otg2";
121 reg = <0xffb00000 0xffff>;
122 interrupts = <157>;
123 interrupt-parent = <&GIC>;
124 status = "disabled";
125 };
126
127 usb1: usb@ffb40000 {
128 compatible = "synopsys,designware-hs-otg2";
129 reg = <0xffb40000 0xffff>;
130 interrupts = <160>;
131 interrupt-parent = <&GIC>;
132 dr_mode = "host";
133 status = "disabled";
134 };
135
136 gmac0: ethernet@ff700000 {
137 compatible = "altr,socfpga-stmmac",
138 "snps,dwmac-3.70a", "snps,dwmac";
139 reg = <0xff700000 0x2000>;
140 interrupts = <147>;
141 interrupt-parent = <&GIC>;
142 phy-mode = "rgmii";
143 status = "disabled";
144 };
145
146 gmac1: ethernet@ff702000 {
147 compatible = "altr,socfpga-stmmac",
148 "snps,dwmac-3.70a", "snps,dwmac";
149 reg = <0xff702000 0x2000>;
150 interrupts = <152>;
151 interrupt-parent = <&GIC>;
152 phy-mode = "rgmii";
153 status = "disabled";
154 };
|
| 155
156 mmc: dwmmc@ff704000 {
157 compatible = "altr,socfpga-dw-mshc";
158 reg = <0xff704000 0x1000>;
159 interrupts = <171>;
160 interrupt-parent = <&GIC>;
161 fifo-depth = <0x400>;
162 status = "disabled";
163 };
|
155 };
156};
| 164 };
165};
|