| socfpga-sockit.dts (272712) | socfpga-sockit.dts (272896) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * | 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga-sockit.dts 272712 2014-10-07 17:39:30Z br $ | 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga-sockit.dts 272896 2014-10-10 14:35:51Z br $ |
| 31 */ 32 33/dts-v1/; 34 35/include/ "socfpga.dtsi" 36 37/ { 38 model = "Terasic SoCKit"; 39 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 40 | 31 */ 32 33/dts-v1/; 34 35/include/ "socfpga.dtsi" 36 37/ { 38 model = "Terasic SoCKit"; 39 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 40 |
| 41 /* Reserve first page for secondary CPU trampoline code */ 42 memreserve = < 0x00000000 0x1000 >; 43 |
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| 41 memory { 42 device_type = "memory"; 43 reg = < 0x00000000 0x40000000 >; /* 1G RAM */ 44 }; 45 46 SOC: socfpga { 47 serial0: serial@ffc02000 { 48 status = "okay"; --- 30 unchanged lines hidden --- | 44 memory { 45 device_type = "memory"; 46 reg = < 0x00000000 0x40000000 >; /* 1G RAM */ 47 }; 48 49 SOC: socfpga { 50 serial0: serial@ffc02000 { 51 status = "okay"; --- 30 unchanged lines hidden --- |