| armada-385.dtsi (294416) | armada-385.dtsi (294432) |
|---|---|
| 1/* 2 * Device Tree Include file for Marvell Armada 385 SoC. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- 31 unchanged lines hidden (view full) --- 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 * | 1/* 2 * Device Tree Include file for Marvell Armada 385 SoC. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- 31 unchanged lines hidden (view full) --- 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 * |
| 48 * $FreeBSD: head/sys/boot/fdt/dts/arm/armada-385.dtsi 294416 2016-01-20 13:14:36Z zbb $ | 48 * $FreeBSD: head/sys/boot/fdt/dts/arm/armada-385.dtsi 294432 2016-01-20 14:14:30Z zbb $ |
| 49 */ 50 51#include "armada-38x.dtsi" 52 53/ { 54 model = "Marvell Armada 385 family SoC"; 55 compatible = "marvell,armada385", "marvell,armada380"; 56 --- 15 unchanged lines hidden (view full) --- 72 }; 73 74 soc { 75 internal-regs { 76 pinctrl@18000 { 77 compatible = "marvell,mv88f6820-pinctrl"; 78 }; 79 }; | 49 */ 50 51#include "armada-38x.dtsi" 52 53/ { 54 model = "Marvell Armada 385 family SoC"; 55 compatible = "marvell,armada385", "marvell,armada380"; 56 --- 15 unchanged lines hidden (view full) --- 72 }; 73 74 soc { 75 internal-regs { 76 pinctrl@18000 { 77 compatible = "marvell,mv88f6820-pinctrl"; 78 }; 79 }; |
| 80 81 pcie-controller { 82 compatible = "marvell,armada-370-pcie"; 83 status = "disabled"; 84 device_type = "pci"; 85 86 #address-cells = <3>; 87 #size-cells = <2>; 88 89 msi-parent = <&mpic>; 90 bus-range = <0x00 0xff>; 91 92 ranges = 93 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 94 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 95 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 96 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 97 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 98 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 99 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 100 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 101 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 102 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ 103 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ 104 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; 105 106 /* 107 * This port can be either x4 or x1. When 108 * configured in x4 by the bootloader, then 109 * pcie@4,0 is not available. 110 */ 111 pcie@1,0 { 112 device_type = "pci"; 113 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 114 reg = <0x0800 0 0 0 0>; 115 #address-cells = <3>; 116 #size-cells = <2>; 117 #interrupt-cells = <1>; 118 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 119 0x81000000 0 0 0x81000000 0x1 0 1 0>; 120 interrupt-map-mask = <0 0 0 0>; 121 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 122 marvell,pcie-port = <0>; 123 marvell,pcie-lane = <0>; 124 clocks = <&gateclk 8>; 125 status = "disabled"; 126 }; 127 128 /* x1 port */ 129 pcie@2,0 { 130 device_type = "pci"; 131 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 132 reg = <0x1000 0 0 0 0>; 133 #address-cells = <3>; 134 #size-cells = <2>; 135 #interrupt-cells = <1>; 136 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 137 0x81000000 0 0 0x81000000 0x2 0 1 0>; 138 interrupt-map-mask = <0 0 0 0>; 139 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 140 marvell,pcie-port = <1>; 141 marvell,pcie-lane = <0>; 142 clocks = <&gateclk 5>; 143 status = "disabled"; 144 }; 145 146 /* x1 port */ 147 pcie@3,0 { 148 device_type = "pci"; 149 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 150 reg = <0x1800 0 0 0 0>; 151 #address-cells = <3>; 152 #size-cells = <2>; 153 #interrupt-cells = <1>; 154 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 155 0x81000000 0 0 0x81000000 0x3 0 1 0>; 156 interrupt-map-mask = <0 0 0 0>; 157 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 158 marvell,pcie-port = <2>; 159 marvell,pcie-lane = <0>; 160 clocks = <&gateclk 6>; 161 status = "disabled"; 162 }; 163 164 /* 165 * x1 port only available when pcie@1,0 is 166 * configured as a x1 port 167 */ 168 pcie@4,0 { 169 device_type = "pci"; 170 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 171 reg = <0x2000 0 0 0 0>; 172 #address-cells = <3>; 173 #size-cells = <2>; 174 #interrupt-cells = <1>; 175 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 176 0x81000000 0 0 0x81000000 0x4 0 1 0>; 177 interrupt-map-mask = <0 0 0 0>; 178 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 179 marvell,pcie-port = <3>; 180 marvell,pcie-lane = <0>; 181 clocks = <&gateclk 7>; 182 status = "disabled"; 183 }; 184 }; | |
| 185 }; 186}; | 80 }; 81}; |