| armreg.h (289581) | armreg.h (292954) |
|---|---|
| 1/*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * | 1/*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/arm64/include/armreg.h 289581 2015-10-19 13:20:23Z andrew $ | 30 * $FreeBSD: head/sys/arm64/include/armreg.h 292954 2015-12-30 17:36:34Z andrew $ |
| 31 */ 32 33#ifndef _MACHINE_ARMREG_H_ 34#define _MACHINE_ARMREG_H_ 35 36#define READ_SPECIALREG(reg) \ 37({ uint64_t val; \ 38 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ --- 77 unchanged lines hidden (view full) --- 116#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 117 118/* ICC_SRE_EL1 */ 119#define ICC_SRE_EL1_SRE (1U << 0) 120 121/* ICC_SRE_EL2 */ 122#define ICC_SRE_EL2_EN (1U << 3) 123 | 31 */ 32 33#ifndef _MACHINE_ARMREG_H_ 34#define _MACHINE_ARMREG_H_ 35 36#define READ_SPECIALREG(reg) \ 37({ uint64_t val; \ 38 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ --- 77 unchanged lines hidden (view full) --- 116#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 117 118/* ICC_SRE_EL1 */ 119#define ICC_SRE_EL1_SRE (1U << 0) 120 121/* ICC_SRE_EL2 */ 122#define ICC_SRE_EL2_EN (1U << 3) 123 |
| 124/* ID_AA64DFR0_EL1 */ 125#define ID_AA64DFR0_MASK 0xf0f0ffff 126#define ID_AA64DFR0_DEBUG_VER_SHIFT 0 127#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) 128#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 129#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) 130#define ID_AA64DFR0_TRACE_VER_SHIFT 4 131#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) 132#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 133#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) 134#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) 135#define ID_AA64DFR0_PMU_VER_SHIFT 8 136#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 137#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 138#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) 139#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) 140#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 141#define ID_AA64DFR0_BRPS_SHIFT 12 142#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) 143#define ID_AA64DFR0_BRPS(x) \ 144 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 145#define ID_AA64DFR0_WRPS_SHIFT 20 146#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) 147#define ID_AA64DFR0_WRPS(x) \ 148 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 149#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 150#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) 151#define ID_AA64DFR0_CTX_CMPS(x) \ 152 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 153 154/* ID_AA64ISAR0_EL1 */ 155#define ID_AA64ISAR0_MASK 0x000ffff0 156#define ID_AA64ISAR0_AES_SHIFT 4 157#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) 158#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 159#define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) 160#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) 161#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) 162#define ID_AA64ISAR0_SHA1_SHIFT 8 163#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) 164#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 165#define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) 166#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) 167#define ID_AA64ISAR0_SHA2_SHIFT 12 168#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) 169#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 170#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) 171#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) 172#define ID_AA64ISAR0_CRC32_SHIFT 16 173#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) 174#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 175#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) 176#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) 177 178/* ID_AA64MMFR0_EL1 */ 179#define ID_AA64MMFR0_MASK 0xffffffff 180#define ID_AA64MMFR0_PA_RANGE_SHIFT 0 181#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) 182#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 183#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) 184#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) 185#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) 186#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) 187#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) 188#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) 189#define ID_AA64MMFR0_ASID_BITS_SHIFT 4 190#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) 191#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 192#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) 193#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) 194#define ID_AA64MMFR0_BIGEND_SHIFT 8 195#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) 196#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 197#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) 198#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) 199#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 200#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) 201#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 202#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 203#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 204#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 205#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 206#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 207#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 208#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 209#define ID_AA64MMFR0_TGRAN16_SHIFT 20 210#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) 211#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 212#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) 213#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) 214#define ID_AA64MMFR0_TGRAN64_SHIFT 24 215#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 216#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 217#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) 218#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 219#define ID_AA64MMFR0_TGRAN4_SHIFT 28 220#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 221#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 222#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) 223#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 224 |
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| 124/* ID_AA64PFR0_EL1 */ | 225/* ID_AA64PFR0_EL1 */ |
| 125#define ID_AA64PFR0_EL0_MASK (0xf << 0) 126#define ID_AA64PFR0_EL1_MASK (0xf << 4) 127#define ID_AA64PFR0_EL2_MASK (0xf << 8) 128#define ID_AA64PFR0_EL3_MASK (0xf << 12) 129#define ID_AA64PFR0_FP_MASK (0xf << 16) 130#define ID_AA64PFR0_FP_IMPL (0x0 << 16) /* Floating-point implemented */ 131#define ID_AA64PFR0_FP_NONE (0xf << 16) /* Floating-point not implemented */ 132#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << 20) 133#define ID_AA64PFR0_GIC_SHIFT (24) 134#define ID_AA64PFR0_GIC_BITS (0x4) /* Number of bits in GIC field */ 135#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 136#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) | 226#define ID_AA64PFR0_MASK 0x0fffffff 227#define ID_AA64PFR0_EL0_SHIFT 0 228#define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) 229#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 230#define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) 231#define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) 232#define ID_AA64PFR0_EL1_SHIFT 4 233#define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) 234#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 235#define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) 236#define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) 237#define ID_AA64PFR0_EL2_SHIFT 8 238#define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) 239#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 240#define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) 241#define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) 242#define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) 243#define ID_AA64PFR0_EL3_SHIFT 12 244#define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) 245#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 246#define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) 247#define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) 248#define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) 249#define ID_AA64PFR0_FP_SHIFT 16 250#define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) 251#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 252#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) 253#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) 254#define ID_AA64PFR0_ADV_SIMD_SHIFT 20 255#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 256#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 257#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) 258#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 259#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 260#define ID_AA64PFR0_GIC_SHIFT 24 261#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 262#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 263#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) 264#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) |
| 137 138/* MAIR_EL1 - Memory Attribute Indirection Register */ 139#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 140#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 141 142/* SCTLR_EL1 - System Control Register */ 143#define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */ 144#define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */ --- 120 unchanged lines hidden --- | 265 266/* MAIR_EL1 - Memory Attribute Indirection Register */ 267#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 268#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 269 270/* SCTLR_EL1 - System Control Register */ 271#define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */ 272#define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */ --- 120 unchanged lines hidden --- |