| ixp425_npereg.h (194322) | ixp425_npereg.h (236987) |
|---|---|
| 1/*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 12 unchanged lines hidden (view full) --- 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * | 1/*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 12 unchanged lines hidden (view full) --- 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * |
| 29 * $FreeBSD: head/sys/arm/xscale/ixp425/ixp425_npereg.h 194322 2009-06-17 02:55:53Z sam $ | 29 * $FreeBSD: head/sys/arm/xscale/ixp425/ixp425_npereg.h 236987 2012-06-13 04:38:09Z imp $ |
| 30 */ 31 32/*- 33 * Copyright (c) 2001-2005, Intel Corporation. 34 * All rights reserved. | 30 */ 31 32/*- 33 * Copyright (c) 2001-2005, Intel Corporation. 34 * All rights reserved. |
| 35 * | 35 * |
| 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the Intel Corporation nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. | 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the Intel Corporation nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. |
| 47 * 48 * | 47 * 48 * |
| 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 50 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT --- 31 unchanged lines hidden (view full) --- 88#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \ 89 (((imageId) >> 16) & 0xff) 90#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \ 91 (((imageId) >> 8) & 0xff) 92#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \ 93 (((imageId) >> 0) & 0xff) 94 95/* | 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 50 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT --- 31 unchanged lines hidden (view full) --- 88#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \ 89 (((imageId) >> 16) & 0xff) 90#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \ 91 (((imageId) >> 8) & 0xff) 92#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \ 93 (((imageId) >> 0) & 0xff) 94 95/* |
| 96 * Instruction and Data Memory Size (in words) for each NPE | 96 * Instruction and Data Memory Size (in words) for each NPE |
| 97 */ 98#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096 99#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048 100#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048 101 102#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048 103#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048 104#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048 --- 25 unchanged lines hidden (view full) --- 130 */ 131#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0 132 133#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 /* VALID bit */ 134#define IX_NPEDL_MASK_STAT_OFNE 0x00010000 /* OFNE bit */ 135#define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */ 136 137/* | 97 */ 98#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096 99#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048 100#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048 101 102#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048 103#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048 104#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048 --- 25 unchanged lines hidden (view full) --- 130 */ 131#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0 132 133#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 /* VALID bit */ 134#define IX_NPEDL_MASK_STAT_OFNE 0x00010000 /* OFNE bit */ 135#define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */ 136 137/* |
| 138 * EXCTL (Execution Control) Register commands | 138 * EXCTL (Execution Control) Register commands |
| 139*/ 140#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */ 141#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */ 142#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 /* Stop execution */ 143#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 /* Clear ins pipeline */ 144 145/* 146 * Read/write operations use address in EXAD and data in EXDATA. --- 12 unchanged lines hidden (view full) --- 159 * EXCTL (Execution Control) Register status bit masks 160 */ 161#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000 162#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000 163#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000 164#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */ 165 166/* | 139*/ 140#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */ 141#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */ 142#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 /* Stop execution */ 143#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 /* Clear ins pipeline */ 144 145/* 146 * Read/write operations use address in EXAD and data in EXDATA. --- 12 unchanged lines hidden (view full) --- 159 * EXCTL (Execution Control) Register status bit masks 160 */ 161#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000 162#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000 163#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000 164#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */ 165 166/* |
| 167 * Executing Context Stack (ECS) level registers | 167 * Executing Context Stack (ECS) level registers |
| 168 */ 169#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */ 170#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */ 171#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 /* reg 2 @ bg ctx */ 172 173#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 /* reg 0 @ pri 1 ctx */ 174#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 /* reg 1 @ pri 1 ctx */ 175#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 /* reg 2 @ pri 1 ctx */ --- 39 unchanged lines hidden (view full) --- 215#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 /* IF bit */ 216#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 /* IE bit */ 217 218 219/* 220 * Bit-Offsets from LSB of particular bit-fields in Execution Access registers. 221 */ 222 | 168 */ 169#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */ 170#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */ 171#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 /* reg 2 @ bg ctx */ 172 173#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 /* reg 0 @ pri 1 ctx */ 174#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 /* reg 1 @ pri 1 ctx */ 175#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 /* reg 2 @ pri 1 ctx */ --- 39 unchanged lines hidden (view full) --- 215#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 /* IF bit */ 216#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 /* IE bit */ 217 218 219/* 220 * Bit-Offsets from LSB of particular bit-fields in Execution Access registers. 221 */ 222 |
| 223#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16 | 223#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16 |
| 224#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8 225 226#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16 227#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0 228 229/* | 224#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8 225 226#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16 227#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0 228 229/* |
| 230 * NPE core & co-processor instruction templates to load into NPE Instruction | 230 * NPE core & co-processor instruction templates to load into NPE Instruction |
| 231 * Register, for read/write of NPE register file registers. 232 */ 233 234/* 235 * Read an 8-bit NPE internal logical register 236 * and return the value in the EXDATA register (aligned to MSB). 237 * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" 238 */ --- 24 unchanged lines hidden (view full) --- 263 * NPE Assembler instruction: "mov16 d0, #0" 264 */ 265#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000 266 267/* 268 * Write a 16-bit NPE internal logical register. 269 * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" 270 */ | 231 * Register, for read/write of NPE register file registers. 232 */ 233 234/* 235 * Read an 8-bit NPE internal logical register 236 * and return the value in the EXDATA register (aligned to MSB). 237 * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" 238 */ --- 24 unchanged lines hidden (view full) --- 263 * NPE Assembler instruction: "mov16 d0, #0" 264 */ 265#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000 266 267/* 268 * Write a 16-bit NPE internal logical register. 269 * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" 270 */ |
| 271#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220 | 271#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220 |
| 272 273/* 274 * Reset Mailbox (MBST) register 275 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" 276 */ 277#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210 278 279 --- 7 unchanged lines hidden (view full) --- 287/* 288 * Masks used to read/write particular bits of an NPE Instruction 289 */ 290 291/** 292 * Mask the bits of 16-bit data value (least-sig 5 bits) to be used in 293 * SRC field of immediate-mode NPE instruction 294 */ | 272 273/* 274 * Reset Mailbox (MBST) register 275 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" 276 */ 277#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210 278 279 --- 7 unchanged lines hidden (view full) --- 287/* 288 * Masks used to read/write particular bits of an NPE Instruction 289 */ 290 291/** 292 * Mask the bits of 16-bit data value (least-sig 5 bits) to be used in 293 * SRC field of immediate-mode NPE instruction 294 */ |
| 295#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F | 295#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F |
| 296 297/** 298 * Mask the bits of 16-bit data value (most-sig 11 bits) to be used in 299 * COPROC field of immediate-mode NPE instruction 300 */ 301#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0 302 303/** --- 124 unchanged lines hidden --- | 296 297/** 298 * Mask the bits of 16-bit data value (most-sig 11 bits) to be used in 299 * COPROC field of immediate-mode NPE instruction 300 */ 301#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0 302 303/** --- 124 unchanged lines hidden --- |