1/*-
2 * Copyright (c) 2010, Andrew Thompson <thompsa@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/*
29 * GPIO driver for Gateworks Cambria
30 *
31 * Note:
32 * The Cambria PLD does not set the i2c ack bit after each write, if we used the
33 * regular iicbus interface it would abort the xfer after the address byte
34 * times out and not write our latch. To get around this we grab the iicbus and
35 * then do our own bit banging. This is a comprimise to changing all the iicbb
36 * device methods to allow a flag to be passed down and is similir to how Linux
37 * does it.
38 *
39 */
40
41#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2010, Andrew Thompson <thompsa@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/*
29 * GPIO driver for Gateworks Cambria
30 *
31 * Note:
32 * The Cambria PLD does not set the i2c ack bit after each write, if we used the
33 * regular iicbus interface it would abort the xfer after the address byte
34 * times out and not write our latch. To get around this we grab the iicbus and
35 * then do our own bit banging. This is a comprimise to changing all the iicbb
36 * device methods to allow a flag to be passed down and is similir to how Linux
37 * does it.
38 *
39 */
40
41#include <sys/cdefs.h>
|
42__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/cambria_gpio.c 277882 2015-01-29 18:08:50Z loos $");
| 42__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/cambria_gpio.c 277996 2015-01-31 19:32:14Z loos $");
|
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/bus.h>
47
48#include <sys/kernel.h>
49#include <sys/module.h>
50#include <sys/rman.h>
51#include <sys/lock.h>
52#include <sys/mutex.h>
53#include <sys/gpio.h>
54
55#include <arm/xscale/ixp425/ixp425reg.h>
56#include <arm/xscale/ixp425/ixp425var.h>
57#include <arm/xscale/ixp425/ixdp425reg.h>
58
| 43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/bus.h>
47
48#include <sys/kernel.h>
49#include <sys/module.h>
50#include <sys/rman.h>
51#include <sys/lock.h>
52#include <sys/mutex.h>
53#include <sys/gpio.h>
54
55#include <arm/xscale/ixp425/ixp425reg.h>
56#include <arm/xscale/ixp425/ixp425var.h>
57#include <arm/xscale/ixp425/ixdp425reg.h>
58
|
| 59#include <dev/gpio/gpiobusvar.h>
|
59#include <dev/iicbus/iiconf.h>
60#include <dev/iicbus/iicbus.h>
61
62#include "iicbb_if.h"
63#include "gpio_if.h"
64
65#define IIC_M_WR 0 /* write operation */
66#define PLD_ADDR 0xac /* slave address */
67
68#define I2C_DELAY 10
69
70#define GPIO_CONF_CLR(sc, reg, mask) \
71 GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) &~ (mask))
72#define GPIO_CONF_SET(sc, reg, mask) \
73 GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) | (mask))
74
75#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
76#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
77#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
78
79#define GPIO_PINS 5
80struct cambria_gpio_softc {
81 device_t sc_dev;
| 60#include <dev/iicbus/iiconf.h>
61#include <dev/iicbus/iicbus.h>
62
63#include "iicbb_if.h"
64#include "gpio_if.h"
65
66#define IIC_M_WR 0 /* write operation */
67#define PLD_ADDR 0xac /* slave address */
68
69#define I2C_DELAY 10
70
71#define GPIO_CONF_CLR(sc, reg, mask) \
72 GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) &~ (mask))
73#define GPIO_CONF_SET(sc, reg, mask) \
74 GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) | (mask))
75
76#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
77#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
78#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
79
80#define GPIO_PINS 5
81struct cambria_gpio_softc {
82 device_t sc_dev;
|
| 83 device_t sc_busdev;
|
82 bus_space_tag_t sc_iot;
83 bus_space_handle_t sc_gpio_ioh;
84 struct mtx sc_mtx;
85 struct gpio_pin sc_pins[GPIO_PINS];
86 uint8_t sc_latch;
87 uint8_t sc_val;
88};
89
90struct cambria_gpio_pin {
91 const char *name;
92 int pin;
93 int flags;
94};
95
96extern struct ixp425_softc *ixp425_softc;
97
98static struct cambria_gpio_pin cambria_gpio_pins[GPIO_PINS] = {
99 { "PLD0", 0, GPIO_PIN_OUTPUT },
100 { "PLD1", 1, GPIO_PIN_OUTPUT },
101 { "PLD2", 2, GPIO_PIN_OUTPUT },
102 { "PLD3", 3, GPIO_PIN_OUTPUT },
103 { "PLD4", 4, GPIO_PIN_OUTPUT },
104};
105
106/*
107 * Helpers
108 */
109static int cambria_gpio_read(struct cambria_gpio_softc *, uint32_t, unsigned int *);
110static int cambria_gpio_write(struct cambria_gpio_softc *);
111
112/*
113 * Driver stuff
114 */
115static int cambria_gpio_probe(device_t dev);
116static int cambria_gpio_attach(device_t dev);
117static int cambria_gpio_detach(device_t dev);
118
119/*
120 * GPIO interface
121 */
| 84 bus_space_tag_t sc_iot;
85 bus_space_handle_t sc_gpio_ioh;
86 struct mtx sc_mtx;
87 struct gpio_pin sc_pins[GPIO_PINS];
88 uint8_t sc_latch;
89 uint8_t sc_val;
90};
91
92struct cambria_gpio_pin {
93 const char *name;
94 int pin;
95 int flags;
96};
97
98extern struct ixp425_softc *ixp425_softc;
99
100static struct cambria_gpio_pin cambria_gpio_pins[GPIO_PINS] = {
101 { "PLD0", 0, GPIO_PIN_OUTPUT },
102 { "PLD1", 1, GPIO_PIN_OUTPUT },
103 { "PLD2", 2, GPIO_PIN_OUTPUT },
104 { "PLD3", 3, GPIO_PIN_OUTPUT },
105 { "PLD4", 4, GPIO_PIN_OUTPUT },
106};
107
108/*
109 * Helpers
110 */
111static int cambria_gpio_read(struct cambria_gpio_softc *, uint32_t, unsigned int *);
112static int cambria_gpio_write(struct cambria_gpio_softc *);
113
114/*
115 * Driver stuff
116 */
117static int cambria_gpio_probe(device_t dev);
118static int cambria_gpio_attach(device_t dev);
119static int cambria_gpio_detach(device_t dev);
120
121/*
122 * GPIO interface
123 */
|
| 124static device_t cambria_gpio_get_bus(device_t);
|
122static int cambria_gpio_pin_max(device_t dev, int *maxpin);
123static int cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
124static int cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
125 *flags);
126static int cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
127static int cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
128static int cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
129static int cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
130static int cambria_gpio_pin_toggle(device_t dev, uint32_t pin);
131
132static int
133i2c_getsda(struct cambria_gpio_softc *sc)
134{
135 uint32_t reg;
136
137 IXP4XX_GPIO_LOCK();
138 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
139
140 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
141 IXP4XX_GPIO_UNLOCK();
142 return (reg & GPIO_I2C_SDA_BIT);
143}
144
145static void
146i2c_setsda(struct cambria_gpio_softc *sc, int val)
147{
148
149 IXP4XX_GPIO_LOCK();
150 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT);
151 if (val)
152 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
153 else
154 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
155 IXP4XX_GPIO_UNLOCK();
156 DELAY(I2C_DELAY);
157}
158
159static void
160i2c_setscl(struct cambria_gpio_softc *sc, int val)
161{
162
163 IXP4XX_GPIO_LOCK();
164 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT);
165 if (val)
166 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
167 else
168 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
169 IXP4XX_GPIO_UNLOCK();
170 DELAY(I2C_DELAY);
171}
172
173static void
174i2c_sendstart(struct cambria_gpio_softc *sc)
175{
176 i2c_setsda(sc, 1);
177 i2c_setscl(sc, 1);
178 i2c_setsda(sc, 0);
179 i2c_setscl(sc, 0);
180}
181
182static void
183i2c_sendstop(struct cambria_gpio_softc *sc)
184{
185 i2c_setscl(sc, 1);
186 i2c_setsda(sc, 1);
187 i2c_setscl(sc, 0);
188 i2c_setsda(sc, 0);
189}
190
191static void
192i2c_sendbyte(struct cambria_gpio_softc *sc, u_char data)
193{
194 int i;
195
196 for (i=7; i>=0; i--) {
197 i2c_setsda(sc, data & (1<<i));
198 i2c_setscl(sc, 1);
199 i2c_setscl(sc, 0);
200 }
201 i2c_setscl(sc, 1);
202 i2c_getsda(sc);
203 i2c_setscl(sc, 0);
204}
205
206static u_char
207i2c_readbyte(struct cambria_gpio_softc *sc)
208{
209 int i;
210 unsigned char data=0;
211
212 for (i=7; i>=0; i--)
213 {
214 i2c_setscl(sc, 1);
215 if (i2c_getsda(sc))
216 data |= (1<<i);
217 i2c_setscl(sc, 0);
218 }
219 return data;
220}
221
222static int
223cambria_gpio_read(struct cambria_gpio_softc *sc, uint32_t pin, unsigned int *val)
224{
225 device_t dev = sc->sc_dev;
226 int error;
227
228 error = iicbus_request_bus(device_get_parent(dev), dev,
229 IIC_DONTWAIT);
230 if (error)
231 return (error);
232
233 i2c_sendstart(sc);
234 i2c_sendbyte(sc, PLD_ADDR | LSB);
235 *val = (i2c_readbyte(sc) & (1 << pin)) != 0;
236 i2c_sendstop(sc);
237
238 iicbus_release_bus(device_get_parent(dev), dev);
239
240 return (0);
241}
242
243static int
244cambria_gpio_write(struct cambria_gpio_softc *sc)
245{
246 device_t dev = sc->sc_dev;
247 int error;
248
249 error = iicbus_request_bus(device_get_parent(dev), dev,
250 IIC_DONTWAIT);
251 if (error)
252 return (error);
253
254 i2c_sendstart(sc);
255 i2c_sendbyte(sc, PLD_ADDR & ~LSB);
256 i2c_sendbyte(sc, sc->sc_latch);
257 i2c_sendstop(sc);
258
259 iicbus_release_bus(device_get_parent(dev), dev);
260
261 return (0);
262}
263
| 125static int cambria_gpio_pin_max(device_t dev, int *maxpin);
126static int cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
127static int cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
128 *flags);
129static int cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
130static int cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
131static int cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
132static int cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
133static int cambria_gpio_pin_toggle(device_t dev, uint32_t pin);
134
135static int
136i2c_getsda(struct cambria_gpio_softc *sc)
137{
138 uint32_t reg;
139
140 IXP4XX_GPIO_LOCK();
141 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
142
143 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
144 IXP4XX_GPIO_UNLOCK();
145 return (reg & GPIO_I2C_SDA_BIT);
146}
147
148static void
149i2c_setsda(struct cambria_gpio_softc *sc, int val)
150{
151
152 IXP4XX_GPIO_LOCK();
153 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT);
154 if (val)
155 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
156 else
157 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
158 IXP4XX_GPIO_UNLOCK();
159 DELAY(I2C_DELAY);
160}
161
162static void
163i2c_setscl(struct cambria_gpio_softc *sc, int val)
164{
165
166 IXP4XX_GPIO_LOCK();
167 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT);
168 if (val)
169 GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
170 else
171 GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
172 IXP4XX_GPIO_UNLOCK();
173 DELAY(I2C_DELAY);
174}
175
176static void
177i2c_sendstart(struct cambria_gpio_softc *sc)
178{
179 i2c_setsda(sc, 1);
180 i2c_setscl(sc, 1);
181 i2c_setsda(sc, 0);
182 i2c_setscl(sc, 0);
183}
184
185static void
186i2c_sendstop(struct cambria_gpio_softc *sc)
187{
188 i2c_setscl(sc, 1);
189 i2c_setsda(sc, 1);
190 i2c_setscl(sc, 0);
191 i2c_setsda(sc, 0);
192}
193
194static void
195i2c_sendbyte(struct cambria_gpio_softc *sc, u_char data)
196{
197 int i;
198
199 for (i=7; i>=0; i--) {
200 i2c_setsda(sc, data & (1<<i));
201 i2c_setscl(sc, 1);
202 i2c_setscl(sc, 0);
203 }
204 i2c_setscl(sc, 1);
205 i2c_getsda(sc);
206 i2c_setscl(sc, 0);
207}
208
209static u_char
210i2c_readbyte(struct cambria_gpio_softc *sc)
211{
212 int i;
213 unsigned char data=0;
214
215 for (i=7; i>=0; i--)
216 {
217 i2c_setscl(sc, 1);
218 if (i2c_getsda(sc))
219 data |= (1<<i);
220 i2c_setscl(sc, 0);
221 }
222 return data;
223}
224
225static int
226cambria_gpio_read(struct cambria_gpio_softc *sc, uint32_t pin, unsigned int *val)
227{
228 device_t dev = sc->sc_dev;
229 int error;
230
231 error = iicbus_request_bus(device_get_parent(dev), dev,
232 IIC_DONTWAIT);
233 if (error)
234 return (error);
235
236 i2c_sendstart(sc);
237 i2c_sendbyte(sc, PLD_ADDR | LSB);
238 *val = (i2c_readbyte(sc) & (1 << pin)) != 0;
239 i2c_sendstop(sc);
240
241 iicbus_release_bus(device_get_parent(dev), dev);
242
243 return (0);
244}
245
246static int
247cambria_gpio_write(struct cambria_gpio_softc *sc)
248{
249 device_t dev = sc->sc_dev;
250 int error;
251
252 error = iicbus_request_bus(device_get_parent(dev), dev,
253 IIC_DONTWAIT);
254 if (error)
255 return (error);
256
257 i2c_sendstart(sc);
258 i2c_sendbyte(sc, PLD_ADDR & ~LSB);
259 i2c_sendbyte(sc, sc->sc_latch);
260 i2c_sendstop(sc);
261
262 iicbus_release_bus(device_get_parent(dev), dev);
263
264 return (0);
265}
266
|
| 267static device_t
268cambria_gpio_get_bus(device_t dev)
269{
270 struct cambria_gpio_softc *sc;
271
272 sc = device_get_softc(dev);
273
274 return (sc->sc_busdev);
275}
276
|
264static int
265cambria_gpio_pin_max(device_t dev, int *maxpin)
266{
267
268 *maxpin = GPIO_PINS - 1;
269 return (0);
270}
271
272static int
273cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
274{
275 struct cambria_gpio_softc *sc = device_get_softc(dev);
276
277 if (pin >= GPIO_PINS)
278 return (EINVAL);
279
280 *caps = sc->sc_pins[pin].gp_caps;
281 return (0);
282}
283
284static int
285cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
286{
287 struct cambria_gpio_softc *sc = device_get_softc(dev);
288
289 if (pin >= GPIO_PINS)
290 return (EINVAL);
291
292 *flags = sc->sc_pins[pin].gp_flags;
293 return (0);
294}
295
296static int
297cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
298{
299 struct cambria_gpio_softc *sc = device_get_softc(dev);
300
301 if (pin >= GPIO_PINS)
302 return (EINVAL);
303
304 memcpy(name, sc->sc_pins[pin].gp_name, GPIOMAXNAME);
305 return (0);
306}
307
308static int
309cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
310{
311 struct cambria_gpio_softc *sc = device_get_softc(dev);
312 int error;
313 uint8_t mask;
314
315 mask = 1 << pin;
316
317 if (pin >= GPIO_PINS)
318 return (EINVAL);
319
320 GPIO_LOCK(sc);
321 sc->sc_pins[pin].gp_flags = flags;
322
323 /*
324 * Writing a logical one sets the signal high and writing a logical
325 * zero sets the signal low. To configure a digital I/O signal as an
326 * input, a logical one must first be written to the data bit to
327 * three-state the associated output.
328 */
329 if (flags & GPIO_PIN_INPUT || sc->sc_val & mask)
330 sc->sc_latch |= mask; /* input or output & high */
331 else
332 sc->sc_latch &= ~mask;
333 error = cambria_gpio_write(sc);
334 GPIO_UNLOCK(sc);
335
336 return (error);
337}
338
339static int
340cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
341{
342 struct cambria_gpio_softc *sc = device_get_softc(dev);
343 int error;
344 uint8_t mask;
345
346 mask = 1 << pin;
347
348 if (pin >= GPIO_PINS)
349 return (EINVAL);
350 GPIO_LOCK(sc);
351 if (value)
352 sc->sc_val |= mask;
353 else
354 sc->sc_val &= ~mask;
355
356 if (sc->sc_pins[pin].gp_flags != GPIO_PIN_OUTPUT) {
357 /* just save, altering the latch will disable input */
358 GPIO_UNLOCK(sc);
359 return (0);
360 }
361
362 if (value)
363 sc->sc_latch |= mask;
364 else
365 sc->sc_latch &= ~mask;
366 error = cambria_gpio_write(sc);
367 GPIO_UNLOCK(sc);
368
369 return (error);
370}
371
372static int
373cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
374{
375 struct cambria_gpio_softc *sc = device_get_softc(dev);
376 int error = 0;
377
378 if (pin >= GPIO_PINS)
379 return (EINVAL);
380
381 GPIO_LOCK(sc);
382 if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT)
383 *val = (sc->sc_latch & (1 << pin)) ? 1 : 0;
384 else
385 error = cambria_gpio_read(sc, pin, val);
386 GPIO_UNLOCK(sc);
387
388 return (error);
389}
390
391static int
392cambria_gpio_pin_toggle(device_t dev, uint32_t pin)
393{
394 struct cambria_gpio_softc *sc = device_get_softc(dev);
395 int error = 0;
396
397 if (pin >= GPIO_PINS)
398 return (EINVAL);
399
400 GPIO_LOCK(sc);
401 sc->sc_val ^= (1 << pin);
402 if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT) {
403 sc->sc_latch ^= (1 << pin);
404 error = cambria_gpio_write(sc);
405 }
406 GPIO_UNLOCK(sc);
407
408 return (error);
409}
410
411static int
412cambria_gpio_probe(device_t dev)
413{
414
415 device_set_desc(dev, "Gateworks Cambria GPIO driver");
416 return (0);
417}
418
419static int
420cambria_gpio_attach(device_t dev)
421{
422 struct cambria_gpio_softc *sc = device_get_softc(dev);
423 int pin;
424
425 sc->sc_dev = dev;
426 sc->sc_iot = ixp425_softc->sc_iot;
427 sc->sc_gpio_ioh = ixp425_softc->sc_gpio_ioh;
428
429 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
430
431 for (pin = 0; pin < GPIO_PINS; pin++) {
432 struct cambria_gpio_pin *p = &cambria_gpio_pins[pin];
433
434 strncpy(sc->sc_pins[pin].gp_name, p->name, GPIOMAXNAME);
435 sc->sc_pins[pin].gp_pin = pin;
436 sc->sc_pins[pin].gp_caps = GPIO_PIN_INPUT|GPIO_PIN_OUTPUT;
437 sc->sc_pins[pin].gp_flags = 0;
438 cambria_gpio_pin_setflags(dev, pin, p->flags);
439 }
440
| 277static int
278cambria_gpio_pin_max(device_t dev, int *maxpin)
279{
280
281 *maxpin = GPIO_PINS - 1;
282 return (0);
283}
284
285static int
286cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
287{
288 struct cambria_gpio_softc *sc = device_get_softc(dev);
289
290 if (pin >= GPIO_PINS)
291 return (EINVAL);
292
293 *caps = sc->sc_pins[pin].gp_caps;
294 return (0);
295}
296
297static int
298cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
299{
300 struct cambria_gpio_softc *sc = device_get_softc(dev);
301
302 if (pin >= GPIO_PINS)
303 return (EINVAL);
304
305 *flags = sc->sc_pins[pin].gp_flags;
306 return (0);
307}
308
309static int
310cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
311{
312 struct cambria_gpio_softc *sc = device_get_softc(dev);
313
314 if (pin >= GPIO_PINS)
315 return (EINVAL);
316
317 memcpy(name, sc->sc_pins[pin].gp_name, GPIOMAXNAME);
318 return (0);
319}
320
321static int
322cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
323{
324 struct cambria_gpio_softc *sc = device_get_softc(dev);
325 int error;
326 uint8_t mask;
327
328 mask = 1 << pin;
329
330 if (pin >= GPIO_PINS)
331 return (EINVAL);
332
333 GPIO_LOCK(sc);
334 sc->sc_pins[pin].gp_flags = flags;
335
336 /*
337 * Writing a logical one sets the signal high and writing a logical
338 * zero sets the signal low. To configure a digital I/O signal as an
339 * input, a logical one must first be written to the data bit to
340 * three-state the associated output.
341 */
342 if (flags & GPIO_PIN_INPUT || sc->sc_val & mask)
343 sc->sc_latch |= mask; /* input or output & high */
344 else
345 sc->sc_latch &= ~mask;
346 error = cambria_gpio_write(sc);
347 GPIO_UNLOCK(sc);
348
349 return (error);
350}
351
352static int
353cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
354{
355 struct cambria_gpio_softc *sc = device_get_softc(dev);
356 int error;
357 uint8_t mask;
358
359 mask = 1 << pin;
360
361 if (pin >= GPIO_PINS)
362 return (EINVAL);
363 GPIO_LOCK(sc);
364 if (value)
365 sc->sc_val |= mask;
366 else
367 sc->sc_val &= ~mask;
368
369 if (sc->sc_pins[pin].gp_flags != GPIO_PIN_OUTPUT) {
370 /* just save, altering the latch will disable input */
371 GPIO_UNLOCK(sc);
372 return (0);
373 }
374
375 if (value)
376 sc->sc_latch |= mask;
377 else
378 sc->sc_latch &= ~mask;
379 error = cambria_gpio_write(sc);
380 GPIO_UNLOCK(sc);
381
382 return (error);
383}
384
385static int
386cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
387{
388 struct cambria_gpio_softc *sc = device_get_softc(dev);
389 int error = 0;
390
391 if (pin >= GPIO_PINS)
392 return (EINVAL);
393
394 GPIO_LOCK(sc);
395 if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT)
396 *val = (sc->sc_latch & (1 << pin)) ? 1 : 0;
397 else
398 error = cambria_gpio_read(sc, pin, val);
399 GPIO_UNLOCK(sc);
400
401 return (error);
402}
403
404static int
405cambria_gpio_pin_toggle(device_t dev, uint32_t pin)
406{
407 struct cambria_gpio_softc *sc = device_get_softc(dev);
408 int error = 0;
409
410 if (pin >= GPIO_PINS)
411 return (EINVAL);
412
413 GPIO_LOCK(sc);
414 sc->sc_val ^= (1 << pin);
415 if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT) {
416 sc->sc_latch ^= (1 << pin);
417 error = cambria_gpio_write(sc);
418 }
419 GPIO_UNLOCK(sc);
420
421 return (error);
422}
423
424static int
425cambria_gpio_probe(device_t dev)
426{
427
428 device_set_desc(dev, "Gateworks Cambria GPIO driver");
429 return (0);
430}
431
432static int
433cambria_gpio_attach(device_t dev)
434{
435 struct cambria_gpio_softc *sc = device_get_softc(dev);
436 int pin;
437
438 sc->sc_dev = dev;
439 sc->sc_iot = ixp425_softc->sc_iot;
440 sc->sc_gpio_ioh = ixp425_softc->sc_gpio_ioh;
441
442 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
443
444 for (pin = 0; pin < GPIO_PINS; pin++) {
445 struct cambria_gpio_pin *p = &cambria_gpio_pins[pin];
446
447 strncpy(sc->sc_pins[pin].gp_name, p->name, GPIOMAXNAME);
448 sc->sc_pins[pin].gp_pin = pin;
449 sc->sc_pins[pin].gp_caps = GPIO_PIN_INPUT|GPIO_PIN_OUTPUT;
450 sc->sc_pins[pin].gp_flags = 0;
451 cambria_gpio_pin_setflags(dev, pin, p->flags);
452 }
453
|
441 device_add_child(dev, "gpioc", -1);
442 device_add_child(dev, "gpiobus", -1);
| 454 sc->sc_busdev = gpiobus_attach_bus(dev);
455 if (sc->sc_busdev == NULL) {
456 mtx_destroy(&sc->sc_mtx);
457 return (ENXIO);
458 }
|
443
| 459
|
444 return (bus_generic_attach(dev));
| 460 return (0);
|
445}
446
447static int
448cambria_gpio_detach(device_t dev)
449{
450 struct cambria_gpio_softc *sc = device_get_softc(dev);
451
452 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
453
| 461}
462
463static int
464cambria_gpio_detach(device_t dev)
465{
466 struct cambria_gpio_softc *sc = device_get_softc(dev);
467
468 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
469
|
454 bus_generic_detach(dev);
455
| 470 gpiobus_detach_bus(dev);
|
456 mtx_destroy(&sc->sc_mtx);
457
458 return(0);
459}
460
461static device_method_t cambria_gpio_methods[] = {
462 DEVMETHOD(device_probe, cambria_gpio_probe),
463 DEVMETHOD(device_attach, cambria_gpio_attach),
464 DEVMETHOD(device_detach, cambria_gpio_detach),
465
466 /* GPIO protocol */
| 471 mtx_destroy(&sc->sc_mtx);
472
473 return(0);
474}
475
476static device_method_t cambria_gpio_methods[] = {
477 DEVMETHOD(device_probe, cambria_gpio_probe),
478 DEVMETHOD(device_attach, cambria_gpio_attach),
479 DEVMETHOD(device_detach, cambria_gpio_detach),
480
481 /* GPIO protocol */
|
| 482 DEVMETHOD(gpio_get_bus, cambria_gpio_get_bus),
|
467 DEVMETHOD(gpio_pin_max, cambria_gpio_pin_max),
468 DEVMETHOD(gpio_pin_getname, cambria_gpio_pin_getname),
469 DEVMETHOD(gpio_pin_getflags, cambria_gpio_pin_getflags),
470 DEVMETHOD(gpio_pin_getcaps, cambria_gpio_pin_getcaps),
471 DEVMETHOD(gpio_pin_setflags, cambria_gpio_pin_setflags),
472 DEVMETHOD(gpio_pin_get, cambria_gpio_pin_get),
473 DEVMETHOD(gpio_pin_set, cambria_gpio_pin_set),
474 DEVMETHOD(gpio_pin_toggle, cambria_gpio_pin_toggle),
475 {0, 0},
476};
477
478static driver_t cambria_gpio_driver = {
479 "gpio",
480 cambria_gpio_methods,
481 sizeof(struct cambria_gpio_softc),
482};
483static devclass_t cambria_gpio_devclass;
484
485DRIVER_MODULE(gpio_cambria, iicbus, cambria_gpio_driver, cambria_gpio_devclass, 0, 0);
486MODULE_VERSION(gpio_cambria, 1);
487MODULE_DEPEND(gpio_cambria, iicbus, 1, 1, 1);
| 483 DEVMETHOD(gpio_pin_max, cambria_gpio_pin_max),
484 DEVMETHOD(gpio_pin_getname, cambria_gpio_pin_getname),
485 DEVMETHOD(gpio_pin_getflags, cambria_gpio_pin_getflags),
486 DEVMETHOD(gpio_pin_getcaps, cambria_gpio_pin_getcaps),
487 DEVMETHOD(gpio_pin_setflags, cambria_gpio_pin_setflags),
488 DEVMETHOD(gpio_pin_get, cambria_gpio_pin_get),
489 DEVMETHOD(gpio_pin_set, cambria_gpio_pin_set),
490 DEVMETHOD(gpio_pin_toggle, cambria_gpio_pin_toggle),
491 {0, 0},
492};
493
494static driver_t cambria_gpio_driver = {
495 "gpio",
496 cambria_gpio_methods,
497 sizeof(struct cambria_gpio_softc),
498};
499static devclass_t cambria_gpio_devclass;
500
501DRIVER_MODULE(gpio_cambria, iicbus, cambria_gpio_driver, cambria_gpio_devclass, 0, 0);
502MODULE_VERSION(gpio_cambria, 1);
503MODULE_DEPEND(gpio_cambria, iicbus, 1, 1, 1);
|