1/*-
2 * Copyright (c) 2009 Sam Leffler. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25/*
26 * Bus space tag for devices on the Cambria expansion bus.
27 * This interlocks accesses to allow the optional GPS+RS485 UART's
28 * to share access with the CF-IDE adapter. Note this does not
29 * slow the timing UART r/w ops because the lock operation does
30 * this implicitly for us. Also note we do not DELAY after byte/word
31 * chip select changes; this doesn't seem necessary (as required
32 * for IXP425/Avila boards).
33 *
34 * XXX should make this generic so all expansion bus devices can
35 * use it but probably not until we eliminate the ATA hacks
36 */
37
38#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2009 Sam Leffler. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25/*
26 * Bus space tag for devices on the Cambria expansion bus.
27 * This interlocks accesses to allow the optional GPS+RS485 UART's
28 * to share access with the CF-IDE adapter. Note this does not
29 * slow the timing UART r/w ops because the lock operation does
30 * this implicitly for us. Also note we do not DELAY after byte/word
31 * chip select changes; this doesn't seem necessary (as required
32 * for IXP425/Avila boards).
33 *
34 * XXX should make this generic so all expansion bus devices can
35 * use it but probably not until we eliminate the ATA hacks
36 */
37
38#include <sys/cdefs.h>
|
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/lock.h>
44#include <sys/mutex.h>
45#include <sys/bus.h>
46#include <sys/endian.h>
47
48#include <machine/bus.h>
49#include <machine/cpu.h>
50
51#include <arm/xscale/ixp425/ixp425reg.h>
52#include <arm/xscale/ixp425/ixp425var.h>
53
54/* Prototypes for all the bus_space structure functions */
55bs_protos(exp);
56bs_protos(generic);
57
58struct expbus_softc {
59 struct ixp425_softc *sc; /* bus space tag */
60 struct mtx lock; /* i/o interlock */
61 bus_size_t csoff; /* CS offset for 8/16 enable */
62};
63#define EXP_LOCK_INIT(exp) \
64 mtx_init(&(exp)->lock, "ExpBus", NULL, MTX_SPIN)
65#define EXP_LOCK_DESTROY(exp) \
66 mtx_destroy(&(exp)->lock)
67#define EXP_LOCK(exp) mtx_lock_spin(&(exp)->lock)
68#define EXP_UNLOCK(exp) mtx_unlock_spin(&(exp)->lock)
69
70/*
71 * Enable/disable 16-bit ops on the expansion bus.
72 */
73static __inline void
74enable_16(struct ixp425_softc *sc, bus_size_t cs)
75{
76 EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) &~ EXP_BYTE_EN);
77}
78
79static __inline void
80disable_16(struct ixp425_softc *sc, bus_size_t cs)
81{
82 EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) | EXP_BYTE_EN);
83}
84
85static uint8_t
86cambria_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o)
87{
88 struct expbus_softc *exp = t;
89 struct ixp425_softc *sc = exp->sc;
90 uint8_t v;
91
92 EXP_LOCK(exp);
93 v = bus_space_read_1(sc->sc_iot, h, o);
94 EXP_UNLOCK(exp);
95 return v;
96}
97
98static void
99cambria_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
100{
101 struct expbus_softc *exp = t;
102 struct ixp425_softc *sc = exp->sc;
103
104 EXP_LOCK(exp);
105 bus_space_write_1(sc->sc_iot, h, o, v);
106 EXP_UNLOCK(exp);
107}
108
109static uint16_t
110cambria_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o)
111{
112 struct expbus_softc *exp = t;
113 struct ixp425_softc *sc = exp->sc;
114 uint16_t v;
115
116 EXP_LOCK(exp);
117 enable_16(sc, exp->csoff);
118 v = bus_space_read_2(sc->sc_iot, h, o);
119 disable_16(sc, exp->csoff);
120 EXP_UNLOCK(exp);
121 return v;
122}
123
124static void
125cambria_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
126{
127 struct expbus_softc *exp = t;
128 struct ixp425_softc *sc = exp->sc;
129
130 EXP_LOCK(exp);
131 enable_16(sc, exp->csoff);
132 bus_space_write_2(sc->sc_iot, h, o, v);
133 disable_16(sc, exp->csoff);
134 EXP_UNLOCK(exp);
135}
136
137static void
138cambria_bs_rm_2(void *t, bus_space_handle_t h, bus_size_t o,
139 u_int16_t *d, bus_size_t c)
140{
141 struct expbus_softc *exp = t;
142 struct ixp425_softc *sc = exp->sc;
143
144 EXP_LOCK(exp);
145 enable_16(sc, exp->csoff);
146 bus_space_read_multi_2(sc->sc_iot, h, o, d, c);
147 disable_16(sc, exp->csoff);
148 EXP_UNLOCK(exp);
149}
150
151static void
152cambria_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o,
153 const u_int16_t *d, bus_size_t c)
154{
155 struct expbus_softc *exp = t;
156 struct ixp425_softc *sc = exp->sc;
157
158 EXP_LOCK(exp);
159 enable_16(sc, exp->csoff);
160 bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
161 disable_16(sc, exp->csoff);
162 EXP_UNLOCK(exp);
163}
164
165/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */
166
167static void
168cambria_bs_rm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
169 u_int16_t *d, bus_size_t c)
170{
171 struct expbus_softc *exp = t;
172 struct ixp425_softc *sc = exp->sc;
173 uint16_t v;
174 bus_size_t i;
175
176 EXP_LOCK(exp);
177 enable_16(sc, exp->csoff);
178#if 1
179 for (i = 0; i < c; i++) {
180 v = bus_space_read_2(sc->sc_iot, h, o);
181 d[i] = bswap16(v);
182 }
183#else
184 bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c);
185#endif
186 disable_16(sc, exp->csoff);
187 EXP_UNLOCK(exp);
188}
189
190static void
191cambria_bs_wm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
192 const u_int16_t *d, bus_size_t c)
193{
194 struct expbus_softc *exp = t;
195 struct ixp425_softc *sc = exp->sc;
196 bus_size_t i;
197
198 EXP_LOCK(exp);
199 enable_16(sc, exp->csoff);
200#if 1
201 for (i = 0; i < c; i++)
202 bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i]));
203#else
204 bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c);
205#endif
206 disable_16(sc, exp->csoff);
207 EXP_UNLOCK(exp);
208}
209
210/* NB: we only define what's needed by ata+uart */
211struct bus_space cambria_exp_bs_tag = {
212 /* mapping/unmapping */
213 .bs_map = generic_bs_map,
214 .bs_unmap = generic_bs_unmap,
215
216 /* barrier */
217 .bs_barrier = generic_bs_barrier,
218
219 /* read (single) */
220 .bs_r_1 = cambria_bs_r_1,
221 .bs_r_2 = cambria_bs_r_2,
222
223 /* write (single) */
224 .bs_w_1 = cambria_bs_w_1,
225 .bs_w_2 = cambria_bs_w_2,
226
227 /* read multiple */
228 .bs_rm_2 = cambria_bs_rm_2,
229 .bs_rm_2_s = cambria_bs_rm_2_s,
230
231 /* write multiple */
232 .bs_wm_2 = cambria_bs_wm_2,
233 .bs_wm_2_s = cambria_bs_wm_2_s,
234};
235
236void
237cambria_exp_bus_init(struct ixp425_softc *sc)
238{
239 static struct expbus_softc c3; /* NB: no need to malloc */
240 uint32_t cs3;
241
242 KASSERT(cpu_is_ixp43x(), ("wrong cpu type"));
243
244 c3.sc = sc;
245 c3.csoff = EXP_TIMING_CS3_OFFSET;
246 EXP_LOCK_INIT(&c3);
247 cambria_exp_bs_tag.bs_cookie = &c3;
248
249 cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET);
250 /* XXX force slowest possible timings and byte mode */
251 EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET,
| 40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/lock.h>
44#include <sys/mutex.h>
45#include <sys/bus.h>
46#include <sys/endian.h>
47
48#include <machine/bus.h>
49#include <machine/cpu.h>
50
51#include <arm/xscale/ixp425/ixp425reg.h>
52#include <arm/xscale/ixp425/ixp425var.h>
53
54/* Prototypes for all the bus_space structure functions */
55bs_protos(exp);
56bs_protos(generic);
57
58struct expbus_softc {
59 struct ixp425_softc *sc; /* bus space tag */
60 struct mtx lock; /* i/o interlock */
61 bus_size_t csoff; /* CS offset for 8/16 enable */
62};
63#define EXP_LOCK_INIT(exp) \
64 mtx_init(&(exp)->lock, "ExpBus", NULL, MTX_SPIN)
65#define EXP_LOCK_DESTROY(exp) \
66 mtx_destroy(&(exp)->lock)
67#define EXP_LOCK(exp) mtx_lock_spin(&(exp)->lock)
68#define EXP_UNLOCK(exp) mtx_unlock_spin(&(exp)->lock)
69
70/*
71 * Enable/disable 16-bit ops on the expansion bus.
72 */
73static __inline void
74enable_16(struct ixp425_softc *sc, bus_size_t cs)
75{
76 EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) &~ EXP_BYTE_EN);
77}
78
79static __inline void
80disable_16(struct ixp425_softc *sc, bus_size_t cs)
81{
82 EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) | EXP_BYTE_EN);
83}
84
85static uint8_t
86cambria_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o)
87{
88 struct expbus_softc *exp = t;
89 struct ixp425_softc *sc = exp->sc;
90 uint8_t v;
91
92 EXP_LOCK(exp);
93 v = bus_space_read_1(sc->sc_iot, h, o);
94 EXP_UNLOCK(exp);
95 return v;
96}
97
98static void
99cambria_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
100{
101 struct expbus_softc *exp = t;
102 struct ixp425_softc *sc = exp->sc;
103
104 EXP_LOCK(exp);
105 bus_space_write_1(sc->sc_iot, h, o, v);
106 EXP_UNLOCK(exp);
107}
108
109static uint16_t
110cambria_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o)
111{
112 struct expbus_softc *exp = t;
113 struct ixp425_softc *sc = exp->sc;
114 uint16_t v;
115
116 EXP_LOCK(exp);
117 enable_16(sc, exp->csoff);
118 v = bus_space_read_2(sc->sc_iot, h, o);
119 disable_16(sc, exp->csoff);
120 EXP_UNLOCK(exp);
121 return v;
122}
123
124static void
125cambria_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
126{
127 struct expbus_softc *exp = t;
128 struct ixp425_softc *sc = exp->sc;
129
130 EXP_LOCK(exp);
131 enable_16(sc, exp->csoff);
132 bus_space_write_2(sc->sc_iot, h, o, v);
133 disable_16(sc, exp->csoff);
134 EXP_UNLOCK(exp);
135}
136
137static void
138cambria_bs_rm_2(void *t, bus_space_handle_t h, bus_size_t o,
139 u_int16_t *d, bus_size_t c)
140{
141 struct expbus_softc *exp = t;
142 struct ixp425_softc *sc = exp->sc;
143
144 EXP_LOCK(exp);
145 enable_16(sc, exp->csoff);
146 bus_space_read_multi_2(sc->sc_iot, h, o, d, c);
147 disable_16(sc, exp->csoff);
148 EXP_UNLOCK(exp);
149}
150
151static void
152cambria_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o,
153 const u_int16_t *d, bus_size_t c)
154{
155 struct expbus_softc *exp = t;
156 struct ixp425_softc *sc = exp->sc;
157
158 EXP_LOCK(exp);
159 enable_16(sc, exp->csoff);
160 bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
161 disable_16(sc, exp->csoff);
162 EXP_UNLOCK(exp);
163}
164
165/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */
166
167static void
168cambria_bs_rm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
169 u_int16_t *d, bus_size_t c)
170{
171 struct expbus_softc *exp = t;
172 struct ixp425_softc *sc = exp->sc;
173 uint16_t v;
174 bus_size_t i;
175
176 EXP_LOCK(exp);
177 enable_16(sc, exp->csoff);
178#if 1
179 for (i = 0; i < c; i++) {
180 v = bus_space_read_2(sc->sc_iot, h, o);
181 d[i] = bswap16(v);
182 }
183#else
184 bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c);
185#endif
186 disable_16(sc, exp->csoff);
187 EXP_UNLOCK(exp);
188}
189
190static void
191cambria_bs_wm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
192 const u_int16_t *d, bus_size_t c)
193{
194 struct expbus_softc *exp = t;
195 struct ixp425_softc *sc = exp->sc;
196 bus_size_t i;
197
198 EXP_LOCK(exp);
199 enable_16(sc, exp->csoff);
200#if 1
201 for (i = 0; i < c; i++)
202 bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i]));
203#else
204 bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c);
205#endif
206 disable_16(sc, exp->csoff);
207 EXP_UNLOCK(exp);
208}
209
210/* NB: we only define what's needed by ata+uart */
211struct bus_space cambria_exp_bs_tag = {
212 /* mapping/unmapping */
213 .bs_map = generic_bs_map,
214 .bs_unmap = generic_bs_unmap,
215
216 /* barrier */
217 .bs_barrier = generic_bs_barrier,
218
219 /* read (single) */
220 .bs_r_1 = cambria_bs_r_1,
221 .bs_r_2 = cambria_bs_r_2,
222
223 /* write (single) */
224 .bs_w_1 = cambria_bs_w_1,
225 .bs_w_2 = cambria_bs_w_2,
226
227 /* read multiple */
228 .bs_rm_2 = cambria_bs_rm_2,
229 .bs_rm_2_s = cambria_bs_rm_2_s,
230
231 /* write multiple */
232 .bs_wm_2 = cambria_bs_wm_2,
233 .bs_wm_2_s = cambria_bs_wm_2_s,
234};
235
236void
237cambria_exp_bus_init(struct ixp425_softc *sc)
238{
239 static struct expbus_softc c3; /* NB: no need to malloc */
240 uint32_t cs3;
241
242 KASSERT(cpu_is_ixp43x(), ("wrong cpu type"));
243
244 c3.sc = sc;
245 c3.csoff = EXP_TIMING_CS3_OFFSET;
246 EXP_LOCK_INIT(&c3);
247 cambria_exp_bs_tag.bs_cookie = &c3;
248
249 cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET);
250 /* XXX force slowest possible timings and byte mode */
251 EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET,
|