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ti_gpio.c (276315) ti_gpio.c (277968)
1/*-
2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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26 */
27
28/**
29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
30 * here uses 0-5.
31 */
32
33#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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26 */
27
28/**
29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
30 * here uses 0-5.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/arm/ti/ti_gpio.c 276315 2014-12-27 19:56:04Z loos $");
34__FBSDID("$FreeBSD: head/sys/arm/ti/ti_gpio.c 277968 2015-01-31 12:17:07Z loos $");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/rman.h>

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108#define AM335X_FIRST_GPIO_BANK 0
109#define AM335X_INTR_PER_BANK 2
110#define AM335X_GPIO_REV 0x50600801
111#define PINS_PER_BANK 32
112#define TI_GPIO_BANK(p) ((p) / PINS_PER_BANK)
113#define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
114
115static struct ti_gpio_softc *ti_gpio_sc = NULL;
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/rman.h>

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108#define AM335X_FIRST_GPIO_BANK 0
109#define AM335X_INTR_PER_BANK 2
110#define AM335X_GPIO_REV 0x50600801
111#define PINS_PER_BANK 32
112#define TI_GPIO_BANK(p) ((p) / PINS_PER_BANK)
113#define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
114
115static struct ti_gpio_softc *ti_gpio_sc = NULL;
116static int ti_gpio_detach(device_t);
116
117static u_int
118ti_max_gpio_banks(void)
119{
120 switch(ti_chip()) {
121#ifdef SOC_OMAP4
122 case CHIP_OMAP_4:
123 return (OMAP4_MAX_GPIO_BANKS);

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758 sc->sc_maxpin++;
759
760 /* There are up to 6 different GPIO register sets located in different
761 * memory areas on the chip. The memory range should have been set for
762 * the driver when it was added as a child.
763 */
764 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
765 device_printf(dev, "Error: could not allocate mem resources\n");
117
118static u_int
119ti_max_gpio_banks(void)
120{
121 switch(ti_chip()) {
122#ifdef SOC_OMAP4
123 case CHIP_OMAP_4:
124 return (OMAP4_MAX_GPIO_BANKS);

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759 sc->sc_maxpin++;
760
761 /* There are up to 6 different GPIO register sets located in different
762 * memory areas on the chip. The memory range should have been set for
763 * the driver when it was added as a child.
764 */
765 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
766 device_printf(dev, "Error: could not allocate mem resources\n");
767 ti_gpio_detach(dev);
766 return (ENXIO);
767 }
768
769 /* Request the IRQ resources */
770 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
768 return (ENXIO);
769 }
770
771 /* Request the IRQ resources */
772 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
771 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
772 device_printf(dev, "Error: could not allocate irq resources\n");
773 device_printf(dev, "Error: could not allocate irq resources\n");
774 ti_gpio_detach(dev);
773 return (ENXIO);
774 }
775
776 /* Setup the IRQ resources */
777 if (ti_gpio_attach_intr(dev) != 0) {
775 return (ENXIO);
776 }
777
778 /* Setup the IRQ resources */
779 if (ti_gpio_attach_intr(dev) != 0) {
778 ti_gpio_detach_intr(dev);
779 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
780 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
780 device_printf(dev, "Error: could not setup irq handlers\n");
781 ti_gpio_detach(dev);
781 return (ENXIO);
782 }
783
784 /*
785 * Initialize the interrupt settings. The default is active-low
786 * interrupts.
787 */
788 sc->sc_irq_trigger = malloc(

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804 * pins are configured which would result in less power used if the GPIO
805 * pins weren't used ...
806 */
807 for (i = 0; i < ti_max_gpio_banks(); i++) {
808 if (sc->sc_mem_res[i] != NULL) {
809 /* Initialize the GPIO module. */
810 err = ti_gpio_bank_init(dev, i);
811 if (err != 0) {
782 return (ENXIO);
783 }
784
785 /*
786 * Initialize the interrupt settings. The default is active-low
787 * interrupts.
788 */
789 sc->sc_irq_trigger = malloc(

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805 * pins are configured which would result in less power used if the GPIO
806 * pins weren't used ...
807 */
808 for (i = 0; i < ti_max_gpio_banks(); i++) {
809 if (sc->sc_mem_res[i] != NULL) {
810 /* Initialize the GPIO module. */
811 err = ti_gpio_bank_init(dev, i);
812 if (err != 0) {
812 ti_gpio_detach_intr(dev);
813 bus_release_resources(dev, ti_gpio_irq_spec,
814 sc->sc_irq_res);
815 bus_release_resources(dev, ti_gpio_mem_spec,
816 sc->sc_mem_res);
813 ti_gpio_detach(dev);
817 return (err);
818 }
819 }
820 }
821
822 /* Finish of the probe call */
823 device_add_child(dev, "gpioc", -1);
824 device_add_child(dev, "gpiobus", -1);

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847
848 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
849
850 /* Disable all interrupts */
851 for (i = 0; i < ti_max_gpio_banks(); i++) {
852 if (sc->sc_mem_res[i] != NULL)
853 ti_gpio_intr_clr(sc, i, 0xffffffff);
854 }
814 return (err);
815 }
816 }
817 }
818
819 /* Finish of the probe call */
820 device_add_child(dev, "gpioc", -1);
821 device_add_child(dev, "gpiobus", -1);

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844
845 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
846
847 /* Disable all interrupts */
848 for (i = 0; i < ti_max_gpio_banks(); i++) {
849 if (sc->sc_mem_res[i] != NULL)
850 ti_gpio_intr_clr(sc, i, 0xffffffff);
851 }
855
856 bus_generic_detach(dev);
852 bus_generic_detach(dev);
857
858 free(sc->sc_events, M_DEVBUF);
859 free(sc->sc_irq_polarity, M_DEVBUF);
860 free(sc->sc_irq_trigger, M_DEVBUF);
861
853 if (sc->sc_events)
854 free(sc->sc_events, M_DEVBUF);
855 if (sc->sc_irq_polarity)
856 free(sc->sc_irq_polarity, M_DEVBUF);
857 if (sc->sc_irq_trigger)
858 free(sc->sc_irq_trigger, M_DEVBUF);
862 /* Release the memory and IRQ resources. */
863 ti_gpio_detach_intr(dev);
864 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
865 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
859 /* Release the memory and IRQ resources. */
860 ti_gpio_detach_intr(dev);
861 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
862 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
866
867 TI_GPIO_LOCK_DESTROY(sc);
868
869 return (0);
870}
871
872static uint32_t
873ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq)
874{

--- 224 unchanged lines hidden --- 		863 TI_GPIO_LOCK_DESTROY(sc);
864
865 return (0);
866}
867
868static uint32_t
869ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq)
870{

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