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timer.c (262534) timer.c (294416)
1/*-
2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
4 * All rights reserved.
5 *
6 * Adapted to Marvell SoC by Semihalf.
7 *
8 * Redistribution and use in source and binary forms, with or without

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
4 * All rights reserved.
5 *
6 * Adapted to Marvell SoC by Semihalf.
7 *
8 * Redistribution and use in source and binary forms, with or without

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/arm/mv/timer.c 262534 2014-02-26 22:06:10Z ian $");
32__FBSDID("$FreeBSD: head/sys/arm/mv/timer.c 294416 2016-01-20 13:14:36Z zbb $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/malloc.h>
40#include <sys/rman.h>

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49#include <arm/mv/mvvar.h>
50
51#include <dev/ofw/ofw_bus.h>
52#include <dev/ofw/ofw_bus_subr.h>
53
54#define INITIAL_TIMECOUNTER (0xffffffff)
55#define MAX_WATCHDOG_TICKS (0xffffffff)
56
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/malloc.h>
40#include <sys/rman.h>

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49#include <arm/mv/mvvar.h>
50
51#include <dev/ofw/ofw_bus.h>
52#include <dev/ofw/ofw_bus_subr.h>
53
54#define INITIAL_TIMECOUNTER (0xffffffff)
55#define MAX_WATCHDOG_TICKS (0xffffffff)
56
57#if defined(SOC_MV_ARMADAXP)
57#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
58#define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
59#else
60#define MV_CLOCK_SRC get_tclk()
61#endif
62
63struct mv_timer_softc {
64 struct resource * timer_res[2];
65 bus_space_tag_t timer_bst;

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119}
120
121static int
122mv_timer_attach(device_t dev)
123{
124 int error;
125 void *ihl;
126 struct mv_timer_softc *sc;
58#define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
59#else
60#define MV_CLOCK_SRC get_tclk()
61#endif
62
63struct mv_timer_softc {
64 struct resource * timer_res[2];
65 bus_space_tag_t timer_bst;

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119}
120
121static int
122mv_timer_attach(device_t dev)
123{
124 int error;
125 void *ihl;
126 struct mv_timer_softc *sc;
127#if !defined(SOC_MV_ARMADAXP)
127#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
128 uint32_t irq_cause, irq_mask;
129#endif
130
131 if (timer_softc != NULL)
132 return (ENXIO);
133
134 sc = (struct mv_timer_softc *)device_get_softc(dev);
135 timer_softc = sc;

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150 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
151 mv_hardclock, NULL, sc, &ihl) != 0) {
152 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
153 device_printf(dev, "Could not setup interrupt.\n");
154 return (ENXIO);
155 }
156
157 mv_setup_timers();
128 uint32_t irq_cause, irq_mask;
129#endif
130
131 if (timer_softc != NULL)
132 return (ENXIO);
133
134 sc = (struct mv_timer_softc *)device_get_softc(dev);
135 timer_softc = sc;

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150 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
151 mv_hardclock, NULL, sc, &ihl) != 0) {
152 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
153 device_printf(dev, "Could not setup interrupt.\n");
154 return (ENXIO);
155 }
156
157 mv_setup_timers();
158#if !defined(SOC_MV_ARMADAXP)
158#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
159 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
160 irq_cause &= IRQ_TIMER0_CLR;
161
162 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
163 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
164 irq_mask |= IRQ_TIMER0_MASK;
165 irq_mask &= ~IRQ_TIMER1_MASK;
166 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);

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289 bus_space_write_4(timer_softc->timer_bst,
290 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
291}
292
293static void
294mv_watchdog_enable(void)
295{
296 uint32_t val, irq_cause;
159 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
160 irq_cause &= IRQ_TIMER0_CLR;
161
162 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
163 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
164 irq_mask |= IRQ_TIMER0_MASK;
165 irq_mask &= ~IRQ_TIMER1_MASK;
166 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);

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289 bus_space_write_4(timer_softc->timer_bst,
290 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
291}
292
293static void
294mv_watchdog_enable(void)
295{
296 uint32_t val, irq_cause;
297#if !defined(SOC_MV_ARMADAXP)
297#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
298 uint32_t irq_mask;
299#endif
300
301 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
302 irq_cause &= IRQ_TIMER_WD_CLR;
303 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
304
298 uint32_t irq_mask;
299#endif
300
301 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
302 irq_cause &= IRQ_TIMER_WD_CLR;
303 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
304
305#if defined(SOC_MV_ARMADAXP)
305#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
306 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
307 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
308 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
309#else
310 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
311 irq_mask |= IRQ_TIMER_WD_MASK;
312 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
313
314 val = read_cpu_ctrl(RSTOUTn_MASK);
315 val |= WD_RST_OUT_EN;
316 write_cpu_ctrl(RSTOUTn_MASK, val);
317#endif
318
319 val = mv_get_timer_control();
320 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
306 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
307 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
308 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
309#else
310 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
311 irq_mask |= IRQ_TIMER_WD_MASK;
312 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
313
314 val = read_cpu_ctrl(RSTOUTn_MASK);
315 val |= WD_RST_OUT_EN;
316 write_cpu_ctrl(RSTOUTn_MASK, val);
317#endif
318
319 val = mv_get_timer_control();
320 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
321#if defined(SOC_MV_ARMADAXP)
321#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
322 val |= CPU_TIMER_WD_25MHZ_EN;
323#endif
324 mv_set_timer_control(val);
325}
326
327static void
328mv_watchdog_disable(void)
329{
330 uint32_t val, irq_cause;
322 val |= CPU_TIMER_WD_25MHZ_EN;
323#endif
324 mv_set_timer_control(val);
325}
326
327static void
328mv_watchdog_disable(void)
329{
330 uint32_t val, irq_cause;
331#if !defined(SOC_MV_ARMADAXP)
331#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
332 uint32_t irq_mask;
333#endif
334
335 val = mv_get_timer_control();
336 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
337 mv_set_timer_control(val);
338
332 uint32_t irq_mask;
333#endif
334
335 val = mv_get_timer_control();
336 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
337 mv_set_timer_control(val);
338
339#if defined(SOC_MV_ARMADAXP)
339#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
340 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
341 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
342 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
343#else
344 val = read_cpu_ctrl(RSTOUTn_MASK);
345 val &= ~WD_RST_OUT_EN;
346 write_cpu_ctrl(RSTOUTn_MASK, val);
347

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433{
434 uint32_t val;
435
436 mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
437 mv_set_timer(1, INITIAL_TIMECOUNTER);
438 val = mv_get_timer_control();
439 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
440 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
340 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
341 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
342 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
343#else
344 val = read_cpu_ctrl(RSTOUTn_MASK);
345 val &= ~WD_RST_OUT_EN;
346 write_cpu_ctrl(RSTOUTn_MASK, val);
347

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433{
434 uint32_t val;
435
436 mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
437 mv_set_timer(1, INITIAL_TIMECOUNTER);
438 val = mv_get_timer_control();
439 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
440 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
441#if defined(SOC_MV_ARMADAXP)
441#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
442 /* Enable 25MHz mode */
443 val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
444#endif
445 mv_set_timer_control(val);
446 timers_initialized = 1;
447}
442 /* Enable 25MHz mode */
443 val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
444#endif
445 mv_set_timer_control(val);
446 timers_initialized = 1;
447}