| db88f5xxx.c (185089) | db88f5xxx.c (186909) |
|---|---|
| 1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 16 unchanged lines hidden (view full) --- 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> | 1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 16 unchanged lines hidden (view full) --- 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> |
| 33__FBSDID("$FreeBSD: head/sys/arm/mv/orion/db88f5xxx.c 185089 2008-11-19 11:30:44Z raj $"); | 33__FBSDID("$FreeBSD: head/sys/arm/mv/orion/db88f5xxx.c 186909 2009-01-08 18:31:43Z raj $"); |
| 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39 40#include <vm/vm.h> 41#include <vm/pmap.h> 42 | 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39 40#include <vm/vm.h> 41#include <vm/pmap.h> 42 |
| 43#include <machine/bus.h> |
|
| 43#include <machine/pte.h> 44#include <machine/pmap.h> 45#include <machine/vmparam.h> 46 47#include <arm/mv/mvreg.h> 48#include <arm/mv/mvvar.h> 49 50/* --- 90 unchanged lines hidden (view full) --- 141 142 /* 143 * XXX This isn't the right place to setup GPIO, but it makes sure 144 * that PCI works on 5XXX targets where U-Boot doesn't set up the GPIO 145 * correctly to handle PCI IRQs (e.g., on 5182). This code will go 146 * away once we set up GPIO in a generic way in a proper place (TBD). 147 */ 148 if (irq >= 0) | 44#include <machine/pte.h> 45#include <machine/pmap.h> 46#include <machine/vmparam.h> 47 48#include <arm/mv/mvreg.h> 49#include <arm/mv/mvvar.h> 50 51/* --- 90 unchanged lines hidden (view full) --- 142 143 /* 144 * XXX This isn't the right place to setup GPIO, but it makes sure 145 * that PCI works on 5XXX targets where U-Boot doesn't set up the GPIO 146 * correctly to handle PCI IRQs (e.g., on 5182). This code will go 147 * away once we set up GPIO in a generic way in a proper place (TBD). 148 */ 149 if (irq >= 0) |
| 149 mv_gpio_configure(IRQ2GPIO(irq), MV_GPIO_POLARITY | | 150 mv_gpio_configure(IRQ2GPIO(irq), MV_GPIO_POLAR_LOW | |
| 150 MV_GPIO_LEVEL, ~0u); 151 152 return (irq); 153} 154 | 151 MV_GPIO_LEVEL, ~0u); 152 153 return (irq); 154} 155 |
| 156/* 157 * mv_gpio_config row structure: 158 * <GPIO number>, <GPIO flags>, <GPIO mode> 159 * 160 * - GPIO pin number (less than zero marks end of table) 161 * - GPIO flags: 162 * MV_GPIO_BLINK 163 * MV_GPIO_POLAR_LOW 164 * MV_GPIO_EDGE 165 * MV_GPIO_LEVEL 166 * - GPIO mode: 167 * 1 - Output, set to HIGH. 168 * 0 - Output, set to LOW. 169 * -1 - Input. 170 */ 171 172/* GPIO Configuration for DB-88F5281 */ 173const struct gpio_config mv_gpio_config[] = { 174 { 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 175 { 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 176 { -1, -1, -1 } 177}; 178 179#if 0 180/* GPIO Configuration for DB-88F5182 */ 181const struct gpio_config mv_gpio_config[] = { 182 { 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 183 { 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 184 { -1, -1, -1 } 185}; 186#endif 187 |
|
| 155int 156platform_pmap_init(void) 157{ 158 159 pmap_bootstrap_lastaddr = MV_BASE - ARM_NOCACHE_KVA_SIZE; 160 pmap_devmap_bootstrap_table = &pmap_devmap[0]; 161 162 return (0); 163} 164 | 188int 189platform_pmap_init(void) 190{ 191 192 pmap_bootstrap_lastaddr = MV_BASE - ARM_NOCACHE_KVA_SIZE; 193 pmap_devmap_bootstrap_table = &pmap_devmap[0]; 194 195 return (0); 196} 197 |
| 198void 199platform_mpp_init(void) 200{ 201 202 /* 203 * MPP configuration for DB-88F5281 204 * 205 * MPP[2]: PCI_REQn[3] 206 * MPP[3]: PCI_GNTn[3] 207 * MPP[4]: PCI_REQn[4] 208 * MPP[5]: PCI_GNTn[4] 209 * MPP[6]: <UNKNOWN> 210 * MPP[7]: <UNKNOWN> 211 * MPP[8]: <UNKNOWN> 212 * MPP[9]: <UNKNOWN> 213 * MPP[14]: NAND Flash REn[2] 214 * MPP[15]: NAND Flash WEn[2] 215 * MPP[16]: UA1_RXD 216 * MPP[17]: UA1_TXD 217 * MPP[18]: UA1_CTS 218 * MPP[19]: UA1_RTS 219 * 220 * Others: GPIO 221 * 222 * <UNKNOWN> entries are not documented, not on the schematics etc. 223 */ 224 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x33222203); 225 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x44000033); 226 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x00000000); 227 228#if 0 229 /* 230 * MPP configuration for DB-88F5182 231 * 232 * MPP[2]: PCI_REQn[3] 233 * MPP[3]: PCI_GNTn[3] 234 * MPP[4]: PCI_REQn[4] 235 * MPP[5]: PCI_GNTn[4] 236 * MPP[6]: SATA0_ACT 237 * MPP[7]: SATA1_ACT 238 * MPP[12]: SATA0_PRESENT 239 * MPP[13]: SATA1_PRESENT 240 * MPP[14]: NAND_FLASH_REn[2] 241 * MPP[15]: NAND_FLASH_WEn[2] 242 * MPP[16]: UA1_RXD 243 * MPP[17]: UA1_TXD 244 * MPP[18]: UA1_CTS 245 * MPP[19]: UA1_RTS 246 * 247 * Others: GPIO 248 */ 249 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x55222203); 250 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x44550000); 251 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x00000000); 252#endif 253} 254 |
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| 165static void 166platform_identify(void *dummy) 167{ 168 169 soc_identify(); 170 171 /* 172 * XXX Board identification e.g. read out from FPGA or similar should 173 * go here 174 */ 175} 176SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL); | 255static void 256platform_identify(void *dummy) 257{ 258 259 soc_identify(); 260 261 /* 262 * XXX Board identification e.g. read out from FPGA or similar should 263 * go here 264 */ 265} 266SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL); |
| 177 178/* 179 * TODO routine setting GPIO/MPP pins 180 */ | |