1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/mv/orion/db88f5xxx.c 185089 2008-11-19 11:30:44Z raj $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39
40#include <vm/vm.h>
41#include <vm/pmap.h>
42
43#include <machine/pte.h>
44#include <machine/pmap.h>
45#include <machine/vmparam.h>
46
47#include <arm/mv/mvreg.h>
48#include <arm/mv/mvvar.h>
49
50/*
51 * Virtual address space layout:
52 * -----------------------------
53 * 0x0000_0000 - 0xbfff_ffff : user process
54 *
55 * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
56 * : structures, ARM stacks etc.)
57 * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
58 * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
59 * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
60 * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
61 * 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB)
62 * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
63 * 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB)
64 * 0xf930_0000 - 0xfffe_ffff : unused (~108MB)
65 * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
66 * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
67 * 0xffff_2000 - 0xffff_ffff : unused (~55KB)
68 */
69
70const struct pmap_devmap *pmap_devmap_bootstrap_table;
71vm_offset_t pmap_bootstrap_lastaddr;
72int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
73
74/* Static device mappings. */
75static const struct pmap_devmap pmap_devmap[] = {
76 /*
77 * Map the on-board devices VA == PA so that we can access them
78 * with the MMU on or off.
79 */
80 { /* SoC integrated peripherals registers range */
81 MV_BASE,
82 MV_PHYS_BASE,
83 MV_SIZE,
84 VM_PROT_READ | VM_PROT_WRITE,
85 PTE_NOCACHE,
86 },
87 { /* PCIE I/O */
88 MV_PCIE_IO_BASE,
89 MV_PCIE_IO_PHYS_BASE,
90 MV_PCIE_IO_SIZE,
91 VM_PROT_READ | VM_PROT_WRITE,
92 PTE_NOCACHE,
93 },
94 { /* PCIE Memory */
95 MV_PCIE_MEM_BASE,
96 MV_PCIE_MEM_PHYS_BASE,
97 MV_PCIE_MEM_SIZE,
98 VM_PROT_READ | VM_PROT_WRITE,
99 PTE_NOCACHE,
100 },
101 { /* PCI I/O */
102 MV_PCI_IO_BASE,
103 MV_PCI_IO_PHYS_BASE,
104 MV_PCI_IO_SIZE,
105 VM_PROT_READ | VM_PROT_WRITE,
106 PTE_NOCACHE,
107 },
108 { /* PCI Memory */
109 MV_PCI_MEM_BASE,
110 MV_PCI_MEM_PHYS_BASE,
111 MV_PCI_MEM_SIZE,
112 VM_PROT_READ | VM_PROT_WRITE,
113 PTE_NOCACHE,
114 },
115 { /* 7-seg LED */
116 MV_DEV_CS0_BASE,
117 MV_DEV_CS0_PHYS_BASE,
118 MV_DEV_CS0_SIZE,
119 VM_PROT_READ | VM_PROT_WRITE,
120 PTE_NOCACHE,
121 },
122 { 0, 0, 0, 0, 0, }
123};
124
125int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin)
126{
127 int irq;
128
129 switch (slot) {
130 case 7:
131 irq = GPIO2IRQ(12); /* GPIO 0 for DB-88F5182 */
132 break; /* GPIO 12 for DB-88F5281 */
133 case 8:
134 case 9:
135 irq = GPIO2IRQ(13); /* GPIO 1 for DB-88F5182 */
136 break; /* GPIO 13 for DB-88F5281 */
137 default:
138 irq = -1;
139 break;
140 };
141
142 /*
143 * XXX This isn't the right place to setup GPIO, but it makes sure
144 * that PCI works on 5XXX targets where U-Boot doesn't set up the GPIO
145 * correctly to handle PCI IRQs (e.g., on 5182). This code will go
146 * away once we set up GPIO in a generic way in a proper place (TBD).
147 */
148 if (irq >= 0)
149 mv_gpio_configure(IRQ2GPIO(irq), MV_GPIO_POLARITY |
150 MV_GPIO_LEVEL, ~0u);
151
152 return (irq);
153}
154
155int
156platform_pmap_init(void)
157{
158
159 pmap_bootstrap_lastaddr = MV_BASE - ARM_NOCACHE_KVA_SIZE;
160 pmap_devmap_bootstrap_table = &pmap_devmap[0];
161
162 return (0);
163}
164
165static void
166platform_identify(void *dummy)
167{
168
169 soc_identify();
170
171 /*
172 * XXX Board identification e.g. read out from FPGA or similar should
173 * go here
174 */
175}
176SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL);
177
178/*
179 * TODO routine setting GPIO/MPP pins
180 */
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/mv/orion/db88f5xxx.c 185089 2008-11-19 11:30:44Z raj $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39
40#include <vm/vm.h>
41#include <vm/pmap.h>
42
43#include <machine/pte.h>
44#include <machine/pmap.h>
45#include <machine/vmparam.h>
46
47#include <arm/mv/mvreg.h>
48#include <arm/mv/mvvar.h>
49
50/*
51 * Virtual address space layout:
52 * -----------------------------
53 * 0x0000_0000 - 0xbfff_ffff : user process
54 *
55 * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
56 * : structures, ARM stacks etc.)
57 * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
58 * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
59 * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
60 * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
61 * 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB)
62 * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
63 * 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB)
64 * 0xf930_0000 - 0xfffe_ffff : unused (~108MB)
65 * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
66 * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
67 * 0xffff_2000 - 0xffff_ffff : unused (~55KB)
68 */
69
70const struct pmap_devmap *pmap_devmap_bootstrap_table;
71vm_offset_t pmap_bootstrap_lastaddr;
72int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
73
74/* Static device mappings. */
75static const struct pmap_devmap pmap_devmap[] = {
76 /*
77 * Map the on-board devices VA == PA so that we can access them
78 * with the MMU on or off.
79 */
80 { /* SoC integrated peripherals registers range */
81 MV_BASE,
82 MV_PHYS_BASE,
83 MV_SIZE,
84 VM_PROT_READ | VM_PROT_WRITE,
85 PTE_NOCACHE,
86 },
87 { /* PCIE I/O */
88 MV_PCIE_IO_BASE,
89 MV_PCIE_IO_PHYS_BASE,
90 MV_PCIE_IO_SIZE,
91 VM_PROT_READ | VM_PROT_WRITE,
92 PTE_NOCACHE,
93 },
94 { /* PCIE Memory */
95 MV_PCIE_MEM_BASE,
96 MV_PCIE_MEM_PHYS_BASE,
97 MV_PCIE_MEM_SIZE,
98 VM_PROT_READ | VM_PROT_WRITE,
99 PTE_NOCACHE,
100 },
101 { /* PCI I/O */
102 MV_PCI_IO_BASE,
103 MV_PCI_IO_PHYS_BASE,
104 MV_PCI_IO_SIZE,
105 VM_PROT_READ | VM_PROT_WRITE,
106 PTE_NOCACHE,
107 },
108 { /* PCI Memory */
109 MV_PCI_MEM_BASE,
110 MV_PCI_MEM_PHYS_BASE,
111 MV_PCI_MEM_SIZE,
112 VM_PROT_READ | VM_PROT_WRITE,
113 PTE_NOCACHE,
114 },
115 { /* 7-seg LED */
116 MV_DEV_CS0_BASE,
117 MV_DEV_CS0_PHYS_BASE,
118 MV_DEV_CS0_SIZE,
119 VM_PROT_READ | VM_PROT_WRITE,
120 PTE_NOCACHE,
121 },
122 { 0, 0, 0, 0, 0, }
123};
124
125int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin)
126{
127 int irq;
128
129 switch (slot) {
130 case 7:
131 irq = GPIO2IRQ(12); /* GPIO 0 for DB-88F5182 */
132 break; /* GPIO 12 for DB-88F5281 */
133 case 8:
134 case 9:
135 irq = GPIO2IRQ(13); /* GPIO 1 for DB-88F5182 */
136 break; /* GPIO 13 for DB-88F5281 */
137 default:
138 irq = -1;
139 break;
140 };
141
142 /*
143 * XXX This isn't the right place to setup GPIO, but it makes sure
144 * that PCI works on 5XXX targets where U-Boot doesn't set up the GPIO
145 * correctly to handle PCI IRQs (e.g., on 5182). This code will go
146 * away once we set up GPIO in a generic way in a proper place (TBD).
147 */
148 if (irq >= 0)
149 mv_gpio_configure(IRQ2GPIO(irq), MV_GPIO_POLARITY |
150 MV_GPIO_LEVEL, ~0u);
151
152 return (irq);
153}
154
155int
156platform_pmap_init(void)
157{
158
159 pmap_bootstrap_lastaddr = MV_BASE - ARM_NOCACHE_KVA_SIZE;
160 pmap_devmap_bootstrap_table = &pmap_devmap[0];
161
162 return (0);
163}
164
165static void
166platform_identify(void *dummy)
167{
168
169 soc_identify();
170
171 /*
172 * XXX Board identification e.g. read out from FPGA or similar should
173 * go here
174 */
175}
176SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL);
177
178/*
179 * TODO routine setting GPIO/MPP pins
180 */