1/*-
2 * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
3 * All rights reserved.
4 *
5 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project by
18 * Wasabi Systems, Inc.
19 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
20 * or promote products derived from this software without specific prior
21 * written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 *
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0var.h, rev 1
36 *
|
37 * $FreeBSD: head/sys/arm/mv/mvvar.h 185092 2008-11-19 11:57:16Z raj $
|
| 37 * $FreeBSD: head/sys/arm/mv/mvvar.h 186909 2009-01-08 18:31:43Z raj $ |
38 */
39
40#ifndef _MVVAR_H_
41#define _MVVAR_H_
42
43#include <sys/rman.h>
44
45#define MV_TYPE_PCI 0
46#define MV_TYPE_PCIE 1
47#define MV_TYPE_PCIE_AGGR_LANE 2 /* Additional PCIE lane to aggregate */
48
49struct obio_softc {
50 bus_space_tag_t obio_bst; /* bus space tag */
51 struct rman obio_mem;
52 struct rman obio_irq;
53 struct rman obio_gpio;
54};
55
56struct obio_device {
57 const char *od_name;
58 u_long od_base;
59 u_long od_size;
60 u_int od_irqs[7 + 1]; /* keep additional entry for -1 sentinel */
61 u_int od_gpio[2 + 1]; /* as above for IRQ */
62 u_int od_pwr_mask;
63 struct resource_list od_resources;
64};
65
66typedef int (*obio_get_irq_t)(u_int bus, u_int slot, u_int func, u_int pin);
67
68struct obio_pci {
69 int op_type;
70
71 bus_addr_t op_base;
72 u_long op_size;
73
74 /* Note IO/MEM regions are assumed VA == PA */
75 bus_addr_t op_io_base;
76 u_long op_io_size;
77 int op_io_win_target;
78 int op_io_win_attr;
79
80 bus_addr_t op_mem_base;
81 u_long op_mem_size;
82 int op_mem_win_target;
83 int op_mem_win_attr;
84
85 obio_get_irq_t op_get_irq; /* IRQ Mapping callback */
86 int op_irq; /* used if callback is NULL */
87};
88
|
89struct gpio_config {
90 int gc_gpio; /* GPIO number */
91 uint32_t gc_flags; /* GPIO flags */
92 int gc_output; /* GPIO output value */
93};
94 |
95struct decode_win {
96 int target; /* Mbus unit ID */
97 int attr; /* Attributes of the target interface */
98 vm_paddr_t base; /* Physical base addr */
99 uint32_t size;
100 int remap;
101};
102
103extern const struct obio_pci mv_pci_info[];
|
| 104extern const struct gpio_config mv_gpio_config[]; |
105extern bus_space_tag_t obio_tag;
106extern struct obio_device obio_devices[];
107extern const struct decode_win *cpu_wins;
108extern const struct decode_win *idma_wins;
|
| 109extern const struct decode_win *xor_wins; |
110extern int cpu_wins_no;
111extern int idma_wins_no;
|
| 112extern int xor_wins_no; |
113
114/* Function prototypes */
115int mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
116 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep);
117void mv_gpio_intr_mask(int pin);
118void mv_gpio_intr_unmask(int pin);
119int mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask);
120void mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable);
121uint8_t mv_gpio_in(uint32_t pin);
122
123int platform_pmap_init(void);
|
| 124void platform_mpp_init(void); |
125int soc_decode_win(void);
126void soc_id(uint32_t *dev, uint32_t *rev);
127void soc_identify(void);
128void soc_dump_decode_win(void);
129uint32_t soc_power_ctrl_get(uint32_t mask);
130
131int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
132 int remap);
133int decode_win_overlap(int, int, const struct decode_win *);
134int win_cpu_can_remap(int);
135
136void decode_win_idma_dump(void);
137void decode_win_idma_setup(void);
138int decode_win_idma_valid(void);
139
|
140void decode_win_xor_dump(void);
141void decode_win_xor_setup(void);
142int decode_win_xor_valid(void);
143 |
144int ddr_is_active(int i);
145uint32_t ddr_base(int i);
146uint32_t ddr_size(int i);
147uint32_t ddr_attr(int i);
148uint32_t ddr_target(int i);
149
150uint32_t cpu_extra_feat(void);
151uint32_t get_tclk(void);
152uint32_t read_cpu_ctrl(uint32_t);
153void write_cpu_ctrl(uint32_t, uint32_t);
154
155enum mbus_device_ivars {
156 MBUS_IVAR_BASE,
157};
158
159#define MBUS_ACCESSOR(var, ivar, type) \
160 __BUS_ACCESSOR(mbus, var, MBUS, ivar, type)
161
162MBUS_ACCESSOR(base, BASE, u_long)
163
164#undef MBUS_ACCESSOR
165
166#endif /* _MVVAR_H_ */
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