| mvreg.h (294430) | mvreg.h (294436) |
|---|---|
| 1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * | 1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * |
| 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 294430 2016-01-20 14:05:21Z zbb $ | 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 294436 2016-01-20 14:23:57Z zbb $ |
| 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#include <arm/mv/mvwin.h> 38 39#if defined(SOC_MV_DISCOVERY) --- 82 unchanged lines hidden (view full) --- 122#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 123#endif 124 125/* 126 * System reset 127 */ 128#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 129#define RSTOUTn_MASK 0x60 | 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#include <arm/mv/mvwin.h> 38 39#if defined(SOC_MV_DISCOVERY) --- 82 unchanged lines hidden (view full) --- 122#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 123#endif 124 125/* 126 * System reset 127 */ 128#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 129#define RSTOUTn_MASK 0x60 |
| 130#define RSTOUTn_MASK_WD 0x400 |
|
| 130#define SYSTEM_SOFT_RESET 0x64 131#define WD_RSTOUTn_MASK 0x4 132#define WD_GLOBAL_MASK 0x00000100 133#define WD_CPU0_MASK 0x00000001 134#define SOFT_RST_OUT_EN 0x00000001 135#define SYS_SOFT_RST 0x00000001 136#else 137#define RSTOUTn_MASK 0x8 --- 76 unchanged lines hidden (view full) --- 214 * Timers 215 */ 216#define CPU_TIMERS_BASE 0x300 217#define CPU_TIMER_CONTROL 0x0 218#define CPU_TIMER0_EN 0x00000001 219#define CPU_TIMER0_AUTO 0x00000002 220#define CPU_TIMER1_EN 0x00000004 221#define CPU_TIMER1_AUTO 0x00000008 | 131#define SYSTEM_SOFT_RESET 0x64 132#define WD_RSTOUTn_MASK 0x4 133#define WD_GLOBAL_MASK 0x00000100 134#define WD_CPU0_MASK 0x00000001 135#define SOFT_RST_OUT_EN 0x00000001 136#define SYS_SOFT_RST 0x00000001 137#else 138#define RSTOUTn_MASK 0x8 --- 76 unchanged lines hidden (view full) --- 215 * Timers 216 */ 217#define CPU_TIMERS_BASE 0x300 218#define CPU_TIMER_CONTROL 0x0 219#define CPU_TIMER0_EN 0x00000001 220#define CPU_TIMER0_AUTO 0x00000002 221#define CPU_TIMER1_EN 0x00000004 222#define CPU_TIMER1_AUTO 0x00000008 |
| 222#define CPU_TIMER_WD_EN 0x00000010 223#define CPU_TIMER_WD_AUTO 0x00000020 | 223#define CPU_TIMER2_EN 0x00000010 224#define CPU_TIMER2_AUTO 0x00000020 225#define CPU_TIMER_WD_EN 0x00000100 226#define CPU_TIMER_WD_AUTO 0x00000200 |
| 224/* 25MHz mode is Armada XP - specific */ 225#define CPU_TIMER_WD_25MHZ_EN 0x00000400 226#define CPU_TIMER0_25MHZ_EN 0x00000800 227#define CPU_TIMER1_25MHZ_EN 0x00001000 228#define CPU_TIMER0_REL 0x10 229#define CPU_TIMER0 0x14 230 231/* --- 238 unchanged lines hidden --- | 227/* 25MHz mode is Armada XP - specific */ 228#define CPU_TIMER_WD_25MHZ_EN 0x00000400 229#define CPU_TIMER0_25MHZ_EN 0x00000800 230#define CPU_TIMER1_25MHZ_EN 0x00001000 231#define CPU_TIMER0_REL 0x10 232#define CPU_TIMER0 0x14 233 234/* --- 238 unchanged lines hidden --- |