| mvreg.h (256760) | mvreg.h (294416) |
|---|---|
| 1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * | 1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * |
| 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 256760 2013-10-19 06:47:02Z rrs $ | 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 294416 2016-01-20 13:14:36Z zbb $ |
| 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#if defined(SOC_MV_DISCOVERY) 38#define IRQ_CAUSE_ERROR 0x0 39#define IRQ_CAUSE 0x4 --- 78 unchanged lines hidden (view full) --- 118#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 119#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 120#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 121#endif 122 123/* 124 * System reset 125 */ | 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#if defined(SOC_MV_DISCOVERY) 38#define IRQ_CAUSE_ERROR 0x0 39#define IRQ_CAUSE 0x4 --- 78 unchanged lines hidden (view full) --- 118#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 119#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 120#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 121#endif 122 123/* 124 * System reset 125 */ |
| 126#if defined(SOC_MV_ARMADAXP) | 126#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) |
| 127#define RSTOUTn_MASK 0x60 128#define SYSTEM_SOFT_RESET 0x64 129#define WD_RSTOUTn_MASK 0x4 130#define WD_GLOBAL_MASK 0x00000100 131#define WD_CPU0_MASK 0x00000001 132#define SOFT_RST_OUT_EN 0x00000001 133#define SYS_SOFT_RST 0x00000001 134#else --- 206 unchanged lines hidden (view full) --- 341#define IRQ2GPIO(irq) ((irq) - NIRQ) 342 343#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 344#define SAMPLE_AT_RESET 0x10 345#elif defined(SOC_MV_KIRKWOOD) 346#define SAMPLE_AT_RESET 0x30 347#elif defined(SOC_MV_FREY) 348#define SAMPLE_AT_RESET 0x100 | 127#define RSTOUTn_MASK 0x60 128#define SYSTEM_SOFT_RESET 0x64 129#define WD_RSTOUTn_MASK 0x4 130#define WD_GLOBAL_MASK 0x00000100 131#define WD_CPU0_MASK 0x00000001 132#define SOFT_RST_OUT_EN 0x00000001 133#define SYS_SOFT_RST 0x00000001 134#else --- 206 unchanged lines hidden (view full) --- 341#define IRQ2GPIO(irq) ((irq) - NIRQ) 342 343#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 344#define SAMPLE_AT_RESET 0x10 345#elif defined(SOC_MV_KIRKWOOD) 346#define SAMPLE_AT_RESET 0x30 347#elif defined(SOC_MV_FREY) 348#define SAMPLE_AT_RESET 0x100 |
| 349#elif defined(SOC_MV_ARMADA38X) 350#define SAMPLE_AT_RESET 0x400 |
|
| 349#endif 350#if defined(SOC_MV_DISCOVERY) 351#define SAMPLE_AT_RESET_LO 0x30 352#define SAMPLE_AT_RESET_HI 0x34 353#elif defined(SOC_MV_DOVE) 354#define SAMPLE_AT_RESET_LO 0x14 355#define SAMPLE_AT_RESET_HI 0x18 356#elif defined(SOC_MV_ARMADAXP) --- 8 unchanged lines hidden (view full) --- 365#define TCLK_MASK 0x00000300 366#define TCLK_SHIFT 0x08 367#elif defined(SOC_MV_DISCOVERY) 368#define TCLK_MASK 0x00000180 369#define TCLK_SHIFT 0x07 370#elif defined(SOC_MV_LOKIPLUS) 371#define TCLK_MASK 0x0000F000 372#define TCLK_SHIFT 0x0C | 351#endif 352#if defined(SOC_MV_DISCOVERY) 353#define SAMPLE_AT_RESET_LO 0x30 354#define SAMPLE_AT_RESET_HI 0x34 355#elif defined(SOC_MV_DOVE) 356#define SAMPLE_AT_RESET_LO 0x14 357#define SAMPLE_AT_RESET_HI 0x18 358#elif defined(SOC_MV_ARMADAXP) --- 8 unchanged lines hidden (view full) --- 367#define TCLK_MASK 0x00000300 368#define TCLK_SHIFT 0x08 369#elif defined(SOC_MV_DISCOVERY) 370#define TCLK_MASK 0x00000180 371#define TCLK_SHIFT 0x07 372#elif defined(SOC_MV_LOKIPLUS) 373#define TCLK_MASK 0x0000F000 374#define TCLK_SHIFT 0x0C |
| 375#elif defined(SOC_MV_ARMADA38X) 376#define TCLK_MASK 0x00008000 377#define TCLK_SHIFT 15 |
|
| 373#endif 374 375#define TCLK_100MHZ 100000000 376#define TCLK_125MHZ 125000000 377#define TCLK_133MHZ 133333333 378#define TCLK_150MHZ 150000000 379#define TCLK_166MHZ 166666667 380#define TCLK_200MHZ 200000000 --- 29 unchanged lines hidden (view full) --- 410 * Chip ID 411 */ 412#define MV_DEV_88F5181 0x5181 413#define MV_DEV_88F5182 0x5182 414#define MV_DEV_88F5281 0x5281 415#define MV_DEV_88F6281 0x6281 416#define MV_DEV_88F6282 0x6282 417#define MV_DEV_88F6781 0x6781 | 378#endif 379 380#define TCLK_100MHZ 100000000 381#define TCLK_125MHZ 125000000 382#define TCLK_133MHZ 133333333 383#define TCLK_150MHZ 150000000 384#define TCLK_166MHZ 166666667 385#define TCLK_200MHZ 200000000 --- 29 unchanged lines hidden (view full) --- 415 * Chip ID 416 */ 417#define MV_DEV_88F5181 0x5181 418#define MV_DEV_88F5182 0x5182 419#define MV_DEV_88F5281 0x5281 420#define MV_DEV_88F6281 0x6281 421#define MV_DEV_88F6282 0x6282 422#define MV_DEV_88F6781 0x6781 |
| 423#define MV_DEV_88F6828 0x6828 424#define MV_DEV_88F6820 0x6820 425#define MV_DEV_88F6810 0x6810 |
|
| 418#define MV_DEV_MV78100_Z0 0x6381 419#define MV_DEV_MV78100 0x7810 420#define MV_DEV_MV78130 0x7813 421#define MV_DEV_MV78160 0x7816 422#define MV_DEV_MV78230 0x7823 423#define MV_DEV_MV78260 0x7826 424#define MV_DEV_MV78460 0x7846 425#define MV_DEV_88RC8180 0x8180 --- 22 unchanged lines hidden --- | 426#define MV_DEV_MV78100_Z0 0x6381 427#define MV_DEV_MV78100 0x7810 428#define MV_DEV_MV78130 0x7813 429#define MV_DEV_MV78160 0x7816 430#define MV_DEV_MV78230 0x7823 431#define MV_DEV_MV78260 0x7826 432#define MV_DEV_MV78460 0x7846 433#define MV_DEV_88RC8180 0x8180 --- 22 unchanged lines hidden --- |