| mvreg.h (243580) | mvreg.h (251371) |
|---|---|
| 1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * | 1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * |
| 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 243580 2012-11-27 01:10:58Z marcel $ | 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 251371 2013-06-04 09:33:03Z gber $ |
| 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#if defined(SOC_MV_DISCOVERY) 38#define IRQ_CAUSE_ERROR 0x0 39#define IRQ_CAUSE 0x4 --- 170 unchanged lines hidden (view full) --- 210#define CPU_TIMERS_BASE 0x300 211#define CPU_TIMER_CONTROL 0x0 212#define CPU_TIMER0_EN 0x00000001 213#define CPU_TIMER0_AUTO 0x00000002 214#define CPU_TIMER1_EN 0x00000004 215#define CPU_TIMER1_AUTO 0x00000008 216#define CPU_TIMER_WD_EN 0x00000010 217#define CPU_TIMER_WD_AUTO 0x00000020 | 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#if defined(SOC_MV_DISCOVERY) 38#define IRQ_CAUSE_ERROR 0x0 39#define IRQ_CAUSE 0x4 --- 170 unchanged lines hidden (view full) --- 210#define CPU_TIMERS_BASE 0x300 211#define CPU_TIMER_CONTROL 0x0 212#define CPU_TIMER0_EN 0x00000001 213#define CPU_TIMER0_AUTO 0x00000002 214#define CPU_TIMER1_EN 0x00000004 215#define CPU_TIMER1_AUTO 0x00000008 216#define CPU_TIMER_WD_EN 0x00000010 217#define CPU_TIMER_WD_AUTO 0x00000020 |
| 218/* 25MHz mode is Armada XP - specific */ 219#define CPU_TIMER_WD_25MHZ_EN 0x00000400 220#define CPU_TIMER0_25MHZ_EN 0x00000800 221#define CPU_TIMER1_25MHZ_EN 0x00001000 |
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| 218#define CPU_TIMER0_REL 0x10 219#define CPU_TIMER0 0x14 220 221/* 222 * SATA 223 */ 224#define SATA_CHAN_NUM 2 225 --- 214 unchanged lines hidden --- | 222#define CPU_TIMER0_REL 0x10 223#define CPU_TIMER0 0x14 224 225/* 226 * SATA 227 */ 228#define SATA_CHAN_NUM 2 229 --- 214 unchanged lines hidden --- |