Deleted Added
sdiff udiff text old ( 186899 ) new ( 186909 )
full compact
mvreg.h (186899) mvreg.h (186909)
1/*-
2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 14 unchanged lines hidden (view full) ---

23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
1/*-
2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 14 unchanged lines hidden (view full) ---

23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: head/sys/arm/mv/mvreg.h 186899 2009-01-08 13:20:28Z raj $
31 * $FreeBSD: head/sys/arm/mv/mvreg.h 186909 2009-01-08 18:31:43Z raj $
32 */
33
34#ifndef _MVREG_H_
35#define _MVREG_H_
36
37#include <machine/intr.h>
38
39/*

--- 29 unchanged lines hidden (view full) ---

69#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */
70/* CS1: 32MB NOR FLASH */
71#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE)
72#define MV_DEV_CS1_SIZE (32 * 1024 * 1024)
73/* CS2: 32MB NAND FLASH */
74#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE)
75#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */
76
32 */
33
34#ifndef _MVREG_H_
35#define _MVREG_H_
36
37#include <machine/intr.h>
38
39/*

--- 29 unchanged lines hidden (view full) ---

69#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */
70/* CS1: 32MB NOR FLASH */
71#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE)
72#define MV_DEV_CS1_SIZE (32 * 1024 * 1024)
73/* CS2: 32MB NAND FLASH */
74#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE)
75#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */
76
77#define MV_CESA_SRAM_PHYS_BASE 0xFD000000
78#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */
79#define MV_CESA_SRAM_SIZE (1024 * 1024)
80
77/* XXX this is probably not robust against wraparounds... */
81/* XXX this is probably not robust against wraparounds... */
78#if ((MV_DEV_CS2_PHYS_BASE + MV_DEV_CS2_SIZE) > 0xFFFEFFFF)
82#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF)
79#error Devices memory layout overlaps reset vectors range!
80#endif
81
82/*
83 * Integrated SoC peripherals addresses
84 */
85#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
86#define MV_DDR_CADR_BASE (MV_BASE + 0x1500)

--- 11 unchanged lines hidden (view full) ---

98#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
99#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
100#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
101#define MV_IC_SIZE 0x3C
102#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300)
103#define MV_TIMERS_SIZE 0x30
104#define MV_PCI_BASE (MV_BASE + 0x30000)
105#define MV_PCI_SIZE 0x2000
83#error Devices memory layout overlaps reset vectors range!
84#endif
85
86/*
87 * Integrated SoC peripherals addresses
88 */
89#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
90#define MV_DDR_CADR_BASE (MV_BASE + 0x1500)

--- 11 unchanged lines hidden (view full) ---

102#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
103#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
104#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
105#define MV_IC_SIZE 0x3C
106#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300)
107#define MV_TIMERS_SIZE 0x30
108#define MV_PCI_BASE (MV_BASE + 0x30000)
109#define MV_PCI_SIZE 0x2000
110#if defined (SOC_MV_KIRKWOOD)
111#define MV_CESA_BASE (MV_BASE + 0x30000) /* CESA,PCI don't coexist */
112#elif defined (SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
113#define MV_CESA_BASE (MV_BASE + 0x90000)
114#endif
115#define MV_CESA_SIZE 0x10000
106#define MV_PCIE_BASE (MV_BASE + 0x40000)
107#define MV_PCIE_SIZE 0x2000
108
109#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000)
110#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000)
111#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000)
112#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000)
113#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000)

--- 9 unchanged lines hidden (view full) ---

123#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320)
124#define MV_IDMA_BASE (MV_BASE + 0x60000)
125#define MV_IDMA_SIZE 0x1000
126#define MV_XOR_BASE (MV_BASE + 0x60000)
127#define MV_XOR_SIZE 0x1000
128#define MV_ETH0_BASE (MV_BASE + 0x72000)
129#define MV_ETH1_BASE (MV_BASE + 0x76000)
130#define MV_ETH_SIZE 0x2000
116#define MV_PCIE_BASE (MV_BASE + 0x40000)
117#define MV_PCIE_SIZE 0x2000
118
119#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000)
120#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000)
121#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000)
122#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000)
123#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000)

--- 9 unchanged lines hidden (view full) ---

133#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320)
134#define MV_IDMA_BASE (MV_BASE + 0x60000)
135#define MV_IDMA_SIZE 0x1000
136#define MV_XOR_BASE (MV_BASE + 0x60000)
137#define MV_XOR_SIZE 0x1000
138#define MV_ETH0_BASE (MV_BASE + 0x72000)
139#define MV_ETH1_BASE (MV_BASE + 0x76000)
140#define MV_ETH_SIZE 0x2000
141#if defined(SOC_MV_ORION) || defined(SOC_MV_KIRKWOOD)
142#define MV_SATAHC_BASE (MV_BASE + 0x80000)
143#define MV_SATAHC_SIZE 0x6000
144#elif defined(SOC_MV_DISCOVERY)
145#define MV_SATAHC_BASE (MV_BASE + 0xA0000)
146#define MV_SATAHC_SIZE 0x6000
147#endif
131
132#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE
133
134/*
135 * Interrupt sources
136 */
137#if defined(SOC_MV_ORION)
138

--- 34 unchanged lines hidden (view full) ---

173#define MV_INT_GBETX 13 /* GbE0 transmit interrupt */
174#define MV_INT_GBEMISC 14 /* GbE0 misc. interrupt */
175#define MV_INT_GBE1SUM 15 /* GbE1 summary interrupt */
176#define MV_INT_GBE1RX 16 /* GbE1 receive interrupt */
177#define MV_INT_GBE1TX 17 /* GbE1 transmit interrupt */
178#define MV_INT_GBE1MISC 18 /* GbE1 misc. interrupt */
179#define MV_INT_USB_CI 19 /* USB Controller interrupt */
180#define MV_INT_SATA 21 /* Serial-ATA Interrupt */
148
149#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE
150
151/*
152 * Interrupt sources
153 */
154#if defined(SOC_MV_ORION)
155

--- 34 unchanged lines hidden (view full) ---

190#define MV_INT_GBETX 13 /* GbE0 transmit interrupt */
191#define MV_INT_GBEMISC 14 /* GbE0 misc. interrupt */
192#define MV_INT_GBE1SUM 15 /* GbE1 summary interrupt */
193#define MV_INT_GBE1RX 16 /* GbE1 receive interrupt */
194#define MV_INT_GBE1TX 17 /* GbE1 transmit interrupt */
195#define MV_INT_GBE1MISC 18 /* GbE1 misc. interrupt */
196#define MV_INT_USB_CI 19 /* USB Controller interrupt */
197#define MV_INT_SATA 21 /* Serial-ATA Interrupt */
198#define MV_INT_CESA 22 /* Security engine completion int. */
181#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */
182#define MV_INT_UART0 33 /* UART0 Interrupt */
183#define MV_INT_UART1 34
184#define MV_INT_GPIO7_0 35 /* GPIO[7:0] Interrupt */
185#define MV_INT_GPIO15_8 36 /* GPIO[15:8] Interrupt */
186#define MV_INT_GPIO23_16 37 /* GPIO[23:16] Interrupt */
187#define MV_INT_GPIO31_24 38 /* GPIO[31:24] Interrupt */
188#define MV_INT_GPIOHI7_0 39 /* GPIOHI[7:0] Interrupt */

--- 22 unchanged lines hidden (view full) ---

211#define MV_INT_TIMER3 11 /* Timer3 interrupt */
212#define MV_INT_UART0 12 /* UART0 interrupt */
213#define MV_INT_UART1 13 /* UART1 interrupt */
214#define MV_INT_UART2 14 /* UART2 interrupt */
215#define MV_INT_UART3 15 /* UART3 interrupt */
216#define MV_INT_USB0 16 /* USB0 interrupt */
217#define MV_INT_USB1 17 /* USB1 interrupt */
218#define MV_INT_USB2 18 /* USB2 interrupt */
199#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */
200#define MV_INT_UART0 33 /* UART0 Interrupt */
201#define MV_INT_UART1 34
202#define MV_INT_GPIO7_0 35 /* GPIO[7:0] Interrupt */
203#define MV_INT_GPIO15_8 36 /* GPIO[15:8] Interrupt */
204#define MV_INT_GPIO23_16 37 /* GPIO[23:16] Interrupt */
205#define MV_INT_GPIO31_24 38 /* GPIO[31:24] Interrupt */
206#define MV_INT_GPIOHI7_0 39 /* GPIOHI[7:0] Interrupt */

--- 22 unchanged lines hidden (view full) ---

229#define MV_INT_TIMER3 11 /* Timer3 interrupt */
230#define MV_INT_UART0 12 /* UART0 interrupt */
231#define MV_INT_UART1 13 /* UART1 interrupt */
232#define MV_INT_UART2 14 /* UART2 interrupt */
233#define MV_INT_UART3 15 /* UART3 interrupt */
234#define MV_INT_USB0 16 /* USB0 interrupt */
235#define MV_INT_USB1 17 /* USB1 interrupt */
236#define MV_INT_USB2 18 /* USB2 interrupt */
219#define MV_INT_CRYPTO 19 /* Crypto engine completion interrupt */
237#define MV_INT_CESA 19 /* Crypto engine completion interrupt */
220#define MV_INT_XOR0 22 /* XOR engine 0 completion interrupt */
221#define MV_INT_XOR1 23 /* XOR engine 1 completion interrupt */
222#define MV_INT_SATA 26 /* SATA interrupt */
223#define MV_INT_PEX00 32 /* PCI Express port 0.0 INTA/B/C/D */
224#define MV_INT_PEX01 33 /* PCI Express port 0.1 INTA/B/C/D */
225#define MV_INT_PEX02 34 /* PCI Express port 0.2 INTA/B/C/D */
226#define MV_INT_PEX03 35 /* PCI Express port 0.3 INTA/B/C/D */
227#define MV_INT_PEX10 36 /* PCI Express port 1.0 INTA/B/C/D */

--- 161 unchanged lines hidden (view full) ---

389#define GPIO_HI_INT_CAUSE 0x54
390#define GPIO_HI_INT_EDGE_MASK 0x58
391#define GPIO_HI_INT_LEV_MASK 0x5c
392
393#define GPIO(n) (1 << (n))
394#define MV_GPIO_MAX_NPINS 64
395
396#define MV_GPIO_BLINK 0x1
238#define MV_INT_XOR0 22 /* XOR engine 0 completion interrupt */
239#define MV_INT_XOR1 23 /* XOR engine 1 completion interrupt */
240#define MV_INT_SATA 26 /* SATA interrupt */
241#define MV_INT_PEX00 32 /* PCI Express port 0.0 INTA/B/C/D */
242#define MV_INT_PEX01 33 /* PCI Express port 0.1 INTA/B/C/D */
243#define MV_INT_PEX02 34 /* PCI Express port 0.2 INTA/B/C/D */
244#define MV_INT_PEX03 35 /* PCI Express port 0.3 INTA/B/C/D */
245#define MV_INT_PEX10 36 /* PCI Express port 1.0 INTA/B/C/D */

--- 161 unchanged lines hidden (view full) ---

407#define GPIO_HI_INT_CAUSE 0x54
408#define GPIO_HI_INT_EDGE_MASK 0x58
409#define GPIO_HI_INT_LEV_MASK 0x5c
410
411#define GPIO(n) (1 << (n))
412#define MV_GPIO_MAX_NPINS 64
413
414#define MV_GPIO_BLINK 0x1
397#define MV_GPIO_POLARITY 0x2
415#define MV_GPIO_POLAR_LOW 0x2
398#define MV_GPIO_EDGE 0x4
399#define MV_GPIO_LEVEL 0x8
400
401#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS)
402#define GPIO2IRQ(gpio) ((gpio) + NIRQ)
403#define IRQ2GPIO(irq) ((irq) - NIRQ)
404
405/*

--- 65 unchanged lines hidden (view full) ---

471#else
472#define MV_WIN_CPU_MAX 8
473#endif
474
475#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
476#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
477#define MV_WIN_DDR_MAX 4
478
416#define MV_GPIO_EDGE 0x4
417#define MV_GPIO_LEVEL 0x8
418
419#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS)
420#define GPIO2IRQ(gpio) ((gpio) + NIRQ)
421#define IRQ2GPIO(irq) ((irq) - NIRQ)
422
423/*

--- 65 unchanged lines hidden (view full) ---

489#else
490#define MV_WIN_CPU_MAX 8
491#endif
492
493#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
494#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
495#define MV_WIN_DDR_MAX 4
496
479#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x0)
480#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x4)
497#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04)
498#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00)
499#define MV_WIN_CESA_MAX 4
500
501#define MV_WIN_USB_CTRL(n, m) (0x10 * (n) + (m) * 0x1000 + 0x0)
502#define MV_WIN_USB_BASE(n, m) (0x10 * (n) + (m) * 0x1000 + 0x4)
481#define MV_WIN_USB_MAX 4
482
483#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
484#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
485#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
486#define MV_WIN_ETH_MAX 6
487
488#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00)
489#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04)
490#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60)
491#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70)
492#define MV_WIN_IDMA_MAX 8
493#define MV_IDMA_CHAN_MAX 4
494
503#define MV_WIN_USB_MAX 4
504
505#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
506#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
507#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
508#define MV_WIN_ETH_MAX 6
509
510#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00)
511#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04)
512#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60)
513#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70)
514#define MV_WIN_IDMA_MAX 8
515#define MV_IDMA_CHAN_MAX 4
516
517#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100)
518#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100)
519#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100)
520#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100)
521#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100)
522#define MV_WIN_XOR_MAX 8
523#define MV_XOR_CHAN_MAX 2
524#define MV_XOR_NON_REMAP 4
525
495#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
496 (n) + 1) + 0x1820)
497#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
498 (n) + 1) + 0x1824)
499#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \
500 (n) + 1) + 0x182C)
501#define MV_WIN_PCIE_MAX 6
502
503#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804)
504#define MV_PCIE_BAR_MAX 3
505
526#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
527 (n) + 1) + 0x1820)
528#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
529 (n) + 1) + 0x1824)
530#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \
531 (n) + 1) + 0x182C)
532#define MV_WIN_PCIE_MAX 6
533
534#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804)
535#define MV_PCIE_BAR_MAX 3
536
537#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30)
538#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
539#define MV_WIN_SATA_MAX 4
540
506#define WIN_REG_IDX_RD(pre,reg,off,base) \
507 static __inline uint32_t \
508 pre ## _ ## reg ## _read(int i) \
509 { \
510 return (bus_space_read_4(obio_tag, base, off(i))); \
511 }
512
541#define WIN_REG_IDX_RD(pre,reg,off,base) \
542 static __inline uint32_t \
543 pre ## _ ## reg ## _read(int i) \
544 { \
545 return (bus_space_read_4(obio_tag, base, off(i))); \
546 }
547
548#define WIN_REG_IDX_RD2(pre,reg,off,base) \
549 static __inline uint32_t \
550 pre ## _ ## reg ## _read(int i, int j) \
551 { \
552 return (bus_space_read_4(obio_tag, base, off(i, j))); \
553 } \
554
513#define WIN_REG_BASE_IDX_RD(pre,reg,off) \
514 static __inline uint32_t \
515 pre ## _ ## reg ## _read(uint32_t base, int i) \
516 { \
517 return (bus_space_read_4(obio_tag, base, off(i))); \
518 }
519
520#define WIN_REG_IDX_WR(pre,reg,off,base) \
521 static __inline void \
522 pre ## _ ## reg ## _write(int i, uint32_t val) \
523 { \
524 bus_space_write_4(obio_tag, base, off(i), val); \
525 }
526
555#define WIN_REG_BASE_IDX_RD(pre,reg,off) \
556 static __inline uint32_t \
557 pre ## _ ## reg ## _read(uint32_t base, int i) \
558 { \
559 return (bus_space_read_4(obio_tag, base, off(i))); \
560 }
561
562#define WIN_REG_IDX_WR(pre,reg,off,base) \
563 static __inline void \
564 pre ## _ ## reg ## _write(int i, uint32_t val) \
565 { \
566 bus_space_write_4(obio_tag, base, off(i), val); \
567 }
568
569#define WIN_REG_IDX_WR2(pre,reg,off,base) \
570 static __inline void \
571 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \
572 { \
573 bus_space_write_4(obio_tag, base, off(i, j), val); \
574 }
575
527#define WIN_REG_BASE_IDX_WR(pre,reg,off) \
528 static __inline void \
529 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \
530 { \
531 bus_space_write_4(obio_tag, base, off(i), val); \
532 }
533
534#define WIN_REG_RD(pre,reg,off,base) \

--- 28 unchanged lines hidden --- 		576#define WIN_REG_BASE_IDX_WR(pre,reg,off) \
577 static __inline void \
578 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \
579 { \
580 bus_space_write_4(obio_tag, base, off(i), val); \
581 }
582
583#define WIN_REG_RD(pre,reg,off,base) \

--- 28 unchanged lines hidden ---