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mv_common.c (186899) mv_common.c (186909)
1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 16 unchanged lines hidden (view full) ---

25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 16 unchanged lines hidden (view full) ---

25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/mv/common.c 186899 2009-01-08 13:20:28Z raj $");
33__FBSDID("$FreeBSD: head/sys/arm/mv/common.c 186909 2009-01-08 18:31:43Z raj $");
34
35#include <sys/systm.h>
36#include <sys/bus.h>
37
38#include <machine/bus.h>
39
40#include <arm/mv/mvreg.h>
41#include <arm/mv/mvvar.h>
42
43static int win_eth_can_remap(int i);
44
45static int decode_win_cpu_valid(void);
46static int decode_win_usb_valid(void);
47static int decode_win_eth_valid(void);
48static int decode_win_pcie_valid(void);
34
35#include <sys/systm.h>
36#include <sys/bus.h>
37
38#include <machine/bus.h>
39
40#include <arm/mv/mvreg.h>
41#include <arm/mv/mvvar.h>
42
43static int win_eth_can_remap(int i);
44
45static int decode_win_cpu_valid(void);
46static int decode_win_usb_valid(void);
47static int decode_win_eth_valid(void);
48static int decode_win_pcie_valid(void);
49static int decode_win_sata_valid(void);
50static int decode_win_cesa_valid(void);
49
50static void decode_win_cpu_setup(void);
51
52static void decode_win_cpu_setup(void);
51static void decode_win_usb_setup(uint32_t ctrl);
53static void decode_win_usb_setup(void);
52static void decode_win_eth_setup(uint32_t base);
53static void decode_win_pcie_setup(uint32_t base);
54static void decode_win_eth_setup(uint32_t base);
55static void decode_win_pcie_setup(uint32_t base);
56static void decode_win_sata_setup(void);
57static void decode_win_cesa_setup(void);
54
58
55static uint32_t dev, rev;
59static void decode_win_cesa_dump(void);
60static void decode_win_usb_dump(void);
61
56static uint32_t used_cpu_wins;
57
58uint32_t
59read_cpu_ctrl(uint32_t reg)
60{
61
62 return (bus_space_read_4(obio_tag, MV_CPU_CONTROL_BASE, reg));
63}

--- 12 unchanged lines hidden (view full) ---

76 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
77 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
78 while (1);
79}
80
81uint32_t
82cpu_extra_feat(void)
83{
62static uint32_t used_cpu_wins;
63
64uint32_t
65read_cpu_ctrl(uint32_t reg)
66{
67
68 return (bus_space_read_4(obio_tag, MV_CPU_CONTROL_BASE, reg));
69}

--- 12 unchanged lines hidden (view full) ---

82 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
83 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
84 while (1);
85}
86
87uint32_t
88cpu_extra_feat(void)
89{
90 uint32_t dev, rev;
84 uint32_t ef = 0;
85
86 soc_id(&dev, &rev);
87 if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100)
88 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
89 else if (dev == MV_DEV_88F5182 || dev == MV_DEV_88F5281)
90 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
91 else if (bootverbose)

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173 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
174
175 /* TODO add info on currently set endianess */
176}
177
178int
179soc_decode_win(void)
180{
91 uint32_t ef = 0;
92
93 soc_id(&dev, &rev);
94 if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100)
95 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
96 else if (dev == MV_DEV_88F5182 || dev == MV_DEV_88F5281)
97 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
98 else if (bootverbose)

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180 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
181
182 /* TODO add info on currently set endianess */
183}
184
185int
186soc_decode_win(void)
187{
188 uint32_t dev, rev;
181
182 /* Retrieve our ID: some windows facilities vary between SoC models */
183 soc_id(&dev, &rev);
184
185 if (decode_win_cpu_valid() != 1 || decode_win_usb_valid() != 1 ||
186 decode_win_eth_valid() != 1 || decode_win_idma_valid() != 1 ||
189
190 /* Retrieve our ID: some windows facilities vary between SoC models */
191 soc_id(&dev, &rev);
192
193 if (decode_win_cpu_valid() != 1 || decode_win_usb_valid() != 1 ||
194 decode_win_eth_valid() != 1 || decode_win_idma_valid() != 1 ||
187 decode_win_pcie_valid() != 1)
195 decode_win_pcie_valid() != 1 || decode_win_sata_valid() != 1 ||
196 decode_win_cesa_valid() != 1)
188 return(-1);
189
190 decode_win_cpu_setup();
197 return(-1);
198
199 decode_win_cpu_setup();
191 decode_win_usb_setup(MV_USB0_BASE);
200 decode_win_usb_setup();
192 decode_win_eth_setup(MV_ETH0_BASE);
193 if (dev == MV_DEV_MV78100)
194 decode_win_eth_setup(MV_ETH1_BASE);
201 decode_win_eth_setup(MV_ETH0_BASE);
202 if (dev == MV_DEV_MV78100)
203 decode_win_eth_setup(MV_ETH1_BASE);
204 if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100)
205 decode_win_cesa_setup();
195
196 decode_win_idma_setup();
206
207 decode_win_idma_setup();
208 decode_win_xor_setup();
197
198 if (dev == MV_DEV_MV78100) {
199 decode_win_pcie_setup(MV_PCIE00_BASE);
200 decode_win_pcie_setup(MV_PCIE01_BASE);
201 decode_win_pcie_setup(MV_PCIE02_BASE);
202 decode_win_pcie_setup(MV_PCIE03_BASE);
203 decode_win_pcie_setup(MV_PCIE10_BASE);
204 decode_win_pcie_setup(MV_PCIE11_BASE);
205 decode_win_pcie_setup(MV_PCIE12_BASE);
206 decode_win_pcie_setup(MV_PCIE13_BASE);
207 } else
208 decode_win_pcie_setup(MV_PCIE_BASE);
209
209
210 if (dev == MV_DEV_MV78100) {
211 decode_win_pcie_setup(MV_PCIE00_BASE);
212 decode_win_pcie_setup(MV_PCIE01_BASE);
213 decode_win_pcie_setup(MV_PCIE02_BASE);
214 decode_win_pcie_setup(MV_PCIE03_BASE);
215 decode_win_pcie_setup(MV_PCIE10_BASE);
216 decode_win_pcie_setup(MV_PCIE11_BASE);
217 decode_win_pcie_setup(MV_PCIE12_BASE);
218 decode_win_pcie_setup(MV_PCIE13_BASE);
219 } else
220 decode_win_pcie_setup(MV_PCIE_BASE);
221
210 /* TODO set up decode wins for SATA */
222 if (dev != MV_DEV_88F5281)
223 decode_win_sata_setup();
211
212 return (0);
213}
214
215/**************************************************************************
216 * Decode windows registers accessors
217 **************************************************************************/
218WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
219WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
220WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
221WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
222WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
223WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
224WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
225WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
226
227WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
228WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
229
224
225 return (0);
226}
227
228/**************************************************************************
229 * Decode windows registers accessors
230 **************************************************************************/
231WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
232WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
233WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
234WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
235WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
236WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
237WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
238WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
239
240WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
241WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
242
230WIN_REG_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
231WIN_REG_IDX_RD(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
232WIN_REG_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
233WIN_REG_IDX_WR(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
243WIN_REG_IDX_RD2(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
244WIN_REG_IDX_RD2(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
245WIN_REG_IDX_WR2(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
246WIN_REG_IDX_WR2(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
234
247
248WIN_REG_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL, MV_CESA_BASE)
249WIN_REG_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE, MV_CESA_BASE)
250WIN_REG_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL, MV_CESA_BASE)
251WIN_REG_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE, MV_CESA_BASE)
252
235WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
236WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
237WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
238WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
239WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
240WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
253WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
254WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
255WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
256WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
257WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
258WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
259
260WIN_REG_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE, MV_XOR_BASE)
261WIN_REG_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE, MV_XOR_BASE)
262WIN_REG_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP, MV_XOR_BASE)
263WIN_REG_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL, MV_XOR_BASE)
264WIN_REG_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE, MV_XOR_BASE)
265WIN_REG_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE, MV_XOR_BASE)
266WIN_REG_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP, MV_XOR_BASE)
267WIN_REG_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL, MV_XOR_BASE)
268
241WIN_REG_BASE_RD(win_eth, bare, 0x290)
242WIN_REG_BASE_RD(win_eth, epap, 0x294)
243WIN_REG_BASE_WR(win_eth, bare, 0x290)
244WIN_REG_BASE_WR(win_eth, epap, 0x294)
245
246WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
247WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
248WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);

--- 8 unchanged lines hidden (view full) ---

257WIN_REG_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
258WIN_REG_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
259WIN_REG_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
260WIN_REG_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
261WIN_REG_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
262WIN_REG_RD(win_idma, bare, 0xa80, MV_IDMA_BASE)
263WIN_REG_WR(win_idma, bare, 0xa80, MV_IDMA_BASE)
264
269WIN_REG_BASE_RD(win_eth, bare, 0x290)
270WIN_REG_BASE_RD(win_eth, epap, 0x294)
271WIN_REG_BASE_WR(win_eth, bare, 0x290)
272WIN_REG_BASE_WR(win_eth, epap, 0x294)
273
274WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
275WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
276WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);

--- 8 unchanged lines hidden (view full) ---

285WIN_REG_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
286WIN_REG_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
287WIN_REG_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
288WIN_REG_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
289WIN_REG_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
290WIN_REG_RD(win_idma, bare, 0xa80, MV_IDMA_BASE)
291WIN_REG_WR(win_idma, bare, 0xa80, MV_IDMA_BASE)
292
293WIN_REG_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL, MV_SATAHC_BASE);
294WIN_REG_IDX_RD(win_sata, br, MV_WIN_SATA_BASE, MV_SATAHC_BASE);
295WIN_REG_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL, MV_SATAHC_BASE);
296WIN_REG_IDX_WR(win_sata, br, MV_WIN_SATA_BASE, MV_SATAHC_BASE);
297
265/**************************************************************************
266 * Decode windows helper routines
267 **************************************************************************/
268void
269soc_dump_decode_win(void)
270{
298/**************************************************************************
299 * Decode windows helper routines
300 **************************************************************************/
301void
302soc_dump_decode_win(void)
303{
304 uint32_t dev, rev;
271 int i;
272
273 soc_id(&dev, &rev);
274
275 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
276 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
277 win_cpu_cr_read(i),
278 win_cpu_br_read(i));

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285 printf("\n");
286 }
287 printf("Internal regs base: 0x%08x\n",
288 bus_space_read_4(obio_tag, MV_INTREGS_BASE, 0));
289
290 for (i = 0; i < MV_WIN_DDR_MAX; i++)
291 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
292 ddr_br_read(i), ddr_sz_read(i));
305 int i;
306
307 soc_id(&dev, &rev);
308
309 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
310 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
311 win_cpu_cr_read(i),
312 win_cpu_br_read(i));

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319 printf("\n");
320 }
321 printf("Internal regs base: 0x%08x\n",
322 bus_space_read_4(obio_tag, MV_INTREGS_BASE, 0));
323
324 for (i = 0; i < MV_WIN_DDR_MAX; i++)
325 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
326 ddr_br_read(i), ddr_sz_read(i));
293
294 for (i = 0; i < MV_WIN_USB_MAX; i++)
295 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
296 win_usb_cr_read(i), win_usb_br_read(i));
297
298 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
299 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
300 win_eth_br_read(MV_ETH0_BASE, i),
301 win_eth_sz_read(MV_ETH0_BASE, i));
302
303 if (win_eth_can_remap(i))
304 printf(", ha 0x%08x",
305 win_eth_har_read(MV_ETH0_BASE, i));
306
307 printf("\n");
308 }
309 printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
310 win_eth_bare_read(MV_ETH0_BASE),
311 win_eth_epap_read(MV_ETH0_BASE));
312
313 decode_win_idma_dump();
327
328 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
329 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
330 win_eth_br_read(MV_ETH0_BASE, i),
331 win_eth_sz_read(MV_ETH0_BASE, i));
332
333 if (win_eth_can_remap(i))
334 printf(", ha 0x%08x",
335 win_eth_har_read(MV_ETH0_BASE, i));
336
337 printf("\n");
338 }
339 printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
340 win_eth_bare_read(MV_ETH0_BASE),
341 win_eth_epap_read(MV_ETH0_BASE));
342
343 decode_win_idma_dump();
344 decode_win_cesa_dump();
345 decode_win_usb_dump();
314 printf("\n");
315}
316
317/**************************************************************************
318 * CPU windows routines
319 **************************************************************************/
320int
321win_cpu_can_remap(int i)
322{
346 printf("\n");
347}
348
349/**************************************************************************
350 * CPU windows routines
351 **************************************************************************/
352int
353win_cpu_can_remap(int i)
354{
355 uint32_t dev, rev;
323
356
357 soc_id(&dev, &rev);
358
324 /* Depending on the SoC certain windows have remap capability */
325 if ((dev == MV_DEV_88F5182 && i < 2) ||
326 (dev == MV_DEV_88F5281 && i < 4) ||
327 (dev == MV_DEV_88F6281 && i < 4) ||
328 (dev == MV_DEV_MV78100 && i < 8))
329 return (1);
330
331 return (0);

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544 **************************************************************************/
545static int
546decode_win_usb_valid(void)
547{
548
549 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
550}
551
359 /* Depending on the SoC certain windows have remap capability */
360 if ((dev == MV_DEV_88F5182 && i < 2) ||
361 (dev == MV_DEV_88F5281 && i < 4) ||
362 (dev == MV_DEV_88F6281 && i < 4) ||
363 (dev == MV_DEV_MV78100 && i < 8))
364 return (1);
365
366 return (0);

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579 **************************************************************************/
580static int
581decode_win_usb_valid(void)
582{
583
584 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
585}
586
587static __inline int
588usb_max_ports(void)
589{
590 uint32_t dev, rev;
591
592 soc_id(&dev, &rev);
593 return (dev == MV_DEV_MV78100 ? 3 : 1);
594}
595
596static void
597decode_win_usb_dump(void)
598{
599 int i, p, m;
600
601 m = usb_max_ports();
602 for (p = 0; p < m; p++)
603 for (i = 0; i < MV_WIN_USB_MAX; i++)
604 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
605 win_usb_cr_read(i, p), win_usb_br_read(i, p));
606}
607
552/*
553 * Set USB decode windows.
554 */
555static void
608/*
609 * Set USB decode windows.
610 */
611static void
556decode_win_usb_setup(uint32_t ctrl)
612decode_win_usb_setup(void)
557{
558 uint32_t br, cr;
613{
614 uint32_t br, cr;
559 int i, j;
615 int i, j, p, m;
560
616
561 /* Disable and clear all USB windows */
562 for (i = 0; i < MV_WIN_USB_MAX; i++) {
563 win_usb_cr_write(i, 0);
564 win_usb_br_write(i, 0);
565 }
617 /* Disable and clear all USB windows for all ports */
618 m = usb_max_ports();
619 for (p = 0; p < m; p++) {
566
620
567 /* Only access to active DRAM banks is required */
568 for (i = 0; i < MV_WIN_DDR_MAX; i++)
569 if (ddr_is_active(i)) {
570 br = ddr_base(i);
571 /*
572 * XXX for 6281 we should handle Mbus write burst limit
573 * field in the ctrl reg
574 */
575 cr = (((ddr_size(i) - 1) & 0xffff0000) |
576 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1);
621 for (i = 0; i < MV_WIN_USB_MAX; i++) {
622 win_usb_cr_write(i, p, 0);
623 win_usb_br_write(i, p, 0);
624 }
577
625
578 /* Set the first free USB window */
579 for (j = 0; j < MV_WIN_USB_MAX; j++) {
580 if (win_usb_cr_read(j) & 0x1)
581 continue;
626 /* Only access to active DRAM banks is required */
627 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
628 if (ddr_is_active(i)) {
629 br = ddr_base(i);
630 /*
631 * XXX for 6281 we should handle Mbus write
632 * burst limit field in the ctrl reg
633 */
634 cr = (((ddr_size(i) - 1) & 0xffff0000) |
635 (ddr_attr(i) << 8) |
636 (ddr_target(i) << 4) | 1);
582
637
583 win_usb_br_write(j, br);
584 win_usb_cr_write(j, cr);
585 break;
638 /* Set the first free USB window */
639 for (j = 0; j < MV_WIN_USB_MAX; j++) {
640 if (win_usb_cr_read(j, p) & 0x1)
641 continue;
642
643 win_usb_br_write(j, p, br);
644 win_usb_cr_write(j, p, cr);
645 break;
646 }
586 }
587 }
647 }
648 }
649 }
588}
589
590/**************************************************************************
591 * ETH windows routines
592 **************************************************************************/
593
594static int
595win_eth_can_remap(int i)

--- 333 unchanged lines hidden (view full) ---

929 "0x%08x\n", i, s, b);
930 rv = 0;
931 continue;
932 }
933
934 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
935 if (j >= 0) {
936 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
650}
651
652/**************************************************************************
653 * ETH windows routines
654 **************************************************************************/
655
656static int
657win_eth_can_remap(int i)

--- 333 unchanged lines hidden (view full) ---

991 "0x%08x\n", i, s, b);
992 rv = 0;
993 continue;
994 }
995
996 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
997 if (j >= 0) {
998 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
937 "with " "#%d (0x%08x - 0x%08x)\n", i, b, e, j,
999 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
938 idma_wins[j].base,
939 idma_wins[j].base + idma_wins[j].size - 1);
940 rv = 0;
941 }
942 }
943
944 return (rv);
945}

--- 32 unchanged lines hidden (view full) ---

978{
979}
980
981void
982decode_win_idma_dump(void)
983{
984}
985#endif
1000 idma_wins[j].base,
1001 idma_wins[j].base + idma_wins[j].size - 1);
1002 rv = 0;
1003 }
1004 }
1005
1006 return (rv);
1007}

--- 32 unchanged lines hidden (view full) ---

1040{
1041}
1042
1043void
1044decode_win_idma_dump(void)
1045{
1046}
1047#endif
1048
1049/**************************************************************************
1050 * XOR windows routines
1051 **************************************************************************/
1052#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
1053static int
1054xor_ctrl_read(int i, int c, int e)
1055{
1056 uint32_t v;
1057 v = win_xor_ctrl_read(c, e);
1058 v &= (1 << i);
1059
1060 return (v >> i);
1061}
1062
1063static void
1064xor_ctrl_write(int i, int c, int e, int val)
1065{
1066 uint32_t v;
1067
1068 v = win_xor_ctrl_read(c, e);
1069 v &= ~(1 << i);
1070 v |= (val << i);
1071 win_xor_ctrl_write(c, e, v);
1072}
1073
1074/*
1075 * Set channel protection 'val' for window 'w' on channel 'c'
1076 */
1077
1078static void
1079xor_chan_write(int c, int e, int w, int val)
1080{
1081 uint32_t v;
1082
1083 v = win_xor_ctrl_read(c, e);
1084 v &= ~(0x3 << (w * 2 + 16));
1085 v |= (val << (w * 2 + 16));
1086 win_xor_ctrl_write(c, e, v);
1087}
1088
1089/*
1090 * Set protection 'val' on all channels for window 'w' on engine 'e'
1091 */
1092static void
1093xor_set_prot(int w, int e, int val)
1094{
1095 int c;
1096
1097 for (c = 0; c < MV_XOR_CHAN_MAX; c++)
1098 xor_chan_write(c, e, w, val);
1099}
1100
1101static int
1102win_xor_can_remap(int i)
1103{
1104
1105 /* XOR decode windows 0-3 have remap capability */
1106 if (i < 4)
1107 return (1);
1108
1109 return (0);
1110}
1111
1112static __inline int
1113xor_max_eng(void)
1114{
1115 uint32_t dev, rev;
1116
1117 soc_id(&dev, &rev);
1118 return ((dev == MV_DEV_88F6281) ? 2 :
1119 (dev == MV_DEV_MV78100) ? 1 : 0);
1120}
1121
1122static void
1123xor_active_dram(int c, int e, int *window)
1124{
1125 uint32_t br, sz;
1126 int i, m, w;
1127
1128 /*
1129 * Set up access to all active DRAM banks
1130 */
1131 m = xor_max_eng();
1132 for (i = 0; i < m; i++)
1133 if (ddr_is_active(i)) {
1134 br = ddr_base(i) | (ddr_attr(i) << 8) |
1135 ddr_target(i);
1136 sz = ((ddr_size(i) - 1) & 0xffff0000);
1137
1138 /* Place DDR entries in non-remapped windows */
1139 for (w = 0; w < MV_WIN_XOR_MAX; w++)
1140 if (win_xor_can_remap(w) != 1 &&
1141 (xor_ctrl_read(w, c, e) == 0) &&
1142 w > *window) {
1143 /* Configure window */
1144 win_xor_br_write(w, e, br);
1145 win_xor_sz_write(w, e, sz);
1146
1147 /* Set protection RW on all channels */
1148 xor_set_prot(w, e, 0x3);
1149
1150 /* Enable window */
1151 xor_ctrl_write(w, c, e, 1);
1152 (*window)++;
1153 break;
1154 }
1155 }
1156}
1157
1158void
1159decode_win_xor_setup(void)
1160{
1161 uint32_t br, sz;
1162 int i, j, z, e = 1, m, window;
1163
1164 /*
1165 * Disable and clear all XOR windows, revoke protection for all
1166 * channels
1167 */
1168 m = xor_max_eng();
1169 for (j = 0; j < m; j++, e--) {
1170
1171 /* Number of non-remaped windows */
1172 window = MV_XOR_NON_REMAP - 1;
1173
1174 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1175 win_xor_br_write(i, e, 0);
1176 win_xor_sz_write(i, e, 0);
1177 }
1178
1179 if (win_xor_can_remap(i) == 1)
1180 win_xor_har_write(i, e, 0);
1181
1182 for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
1183 win_xor_ctrl_write(i, e, 0);
1184 xor_active_dram(i, e, &window);
1185 }
1186
1187 /*
1188 * Remaining targets -- from a statically defined table
1189 */
1190 for (i = 0; i < xor_wins_no; i++)
1191 if (xor_wins[i].target > 0) {
1192 br = (xor_wins[i].base & 0xffff0000) |
1193 (xor_wins[i].attr << 8) |
1194 xor_wins[i].target;
1195 sz = ((xor_wins[i].size - 1) & 0xffff0000);
1196
1197 /* Set the first free XOR window */
1198 for (z = 0; z < MV_WIN_XOR_MAX; z++) {
1199 if (xor_ctrl_read(z, 0, e) &&
1200 xor_ctrl_read(z, 1, e))
1201 continue;
1202
1203 /* Configure window */
1204 win_xor_br_write(z, e, br);
1205 win_xor_sz_write(z, e, sz);
1206 if (win_xor_can_remap(z) &&
1207 xor_wins[z].remap >= 0)
1208 win_xor_har_write(z, e,
1209 xor_wins[z].remap);
1210
1211 /* Set protection RW on all channels */
1212 xor_set_prot(z, e, 0x3);
1213
1214 /* Enable window */
1215 xor_ctrl_write(z, 0, e, 1);
1216 xor_ctrl_write(z, 1, e, 1);
1217 break;
1218 }
1219 }
1220 }
1221}
1222
1223int
1224decode_win_xor_valid(void)
1225{
1226 const struct decode_win *wintab;
1227 int c, i, j, rv;
1228 uint32_t b, e, s;
1229
1230 if (xor_wins_no > MV_WIN_XOR_MAX) {
1231 printf("XOR windows: too many entries: %d\n", xor_wins_no);
1232 return (-1);
1233 }
1234 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
1235 if (ddr_is_active(i))
1236 c++;
1237
1238 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
1239 printf("XOR windows: too many entries: %d, available: %d\n",
1240 xor_wins_no, MV_WIN_IDMA_MAX - c);
1241 return (-1);
1242 }
1243
1244 wintab = xor_wins;
1245 rv = 1;
1246 for (i = 0; i < xor_wins_no; i++, wintab++) {
1247
1248 if (wintab->target == 0) {
1249 printf("XOR window#%d: DDR target window is not "
1250 "supposed to be reprogrammed!\n", i);
1251 rv = 0;
1252 }
1253
1254 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
1255 printf("XOR window#%d: not capable of remapping, but "
1256 "val 0x%08x defined\n", i, wintab->remap);
1257 rv = 0;
1258 }
1259
1260 s = wintab->size;
1261 b = wintab->base;
1262 e = b + s - 1;
1263 if (s > (0xFFFFFFFF - b + 1)) {
1264 /*
1265 * XXX this boundary check should account for 64bit
1266 * and remapping..
1267 */
1268 printf("XOR window#%d: no space for size 0x%08x at "
1269 "0x%08x\n", i, s, b);
1270 rv = 0;
1271 continue;
1272 }
1273
1274 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
1275 if (j >= 0) {
1276 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
1277 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1278 xor_wins[j].base,
1279 xor_wins[j].base + xor_wins[j].size - 1);
1280 rv = 0;
1281 }
1282 }
1283
1284 return (rv);
1285}
1286
1287void
1288decode_win_xor_dump(void)
1289{
1290 int i, j;
1291 int e = 1;
1292
1293 for (j = 0; j < xor_max_eng(); j++, e--) {
1294 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1295 printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
1296 win_xor_br_read(i, e), win_xor_sz_read(i, e));
1297
1298 if (win_xor_can_remap(i))
1299 printf(", ha 0x%08x", win_xor_har_read(i, e));
1300
1301 printf("\n");
1302 }
1303 for (i = 0; i < MV_XOR_CHAN_MAX; i++)
1304 printf("XOR control#%d: 0x%08x\n", i,
1305 win_xor_ctrl_read(i, e));
1306 }
1307}
1308
1309#else
1310/* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
1311int
1312decode_win_xor_valid(void)
1313{
1314
1315 return (1);
1316}
1317
1318void
1319decode_win_xor_setup(void)
1320{
1321}
1322
1323void
1324decode_win_xor_dump(void)
1325{
1326}
1327#endif
1328
1329/**************************************************************************
1330 * CESA TDMA windows routines
1331 **************************************************************************/
1332#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
1333/*
1334 * Dump CESA TDMA decode windows.
1335 */
1336static void
1337decode_win_cesa_dump(void)
1338{
1339 int i;
1340
1341 for (i = 0; i < MV_WIN_CESA_MAX; i++)
1342 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i,
1343 win_cesa_cr_read(i), win_cesa_br_read(i));
1344}
1345
1346
1347/*
1348 * Set CESA TDMA decode windows.
1349 */
1350static void
1351decode_win_cesa_setup(void)
1352{
1353 uint32_t br, cr;
1354 int i, j;
1355
1356 /* Disable and clear all CESA windows */
1357 for (i = 0; i < MV_WIN_CESA_MAX; i++) {
1358 win_cesa_cr_write(i, 0);
1359 win_cesa_br_write(i, 0);
1360 }
1361
1362 /* Only access to active DRAM banks is required. */
1363 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1364 if (ddr_is_active(i)) {
1365 br = ddr_base(i);
1366 cr = (((ddr_size(i) - 1) & 0xffff0000) |
1367 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1);
1368
1369 /* Set the first available CESA window */
1370 for (j = 0; j < MV_WIN_CESA_MAX; j++) {
1371 if (win_cesa_cr_read(j) & 0x1)
1372 continue;
1373
1374 win_cesa_br_write(j, br);
1375 win_cesa_cr_write(j, cr);
1376 break;
1377 }
1378 }
1379}
1380
1381/*
1382 * Check CESA TDMA decode windows.
1383 */
1384static int
1385decode_win_cesa_valid(void)
1386{
1387
1388 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX));
1389}
1390#else
1391
1392/*
1393 * Provide dummy functions to satisfy the build for SoCs not equipped with
1394 * CESA
1395 */
1396
1397int
1398decode_win_cesa_valid(void)
1399{
1400
1401 return (1);
1402}
1403
1404void
1405decode_win_cesa_setup(void)
1406{
1407}
1408
1409void
1410decode_win_cesa_dump(void)
1411{
1412}
1413#endif
1414
1415/**************************************************************************
1416 * SATA windows routines
1417 **************************************************************************/
1418static void
1419decode_win_sata_setup(void)
1420{
1421 uint32_t cr, br;
1422 int i, j;
1423
1424 for (i = 0; i < MV_WIN_SATA_MAX; i++) {
1425 win_sata_cr_write(i, 0);
1426 win_sata_br_write(i, 0);
1427 }
1428
1429 for (i = 0; i < MV_WIN_DDR_MAX; i++)
1430 if (ddr_is_active(i)) {
1431 cr = ((ddr_size(i) - 1) & 0xffff0000) |
1432 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
1433 br = ddr_base(i);
1434
1435 /* Use the first available SATA window */
1436 for (j = 0; j < MV_WIN_SATA_MAX; j++) {
1437 if ((win_sata_cr_read(j) & 1) != 0)
1438 continue;
1439
1440 win_sata_br_write(j, br);
1441 win_sata_cr_write(j, cr);
1442 break;
1443 }
1444 }
1445}
1446
1447static int
1448decode_win_sata_valid(void)
1449{
1450 uint32_t dev, rev;
1451
1452 soc_id(&dev, &rev);
1453 if (dev == MV_DEV_88F5281)
1454 return (1);
1455
1456 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
1457}