1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/mv/common.c 186899 2009-01-08 13:20:28Z raj $");
34
35#include <sys/systm.h>
36#include <sys/bus.h>
37
38#include <machine/bus.h>
39
40#include <arm/mv/mvreg.h>
41#include <arm/mv/mvvar.h>
42
43static int win_eth_can_remap(int i);
44
45static int decode_win_cpu_valid(void);
46static int decode_win_usb_valid(void);
47static int decode_win_eth_valid(void);
48static int decode_win_pcie_valid(void);
49
50static void decode_win_cpu_setup(void);
51static void decode_win_usb_setup(uint32_t ctrl);
52static void decode_win_eth_setup(uint32_t base);
53static void decode_win_pcie_setup(uint32_t base);
54
55static uint32_t dev, rev;
56static uint32_t used_cpu_wins;
57
58uint32_t
59read_cpu_ctrl(uint32_t reg)
60{
61
62 return (bus_space_read_4(obio_tag, MV_CPU_CONTROL_BASE, reg));
63}
64
65void
66write_cpu_ctrl(uint32_t reg, uint32_t val)
67{
68
69 bus_space_write_4(obio_tag, MV_CPU_CONTROL_BASE, reg, val);
70}
71
72void
73cpu_reset(void)
74{
75
76 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
77 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
78 while (1);
79}
80
81uint32_t
82cpu_extra_feat(void)
83{
84 uint32_t ef = 0;
85
86 soc_id(&dev, &rev);
87 if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100)
88 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
89 else if (dev == MV_DEV_88F5182 || dev == MV_DEV_88F5281)
90 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
91 else if (bootverbose)
92 printf("This ARM Core does not support any extra features\n");
93
94 return (ef);
95}
96
97uint32_t
98soc_power_ctrl_get(uint32_t mask)
99{
100
101 if (mask != CPU_PM_CTRL_NONE)
102 mask &= read_cpu_ctrl(CPU_PM_CTRL);
103
104 return (mask);
105}
106
107void
108soc_id(uint32_t *dev, uint32_t *rev)
109{
110
111 /*
112 * Notice: system identifiers are available in the registers range of
113 * PCIE controller, so using this function is only allowed (and
114 * possible) after the internal registers range has been mapped in via
115 * pmap_devmap_bootstrap().
116 */
117 *dev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 0) >> 16;
118 *rev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 8) & 0xff;
119}
120
121void
122soc_identify(void)
123{
124 uint32_t d, r;
125 const char *dev;
126 const char *rev;
127
128 soc_id(&d, &r);
129
130 printf("SOC: ");
131 if (bootverbose)
132 printf("(0x%4x:0x%02x) ", d, r);
133
134 rev = "";
135 switch (d) {
136 case MV_DEV_88F5181:
137 dev = "Marvell 88F5181";
138 if (r == 3)
139 rev = "B1";
140 break;
141 case MV_DEV_88F5182:
142 dev = "Marvell 88F5182";
143 if (r == 2)
144 rev = "A2";
145 break;
146 case MV_DEV_88F5281:
147 dev = "Marvell 88F5281";
148 if (r == 4)
149 rev = "D0";
150 else if (r == 5)
151 rev = "D1";
152 else if (r == 6)
153 rev = "D2";
154 break;
155 case MV_DEV_88F6281:
156 dev = "Marvell 88F6281";
157 if (r == 0)
158 rev = "Z0";
159 else if (r == 2)
160 rev = "A0";
161 break;
162 case MV_DEV_MV78100:
163 dev = "Marvell MV78100";
164 break;
165 default:
166 dev = "UNKNOWN";
167 break;
168 }
169
170 printf("%s", dev);
171 if (*rev != '\0')
172 printf(" rev %s", rev);
173 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
174
175 /* TODO add info on currently set endianess */
176}
177
178int
179soc_decode_win(void)
180{
181
182 /* Retrieve our ID: some windows facilities vary between SoC models */
183 soc_id(&dev, &rev);
184
185 if (decode_win_cpu_valid() != 1 || decode_win_usb_valid() != 1 ||
186 decode_win_eth_valid() != 1 || decode_win_idma_valid() != 1 ||
187 decode_win_pcie_valid() != 1)
188 return(-1);
189
190 decode_win_cpu_setup();
191 decode_win_usb_setup(MV_USB0_BASE);
192 decode_win_eth_setup(MV_ETH0_BASE);
193 if (dev == MV_DEV_MV78100)
194 decode_win_eth_setup(MV_ETH1_BASE);
195
196 decode_win_idma_setup();
197
198 if (dev == MV_DEV_MV78100) {
199 decode_win_pcie_setup(MV_PCIE00_BASE);
200 decode_win_pcie_setup(MV_PCIE01_BASE);
201 decode_win_pcie_setup(MV_PCIE02_BASE);
202 decode_win_pcie_setup(MV_PCIE03_BASE);
203 decode_win_pcie_setup(MV_PCIE10_BASE);
204 decode_win_pcie_setup(MV_PCIE11_BASE);
205 decode_win_pcie_setup(MV_PCIE12_BASE);
206 decode_win_pcie_setup(MV_PCIE13_BASE);
207 } else
208 decode_win_pcie_setup(MV_PCIE_BASE);
209
210 /* TODO set up decode wins for SATA */
211
212 return (0);
213}
214
215/**************************************************************************
216 * Decode windows registers accessors
217 **************************************************************************/
218WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
219WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
220WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
221WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
222WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
223WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
224WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
225WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
226
227WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
228WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
229
230WIN_REG_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
231WIN_REG_IDX_RD(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
232WIN_REG_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
233WIN_REG_IDX_WR(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
234
235WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
236WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
237WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
238WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
239WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
240WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
241WIN_REG_BASE_RD(win_eth, bare, 0x290)
242WIN_REG_BASE_RD(win_eth, epap, 0x294)
243WIN_REG_BASE_WR(win_eth, bare, 0x290)
244WIN_REG_BASE_WR(win_eth, epap, 0x294)
245
246WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
247WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
248WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
249WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
250WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
251WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
252WIN_REG_BASE_IDX_WR(pcie, bar, MV_PCIE_BAR);
253
254WIN_REG_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
255WIN_REG_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
256WIN_REG_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
257WIN_REG_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
258WIN_REG_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
259WIN_REG_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
260WIN_REG_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
261WIN_REG_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
262WIN_REG_RD(win_idma, bare, 0xa80, MV_IDMA_BASE)
263WIN_REG_WR(win_idma, bare, 0xa80, MV_IDMA_BASE)
264
265/**************************************************************************
266 * Decode windows helper routines
267 **************************************************************************/
268void
269soc_dump_decode_win(void)
270{
271 int i;
272
273 soc_id(&dev, &rev);
274
275 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
276 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
277 win_cpu_cr_read(i),
278 win_cpu_br_read(i));
279
280 if (win_cpu_can_remap(i))
281 printf(", rl 0x%08x, rh 0x%08x",
282 win_cpu_remap_l_read(i),
283 win_cpu_remap_h_read(i));
284
285 printf("\n");
286 }
287 printf("Internal regs base: 0x%08x\n",
288 bus_space_read_4(obio_tag, MV_INTREGS_BASE, 0));
289
290 for (i = 0; i < MV_WIN_DDR_MAX; i++)
291 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
292 ddr_br_read(i), ddr_sz_read(i));
293
294 for (i = 0; i < MV_WIN_USB_MAX; i++)
295 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
296 win_usb_cr_read(i), win_usb_br_read(i));
297
298 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
299 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
300 win_eth_br_read(MV_ETH0_BASE, i),
301 win_eth_sz_read(MV_ETH0_BASE, i));
302
303 if (win_eth_can_remap(i))
304 printf(", ha 0x%08x",
305 win_eth_har_read(MV_ETH0_BASE, i));
306
307 printf("\n");
308 }
309 printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
310 win_eth_bare_read(MV_ETH0_BASE),
311 win_eth_epap_read(MV_ETH0_BASE));
312
313 decode_win_idma_dump();
314 printf("\n");
315}
316
317/**************************************************************************
318 * CPU windows routines
319 **************************************************************************/
320int
321win_cpu_can_remap(int i)
322{
323
324 /* Depending on the SoC certain windows have remap capability */
325 if ((dev == MV_DEV_88F5182 && i < 2) ||
326 (dev == MV_DEV_88F5281 && i < 4) ||
327 (dev == MV_DEV_88F6281 && i < 4) ||
328 (dev == MV_DEV_MV78100 && i < 8))
329 return (1);
330
331 return (0);
332}
333
334/* XXX This should check for overlapping remap fields too.. */
335int
336decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
337{
338 const struct decode_win *tab;
339 int i;
340
341 tab = wintab;
342
343 for (i = 0; i < win_no; i++, tab++) {
344 if (i == win)
345 /* Skip self */
346 continue;
347
348 if ((tab->base + tab->size - 1) < (wintab + win)->base)
349 continue;
350
351 else if (((wintab + win)->base + (wintab + win)->size - 1) <
352 tab->base)
353 continue;
354 else
355 return (i);
356 }
357
358 return (-1);
359}
360
361static int
362decode_win_cpu_valid(void)
363{
364 int i, j, rv;
365 uint32_t b, e, s;
366
367 if (cpu_wins_no > MV_WIN_CPU_MAX) {
368 printf("CPU windows: too many entries: %d\n", cpu_wins_no);
369 return (-1);
370 }
371
372 rv = 1;
373 for (i = 0; i < cpu_wins_no; i++) {
374
375 if (cpu_wins[i].target == 0) {
376 printf("CPU window#%d: DDR target window is not "
377 "supposed to be reprogrammed!\n", i);
378 rv = 0;
379 }
380
381 if (cpu_wins[i].remap >= 0 && win_cpu_can_remap(i) != 1) {
382 printf("CPU window#%d: not capable of remapping, but "
383 "val 0x%08x defined\n", i, cpu_wins[i].remap);
384 rv = 0;
385 }
386
387 s = cpu_wins[i].size;
388 b = cpu_wins[i].base;
389 e = b + s - 1;
390 if (s > (0xFFFFFFFF - b + 1)) {
391 /*
392 * XXX this boundary check should account for 64bit
393 * and remapping..
394 */
395 printf("CPU window#%d: no space for size 0x%08x at "
396 "0x%08x\n", i, s, b);
397 rv = 0;
398 continue;
399 }
400
401 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
402 if (j >= 0) {
403 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
404 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
405 cpu_wins[j].base,
406 cpu_wins[j].base + cpu_wins[j].size - 1);
407 rv = 0;
408 }
409 }
410
411 return (rv);
412}
413
414int
415decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
416 int remap)
417{
418 uint32_t br, cr;
419 int win;
420
421 if (used_cpu_wins >= MV_WIN_CPU_MAX)
422 return (-1);
423
424 win = used_cpu_wins++;
425
426 br = base & 0xffff0000;
427 win_cpu_br_write(win, br);
428
429 if (win_cpu_can_remap(win)) {
430 if (remap >= 0) {
431 win_cpu_remap_l_write(win, remap & 0xffff0000);
432 win_cpu_remap_h_write(win, 0);
433 } else {
434 /*
435 * Remap function is not used for a given window
436 * (capable of remapping) - set remap field with the
437 * same value as base.
438 */
439 win_cpu_remap_l_write(win, base & 0xffff0000);
440 win_cpu_remap_h_write(win, 0);
441 }
442 }
443
444 cr = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
445 win_cpu_cr_write(win, cr);
446
447 return (0);
448}
449
450static void
451decode_win_cpu_setup(void)
452{
453 int i;
454
455 used_cpu_wins = 0;
456
457 /* Disable all CPU windows */
458 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
459 win_cpu_cr_write(i, 0);
460 win_cpu_br_write(i, 0);
461 if (win_cpu_can_remap(i)) {
462 win_cpu_remap_l_write(i, 0);
463 win_cpu_remap_h_write(i, 0);
464 }
465 }
466
467 for (i = 0; i < cpu_wins_no; i++)
468 if (cpu_wins[i].target > 0)
469 decode_win_cpu_set(cpu_wins[i].target,
470 cpu_wins[i].attr, cpu_wins[i].base,
471 cpu_wins[i].size, cpu_wins[i].remap);
472
473}
474
475/*
476 * Check if we're able to cover all active DDR banks.
477 */
478static int
479decode_win_can_cover_ddr(int max)
480{
481 int i, c;
482
483 c = 0;
484 for (i = 0; i < MV_WIN_DDR_MAX; i++)
485 if (ddr_is_active(i))
486 c++;
487
488 if (c > max) {
489 printf("Unable to cover all active DDR banks: "
490 "%d, available windows: %d\n", c, max);
491 return (0);
492 }
493
494 return (1);
495}
496
497/**************************************************************************
498 * DDR windows routines
499 **************************************************************************/
500int
501ddr_is_active(int i)
502{
503
504 if (ddr_sz_read(i) & 0x1)
505 return (1);
506
507 return (0);
508}
509
510uint32_t
511ddr_base(int i)
512{
513
514 return (ddr_br_read(i) & 0xff000000);
515}
516
517uint32_t
518ddr_size(int i)
519{
520
521 return ((ddr_sz_read(i) | 0x00ffffff) + 1);
522}
523
524uint32_t
525ddr_attr(int i)
526{
527
528 return (i == 0 ? 0xe :
529 (i == 1 ? 0xd :
530 (i == 2 ? 0xb :
531 (i == 3 ? 0x7 : 0xff))));
532}
533
534uint32_t
535ddr_target(int i)
536{
537
538 /* Mbus unit ID is 0x0 for DDR SDRAM controller */
539 return (0);
540}
541
542/**************************************************************************
543 * USB windows routines
544 **************************************************************************/
545static int
546decode_win_usb_valid(void)
547{
548
549 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
550}
551
552/*
553 * Set USB decode windows.
554 */
555static void
556decode_win_usb_setup(uint32_t ctrl)
557{
558 uint32_t br, cr;
559 int i, j;
560
561 /* Disable and clear all USB windows */
562 for (i = 0; i < MV_WIN_USB_MAX; i++) {
563 win_usb_cr_write(i, 0);
564 win_usb_br_write(i, 0);
565 }
566
567 /* Only access to active DRAM banks is required */
568 for (i = 0; i < MV_WIN_DDR_MAX; i++)
569 if (ddr_is_active(i)) {
570 br = ddr_base(i);
571 /*
572 * XXX for 6281 we should handle Mbus write burst limit
573 * field in the ctrl reg
574 */
575 cr = (((ddr_size(i) - 1) & 0xffff0000) |
576 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1);
577
578 /* Set the first free USB window */
579 for (j = 0; j < MV_WIN_USB_MAX; j++) {
580 if (win_usb_cr_read(j) & 0x1)
581 continue;
582
583 win_usb_br_write(j, br);
584 win_usb_cr_write(j, cr);
585 break;
586 }
587 }
588}
589
590/**************************************************************************
591 * ETH windows routines
592 **************************************************************************/
593
594static int
595win_eth_can_remap(int i)
596{
597
598 /* ETH encode windows 0-3 have remap capability */
599 if (i < 4)
600 return (1);
601
602 return (0);
603}
604
605static int
606eth_bare_read(uint32_t base, int i)
607{
608 uint32_t v;
609
610 v = win_eth_bare_read(base);
611 v &= (1 << i);
612
613 return (v >> i);
614}
615
616static void
617eth_bare_write(uint32_t base, int i, int val)
618{
619 uint32_t v;
620
621 v = win_eth_bare_read(base);
622 v &= ~(1 << i);
623 v |= (val << i);
624 win_eth_bare_write(base, v);
625}
626
627static void
628eth_epap_write(uint32_t base, int i, int val)
629{
630 uint32_t v;
631
632 v = win_eth_epap_read(base);
633 v &= ~(0x3 << (i * 2));
634 v |= (val << (i * 2));
635 win_eth_epap_write(base, v);
636}
637
638static void
639decode_win_eth_setup(uint32_t base)
640{
641 uint32_t br, sz;
642 int i, j;
643
644 /* Disable, clear and revoke protection for all ETH windows */
645 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
646
647 eth_bare_write(base, i, 1);
648 eth_epap_write(base, i, 0);
649 win_eth_br_write(base, i, 0);
650 win_eth_sz_write(base, i, 0);
651 if (win_eth_can_remap(i))
652 win_eth_har_write(base, i, 0);
653 }
654
655 /* Only access to active DRAM banks is required */
656 for (i = 0; i < MV_WIN_DDR_MAX; i++)
657 if (ddr_is_active(i)) {
658
659 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
660 sz = ((ddr_size(i) - 1) & 0xffff0000);
661
662 /* Set the first free ETH window */
663 for (j = 0; j < MV_WIN_ETH_MAX; j++) {
664 if (eth_bare_read(base, j) == 0)
665 continue;
666
667 win_eth_br_write(base, j, br);
668 win_eth_sz_write(base, j, sz);
669
670 /* XXX remapping ETH windows not supported */
671
672 /* Set protection RW */
673 eth_epap_write(base, j, 0x3);
674
675 /* Enable window */
676 eth_bare_write(base, j, 0);
677 break;
678 }
679 }
680}
681
682static int
683decode_win_eth_valid(void)
684{
685
686 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
687}
688
689/**************************************************************************
690 * PCIE windows routines
691 **************************************************************************/
692
693static void
694decode_win_pcie_setup(uint32_t base)
695{
696 uint32_t size = 0;
697 uint32_t cr, br;
698 int i, j;
699
700 for (i = 0; i < MV_PCIE_BAR_MAX; i++)
701 pcie_bar_write(base, i, 0);
702
703 for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
704 win_pcie_cr_write(base, i, 0);
705 win_pcie_br_write(base, i, 0);
706 win_pcie_remap_write(base, i, 0);
707 }
708
709 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
710 if (ddr_is_active(i)) {
711 /* Map DDR to BAR 1 */
712 cr = (ddr_size(i) - 1) & 0xffff0000;
713 size += ddr_size(i) & 0xffff0000;
714 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
715 br = ddr_base(i);
716
717 /* Use the first available PCIE window */
718 for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
719 if (win_pcie_cr_read(base, j) != 0)
720 continue;
721
722 win_pcie_br_write(base, j, br);
723 win_pcie_cr_write(base, j, cr);
724 break;
725 }
726 }
727 }
728
729 /*
730 * Upper 16 bits in BAR register is interpreted as BAR size
731 * (in 64 kB units) plus 64kB, so substract 0x10000
732 * form value passed to register to get correct value.
733 */
734 size -= 0x10000;
735 pcie_bar_write(base, 0, size | 1);
736}
737
738static int
739decode_win_pcie_valid(void)
740{
741
742 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
743}
744
745/**************************************************************************
746 * IDMA windows routines
747 **************************************************************************/
748#if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
749static int
750idma_bare_read(int i)
751{
752 uint32_t v;
753
754 v = win_idma_bare_read();
755 v &= (1 << i);
756
757 return (v >> i);
758}
759
760static void
761idma_bare_write(int i, int val)
762{
763 uint32_t v;
764
765 v = win_idma_bare_read();
766 v &= ~(1 << i);
767 v |= (val << i);
768 win_idma_bare_write(v);
769}
770
771/*
772 * Sets channel protection 'val' for window 'w' on channel 'c'
773 */
774static void
775idma_cap_write(int c, int w, int val)
776{
777 uint32_t v;
778
779 v = win_idma_cap_read(c);
780 v &= ~(0x3 << (w * 2));
781 v |= (val << (w * 2));
782 win_idma_cap_write(c, v);
783}
784
785/*
786 * Set protection 'val' on all channels for window 'w'
787 */
788static void
789idma_set_prot(int w, int val)
790{
791 int c;
792
793 for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
794 idma_cap_write(c, w, val);
795}
796
797static int
798win_idma_can_remap(int i)
799{
800
801 /* IDMA decode windows 0-3 have remap capability */
802 if (i < 4)
803 return (1);
804
805 return (0);
806}
807
808void
809decode_win_idma_setup(void)
810{
811 uint32_t br, sz;
812 int i, j;
813
814 /*
815 * Disable and clear all IDMA windows, revoke protection for all channels
816 */
817 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
818
819 idma_bare_write(i, 1);
820 win_idma_br_write(i, 0);
821 win_idma_sz_write(i, 0);
822 if (win_idma_can_remap(i) == 1)
823 win_idma_har_write(i, 0);
824 }
825 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
826 win_idma_cap_write(i, 0);
827
828 /*
829 * Set up access to all active DRAM banks
830 */
831 for (i = 0; i < MV_WIN_DDR_MAX; i++)
832 if (ddr_is_active(i)) {
833 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
834 sz = ((ddr_size(i) - 1) & 0xffff0000);
835
836 /* Place DDR entries in non-remapped windows */
837 for (j = 0; j < MV_WIN_IDMA_MAX; j++)
838 if (win_idma_can_remap(j) != 1 &&
839 idma_bare_read(j) == 1) {
840
841 /* Configure window */
842 win_idma_br_write(j, br);
843 win_idma_sz_write(j, sz);
844
845 /* Set protection RW on all channels */
846 idma_set_prot(j, 0x3);
847
848 /* Enable window */
849 idma_bare_write(j, 0);
850 break;
851 }
852 }
853
854 /*
855 * Remaining targets -- from statically defined table
856 */
857 for (i = 0; i < idma_wins_no; i++)
858 if (idma_wins[i].target > 0) {
859 br = (idma_wins[i].base & 0xffff0000) |
860 (idma_wins[i].attr << 8) | idma_wins[i].target;
861 sz = ((idma_wins[i].size - 1) & 0xffff0000);
862
863 /* Set the first free IDMA window */
864 for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
865 if (idma_bare_read(j) == 0)
866 continue;
867
868 /* Configure window */
869 win_idma_br_write(j, br);
870 win_idma_sz_write(j, sz);
871 if (win_idma_can_remap(j) &&
872 idma_wins[j].remap >= 0)
873 win_idma_har_write(j, idma_wins[j].remap);
874
875 /* Set protection RW on all channels */
876 idma_set_prot(j, 0x3);
877
878 /* Enable window */
879 idma_bare_write(j, 0);
880 break;
881 }
882 }
883}
884
885int
886decode_win_idma_valid(void)
887{
888 const struct decode_win *wintab;
889 int c, i, j, rv;
890 uint32_t b, e, s;
891
892 if (idma_wins_no > MV_WIN_IDMA_MAX) {
893 printf("IDMA windows: too many entries: %d\n", idma_wins_no);
894 return (-1);
895 }
896 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
897 if (ddr_is_active(i))
898 c++;
899
900 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
901 printf("IDMA windows: too many entries: %d, available: %d\n",
902 idma_wins_no, MV_WIN_IDMA_MAX - c);
903 return (-1);
904 }
905
906 wintab = idma_wins;
907 rv = 1;
908 for (i = 0; i < idma_wins_no; i++, wintab++) {
909
910 if (wintab->target == 0) {
911 printf("IDMA window#%d: DDR target window is not "
912 "supposed to be reprogrammed!\n", i);
913 rv = 0;
914 }
915
916 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
917 printf("IDMA window#%d: not capable of remapping, but "
918 "val 0x%08x defined\n", i, wintab->remap);
919 rv = 0;
920 }
921
922 s = wintab->size;
923 b = wintab->base;
924 e = b + s - 1;
925 if (s > (0xFFFFFFFF - b + 1)) {
926 /* XXX this boundary check should account for 64bit and
927 * remapping.. */
928 printf("IDMA window#%d: no space for size 0x%08x at "
929 "0x%08x\n", i, s, b);
930 rv = 0;
931 continue;
932 }
933
934 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
935 if (j >= 0) {
936 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
937 "with " "#%d (0x%08x - 0x%08x)\n", i, b, e, j,
938 idma_wins[j].base,
939 idma_wins[j].base + idma_wins[j].size - 1);
940 rv = 0;
941 }
942 }
943
944 return (rv);
945}
946
947void
948decode_win_idma_dump(void)
949{
950 int i;
951
952 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
953 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
954 win_idma_br_read(i), win_idma_sz_read(i));
955
956 if (win_idma_can_remap(i))
957 printf(", ha 0x%08x", win_idma_har_read(i));
958
959 printf("\n");
960 }
961 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
962 printf("IDMA channel#%d: ap 0x%08x\n", i,
963 win_idma_cap_read(i));
964 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read());
965}
966#else
967
968/* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
969int
970decode_win_idma_valid(void)
971{
972
973 return (1);
974}
975
976void
977decode_win_idma_setup(void)
978{
979}
980
981void
982decode_win_idma_dump(void)
983{
984}
985#endif
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/mv/common.c 186899 2009-01-08 13:20:28Z raj $");
34
35#include <sys/systm.h>
36#include <sys/bus.h>
37
38#include <machine/bus.h>
39
40#include <arm/mv/mvreg.h>
41#include <arm/mv/mvvar.h>
42
43static int win_eth_can_remap(int i);
44
45static int decode_win_cpu_valid(void);
46static int decode_win_usb_valid(void);
47static int decode_win_eth_valid(void);
48static int decode_win_pcie_valid(void);
49
50static void decode_win_cpu_setup(void);
51static void decode_win_usb_setup(uint32_t ctrl);
52static void decode_win_eth_setup(uint32_t base);
53static void decode_win_pcie_setup(uint32_t base);
54
55static uint32_t dev, rev;
56static uint32_t used_cpu_wins;
57
58uint32_t
59read_cpu_ctrl(uint32_t reg)
60{
61
62 return (bus_space_read_4(obio_tag, MV_CPU_CONTROL_BASE, reg));
63}
64
65void
66write_cpu_ctrl(uint32_t reg, uint32_t val)
67{
68
69 bus_space_write_4(obio_tag, MV_CPU_CONTROL_BASE, reg, val);
70}
71
72void
73cpu_reset(void)
74{
75
76 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
77 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
78 while (1);
79}
80
81uint32_t
82cpu_extra_feat(void)
83{
84 uint32_t ef = 0;
85
86 soc_id(&dev, &rev);
87 if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100)
88 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
89 else if (dev == MV_DEV_88F5182 || dev == MV_DEV_88F5281)
90 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
91 else if (bootverbose)
92 printf("This ARM Core does not support any extra features\n");
93
94 return (ef);
95}
96
97uint32_t
98soc_power_ctrl_get(uint32_t mask)
99{
100
101 if (mask != CPU_PM_CTRL_NONE)
102 mask &= read_cpu_ctrl(CPU_PM_CTRL);
103
104 return (mask);
105}
106
107void
108soc_id(uint32_t *dev, uint32_t *rev)
109{
110
111 /*
112 * Notice: system identifiers are available in the registers range of
113 * PCIE controller, so using this function is only allowed (and
114 * possible) after the internal registers range has been mapped in via
115 * pmap_devmap_bootstrap().
116 */
117 *dev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 0) >> 16;
118 *rev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 8) & 0xff;
119}
120
121void
122soc_identify(void)
123{
124 uint32_t d, r;
125 const char *dev;
126 const char *rev;
127
128 soc_id(&d, &r);
129
130 printf("SOC: ");
131 if (bootverbose)
132 printf("(0x%4x:0x%02x) ", d, r);
133
134 rev = "";
135 switch (d) {
136 case MV_DEV_88F5181:
137 dev = "Marvell 88F5181";
138 if (r == 3)
139 rev = "B1";
140 break;
141 case MV_DEV_88F5182:
142 dev = "Marvell 88F5182";
143 if (r == 2)
144 rev = "A2";
145 break;
146 case MV_DEV_88F5281:
147 dev = "Marvell 88F5281";
148 if (r == 4)
149 rev = "D0";
150 else if (r == 5)
151 rev = "D1";
152 else if (r == 6)
153 rev = "D2";
154 break;
155 case MV_DEV_88F6281:
156 dev = "Marvell 88F6281";
157 if (r == 0)
158 rev = "Z0";
159 else if (r == 2)
160 rev = "A0";
161 break;
162 case MV_DEV_MV78100:
163 dev = "Marvell MV78100";
164 break;
165 default:
166 dev = "UNKNOWN";
167 break;
168 }
169
170 printf("%s", dev);
171 if (*rev != '\0')
172 printf(" rev %s", rev);
173 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
174
175 /* TODO add info on currently set endianess */
176}
177
178int
179soc_decode_win(void)
180{
181
182 /* Retrieve our ID: some windows facilities vary between SoC models */
183 soc_id(&dev, &rev);
184
185 if (decode_win_cpu_valid() != 1 || decode_win_usb_valid() != 1 ||
186 decode_win_eth_valid() != 1 || decode_win_idma_valid() != 1 ||
187 decode_win_pcie_valid() != 1)
188 return(-1);
189
190 decode_win_cpu_setup();
191 decode_win_usb_setup(MV_USB0_BASE);
192 decode_win_eth_setup(MV_ETH0_BASE);
193 if (dev == MV_DEV_MV78100)
194 decode_win_eth_setup(MV_ETH1_BASE);
195
196 decode_win_idma_setup();
197
198 if (dev == MV_DEV_MV78100) {
199 decode_win_pcie_setup(MV_PCIE00_BASE);
200 decode_win_pcie_setup(MV_PCIE01_BASE);
201 decode_win_pcie_setup(MV_PCIE02_BASE);
202 decode_win_pcie_setup(MV_PCIE03_BASE);
203 decode_win_pcie_setup(MV_PCIE10_BASE);
204 decode_win_pcie_setup(MV_PCIE11_BASE);
205 decode_win_pcie_setup(MV_PCIE12_BASE);
206 decode_win_pcie_setup(MV_PCIE13_BASE);
207 } else
208 decode_win_pcie_setup(MV_PCIE_BASE);
209
210 /* TODO set up decode wins for SATA */
211
212 return (0);
213}
214
215/**************************************************************************
216 * Decode windows registers accessors
217 **************************************************************************/
218WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
219WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
220WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
221WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
222WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
223WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
224WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
225WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
226
227WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
228WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
229
230WIN_REG_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
231WIN_REG_IDX_RD(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
232WIN_REG_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
233WIN_REG_IDX_WR(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
234
235WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
236WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
237WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
238WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
239WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
240WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
241WIN_REG_BASE_RD(win_eth, bare, 0x290)
242WIN_REG_BASE_RD(win_eth, epap, 0x294)
243WIN_REG_BASE_WR(win_eth, bare, 0x290)
244WIN_REG_BASE_WR(win_eth, epap, 0x294)
245
246WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
247WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
248WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
249WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
250WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
251WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
252WIN_REG_BASE_IDX_WR(pcie, bar, MV_PCIE_BAR);
253
254WIN_REG_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
255WIN_REG_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
256WIN_REG_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
257WIN_REG_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
258WIN_REG_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
259WIN_REG_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
260WIN_REG_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
261WIN_REG_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
262WIN_REG_RD(win_idma, bare, 0xa80, MV_IDMA_BASE)
263WIN_REG_WR(win_idma, bare, 0xa80, MV_IDMA_BASE)
264
265/**************************************************************************
266 * Decode windows helper routines
267 **************************************************************************/
268void
269soc_dump_decode_win(void)
270{
271 int i;
272
273 soc_id(&dev, &rev);
274
275 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
276 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
277 win_cpu_cr_read(i),
278 win_cpu_br_read(i));
279
280 if (win_cpu_can_remap(i))
281 printf(", rl 0x%08x, rh 0x%08x",
282 win_cpu_remap_l_read(i),
283 win_cpu_remap_h_read(i));
284
285 printf("\n");
286 }
287 printf("Internal regs base: 0x%08x\n",
288 bus_space_read_4(obio_tag, MV_INTREGS_BASE, 0));
289
290 for (i = 0; i < MV_WIN_DDR_MAX; i++)
291 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
292 ddr_br_read(i), ddr_sz_read(i));
293
294 for (i = 0; i < MV_WIN_USB_MAX; i++)
295 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
296 win_usb_cr_read(i), win_usb_br_read(i));
297
298 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
299 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
300 win_eth_br_read(MV_ETH0_BASE, i),
301 win_eth_sz_read(MV_ETH0_BASE, i));
302
303 if (win_eth_can_remap(i))
304 printf(", ha 0x%08x",
305 win_eth_har_read(MV_ETH0_BASE, i));
306
307 printf("\n");
308 }
309 printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
310 win_eth_bare_read(MV_ETH0_BASE),
311 win_eth_epap_read(MV_ETH0_BASE));
312
313 decode_win_idma_dump();
314 printf("\n");
315}
316
317/**************************************************************************
318 * CPU windows routines
319 **************************************************************************/
320int
321win_cpu_can_remap(int i)
322{
323
324 /* Depending on the SoC certain windows have remap capability */
325 if ((dev == MV_DEV_88F5182 && i < 2) ||
326 (dev == MV_DEV_88F5281 && i < 4) ||
327 (dev == MV_DEV_88F6281 && i < 4) ||
328 (dev == MV_DEV_MV78100 && i < 8))
329 return (1);
330
331 return (0);
332}
333
334/* XXX This should check for overlapping remap fields too.. */
335int
336decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
337{
338 const struct decode_win *tab;
339 int i;
340
341 tab = wintab;
342
343 for (i = 0; i < win_no; i++, tab++) {
344 if (i == win)
345 /* Skip self */
346 continue;
347
348 if ((tab->base + tab->size - 1) < (wintab + win)->base)
349 continue;
350
351 else if (((wintab + win)->base + (wintab + win)->size - 1) <
352 tab->base)
353 continue;
354 else
355 return (i);
356 }
357
358 return (-1);
359}
360
361static int
362decode_win_cpu_valid(void)
363{
364 int i, j, rv;
365 uint32_t b, e, s;
366
367 if (cpu_wins_no > MV_WIN_CPU_MAX) {
368 printf("CPU windows: too many entries: %d\n", cpu_wins_no);
369 return (-1);
370 }
371
372 rv = 1;
373 for (i = 0; i < cpu_wins_no; i++) {
374
375 if (cpu_wins[i].target == 0) {
376 printf("CPU window#%d: DDR target window is not "
377 "supposed to be reprogrammed!\n", i);
378 rv = 0;
379 }
380
381 if (cpu_wins[i].remap >= 0 && win_cpu_can_remap(i) != 1) {
382 printf("CPU window#%d: not capable of remapping, but "
383 "val 0x%08x defined\n", i, cpu_wins[i].remap);
384 rv = 0;
385 }
386
387 s = cpu_wins[i].size;
388 b = cpu_wins[i].base;
389 e = b + s - 1;
390 if (s > (0xFFFFFFFF - b + 1)) {
391 /*
392 * XXX this boundary check should account for 64bit
393 * and remapping..
394 */
395 printf("CPU window#%d: no space for size 0x%08x at "
396 "0x%08x\n", i, s, b);
397 rv = 0;
398 continue;
399 }
400
401 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
402 if (j >= 0) {
403 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
404 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
405 cpu_wins[j].base,
406 cpu_wins[j].base + cpu_wins[j].size - 1);
407 rv = 0;
408 }
409 }
410
411 return (rv);
412}
413
414int
415decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
416 int remap)
417{
418 uint32_t br, cr;
419 int win;
420
421 if (used_cpu_wins >= MV_WIN_CPU_MAX)
422 return (-1);
423
424 win = used_cpu_wins++;
425
426 br = base & 0xffff0000;
427 win_cpu_br_write(win, br);
428
429 if (win_cpu_can_remap(win)) {
430 if (remap >= 0) {
431 win_cpu_remap_l_write(win, remap & 0xffff0000);
432 win_cpu_remap_h_write(win, 0);
433 } else {
434 /*
435 * Remap function is not used for a given window
436 * (capable of remapping) - set remap field with the
437 * same value as base.
438 */
439 win_cpu_remap_l_write(win, base & 0xffff0000);
440 win_cpu_remap_h_write(win, 0);
441 }
442 }
443
444 cr = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
445 win_cpu_cr_write(win, cr);
446
447 return (0);
448}
449
450static void
451decode_win_cpu_setup(void)
452{
453 int i;
454
455 used_cpu_wins = 0;
456
457 /* Disable all CPU windows */
458 for (i = 0; i < MV_WIN_CPU_MAX; i++) {
459 win_cpu_cr_write(i, 0);
460 win_cpu_br_write(i, 0);
461 if (win_cpu_can_remap(i)) {
462 win_cpu_remap_l_write(i, 0);
463 win_cpu_remap_h_write(i, 0);
464 }
465 }
466
467 for (i = 0; i < cpu_wins_no; i++)
468 if (cpu_wins[i].target > 0)
469 decode_win_cpu_set(cpu_wins[i].target,
470 cpu_wins[i].attr, cpu_wins[i].base,
471 cpu_wins[i].size, cpu_wins[i].remap);
472
473}
474
475/*
476 * Check if we're able to cover all active DDR banks.
477 */
478static int
479decode_win_can_cover_ddr(int max)
480{
481 int i, c;
482
483 c = 0;
484 for (i = 0; i < MV_WIN_DDR_MAX; i++)
485 if (ddr_is_active(i))
486 c++;
487
488 if (c > max) {
489 printf("Unable to cover all active DDR banks: "
490 "%d, available windows: %d\n", c, max);
491 return (0);
492 }
493
494 return (1);
495}
496
497/**************************************************************************
498 * DDR windows routines
499 **************************************************************************/
500int
501ddr_is_active(int i)
502{
503
504 if (ddr_sz_read(i) & 0x1)
505 return (1);
506
507 return (0);
508}
509
510uint32_t
511ddr_base(int i)
512{
513
514 return (ddr_br_read(i) & 0xff000000);
515}
516
517uint32_t
518ddr_size(int i)
519{
520
521 return ((ddr_sz_read(i) | 0x00ffffff) + 1);
522}
523
524uint32_t
525ddr_attr(int i)
526{
527
528 return (i == 0 ? 0xe :
529 (i == 1 ? 0xd :
530 (i == 2 ? 0xb :
531 (i == 3 ? 0x7 : 0xff))));
532}
533
534uint32_t
535ddr_target(int i)
536{
537
538 /* Mbus unit ID is 0x0 for DDR SDRAM controller */
539 return (0);
540}
541
542/**************************************************************************
543 * USB windows routines
544 **************************************************************************/
545static int
546decode_win_usb_valid(void)
547{
548
549 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
550}
551
552/*
553 * Set USB decode windows.
554 */
555static void
556decode_win_usb_setup(uint32_t ctrl)
557{
558 uint32_t br, cr;
559 int i, j;
560
561 /* Disable and clear all USB windows */
562 for (i = 0; i < MV_WIN_USB_MAX; i++) {
563 win_usb_cr_write(i, 0);
564 win_usb_br_write(i, 0);
565 }
566
567 /* Only access to active DRAM banks is required */
568 for (i = 0; i < MV_WIN_DDR_MAX; i++)
569 if (ddr_is_active(i)) {
570 br = ddr_base(i);
571 /*
572 * XXX for 6281 we should handle Mbus write burst limit
573 * field in the ctrl reg
574 */
575 cr = (((ddr_size(i) - 1) & 0xffff0000) |
576 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1);
577
578 /* Set the first free USB window */
579 for (j = 0; j < MV_WIN_USB_MAX; j++) {
580 if (win_usb_cr_read(j) & 0x1)
581 continue;
582
583 win_usb_br_write(j, br);
584 win_usb_cr_write(j, cr);
585 break;
586 }
587 }
588}
589
590/**************************************************************************
591 * ETH windows routines
592 **************************************************************************/
593
594static int
595win_eth_can_remap(int i)
596{
597
598 /* ETH encode windows 0-3 have remap capability */
599 if (i < 4)
600 return (1);
601
602 return (0);
603}
604
605static int
606eth_bare_read(uint32_t base, int i)
607{
608 uint32_t v;
609
610 v = win_eth_bare_read(base);
611 v &= (1 << i);
612
613 return (v >> i);
614}
615
616static void
617eth_bare_write(uint32_t base, int i, int val)
618{
619 uint32_t v;
620
621 v = win_eth_bare_read(base);
622 v &= ~(1 << i);
623 v |= (val << i);
624 win_eth_bare_write(base, v);
625}
626
627static void
628eth_epap_write(uint32_t base, int i, int val)
629{
630 uint32_t v;
631
632 v = win_eth_epap_read(base);
633 v &= ~(0x3 << (i * 2));
634 v |= (val << (i * 2));
635 win_eth_epap_write(base, v);
636}
637
638static void
639decode_win_eth_setup(uint32_t base)
640{
641 uint32_t br, sz;
642 int i, j;
643
644 /* Disable, clear and revoke protection for all ETH windows */
645 for (i = 0; i < MV_WIN_ETH_MAX; i++) {
646
647 eth_bare_write(base, i, 1);
648 eth_epap_write(base, i, 0);
649 win_eth_br_write(base, i, 0);
650 win_eth_sz_write(base, i, 0);
651 if (win_eth_can_remap(i))
652 win_eth_har_write(base, i, 0);
653 }
654
655 /* Only access to active DRAM banks is required */
656 for (i = 0; i < MV_WIN_DDR_MAX; i++)
657 if (ddr_is_active(i)) {
658
659 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
660 sz = ((ddr_size(i) - 1) & 0xffff0000);
661
662 /* Set the first free ETH window */
663 for (j = 0; j < MV_WIN_ETH_MAX; j++) {
664 if (eth_bare_read(base, j) == 0)
665 continue;
666
667 win_eth_br_write(base, j, br);
668 win_eth_sz_write(base, j, sz);
669
670 /* XXX remapping ETH windows not supported */
671
672 /* Set protection RW */
673 eth_epap_write(base, j, 0x3);
674
675 /* Enable window */
676 eth_bare_write(base, j, 0);
677 break;
678 }
679 }
680}
681
682static int
683decode_win_eth_valid(void)
684{
685
686 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
687}
688
689/**************************************************************************
690 * PCIE windows routines
691 **************************************************************************/
692
693static void
694decode_win_pcie_setup(uint32_t base)
695{
696 uint32_t size = 0;
697 uint32_t cr, br;
698 int i, j;
699
700 for (i = 0; i < MV_PCIE_BAR_MAX; i++)
701 pcie_bar_write(base, i, 0);
702
703 for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
704 win_pcie_cr_write(base, i, 0);
705 win_pcie_br_write(base, i, 0);
706 win_pcie_remap_write(base, i, 0);
707 }
708
709 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
710 if (ddr_is_active(i)) {
711 /* Map DDR to BAR 1 */
712 cr = (ddr_size(i) - 1) & 0xffff0000;
713 size += ddr_size(i) & 0xffff0000;
714 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
715 br = ddr_base(i);
716
717 /* Use the first available PCIE window */
718 for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
719 if (win_pcie_cr_read(base, j) != 0)
720 continue;
721
722 win_pcie_br_write(base, j, br);
723 win_pcie_cr_write(base, j, cr);
724 break;
725 }
726 }
727 }
728
729 /*
730 * Upper 16 bits in BAR register is interpreted as BAR size
731 * (in 64 kB units) plus 64kB, so substract 0x10000
732 * form value passed to register to get correct value.
733 */
734 size -= 0x10000;
735 pcie_bar_write(base, 0, size | 1);
736}
737
738static int
739decode_win_pcie_valid(void)
740{
741
742 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
743}
744
745/**************************************************************************
746 * IDMA windows routines
747 **************************************************************************/
748#if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
749static int
750idma_bare_read(int i)
751{
752 uint32_t v;
753
754 v = win_idma_bare_read();
755 v &= (1 << i);
756
757 return (v >> i);
758}
759
760static void
761idma_bare_write(int i, int val)
762{
763 uint32_t v;
764
765 v = win_idma_bare_read();
766 v &= ~(1 << i);
767 v |= (val << i);
768 win_idma_bare_write(v);
769}
770
771/*
772 * Sets channel protection 'val' for window 'w' on channel 'c'
773 */
774static void
775idma_cap_write(int c, int w, int val)
776{
777 uint32_t v;
778
779 v = win_idma_cap_read(c);
780 v &= ~(0x3 << (w * 2));
781 v |= (val << (w * 2));
782 win_idma_cap_write(c, v);
783}
784
785/*
786 * Set protection 'val' on all channels for window 'w'
787 */
788static void
789idma_set_prot(int w, int val)
790{
791 int c;
792
793 for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
794 idma_cap_write(c, w, val);
795}
796
797static int
798win_idma_can_remap(int i)
799{
800
801 /* IDMA decode windows 0-3 have remap capability */
802 if (i < 4)
803 return (1);
804
805 return (0);
806}
807
808void
809decode_win_idma_setup(void)
810{
811 uint32_t br, sz;
812 int i, j;
813
814 /*
815 * Disable and clear all IDMA windows, revoke protection for all channels
816 */
817 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
818
819 idma_bare_write(i, 1);
820 win_idma_br_write(i, 0);
821 win_idma_sz_write(i, 0);
822 if (win_idma_can_remap(i) == 1)
823 win_idma_har_write(i, 0);
824 }
825 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
826 win_idma_cap_write(i, 0);
827
828 /*
829 * Set up access to all active DRAM banks
830 */
831 for (i = 0; i < MV_WIN_DDR_MAX; i++)
832 if (ddr_is_active(i)) {
833 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
834 sz = ((ddr_size(i) - 1) & 0xffff0000);
835
836 /* Place DDR entries in non-remapped windows */
837 for (j = 0; j < MV_WIN_IDMA_MAX; j++)
838 if (win_idma_can_remap(j) != 1 &&
839 idma_bare_read(j) == 1) {
840
841 /* Configure window */
842 win_idma_br_write(j, br);
843 win_idma_sz_write(j, sz);
844
845 /* Set protection RW on all channels */
846 idma_set_prot(j, 0x3);
847
848 /* Enable window */
849 idma_bare_write(j, 0);
850 break;
851 }
852 }
853
854 /*
855 * Remaining targets -- from statically defined table
856 */
857 for (i = 0; i < idma_wins_no; i++)
858 if (idma_wins[i].target > 0) {
859 br = (idma_wins[i].base & 0xffff0000) |
860 (idma_wins[i].attr << 8) | idma_wins[i].target;
861 sz = ((idma_wins[i].size - 1) & 0xffff0000);
862
863 /* Set the first free IDMA window */
864 for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
865 if (idma_bare_read(j) == 0)
866 continue;
867
868 /* Configure window */
869 win_idma_br_write(j, br);
870 win_idma_sz_write(j, sz);
871 if (win_idma_can_remap(j) &&
872 idma_wins[j].remap >= 0)
873 win_idma_har_write(j, idma_wins[j].remap);
874
875 /* Set protection RW on all channels */
876 idma_set_prot(j, 0x3);
877
878 /* Enable window */
879 idma_bare_write(j, 0);
880 break;
881 }
882 }
883}
884
885int
886decode_win_idma_valid(void)
887{
888 const struct decode_win *wintab;
889 int c, i, j, rv;
890 uint32_t b, e, s;
891
892 if (idma_wins_no > MV_WIN_IDMA_MAX) {
893 printf("IDMA windows: too many entries: %d\n", idma_wins_no);
894 return (-1);
895 }
896 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
897 if (ddr_is_active(i))
898 c++;
899
900 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
901 printf("IDMA windows: too many entries: %d, available: %d\n",
902 idma_wins_no, MV_WIN_IDMA_MAX - c);
903 return (-1);
904 }
905
906 wintab = idma_wins;
907 rv = 1;
908 for (i = 0; i < idma_wins_no; i++, wintab++) {
909
910 if (wintab->target == 0) {
911 printf("IDMA window#%d: DDR target window is not "
912 "supposed to be reprogrammed!\n", i);
913 rv = 0;
914 }
915
916 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
917 printf("IDMA window#%d: not capable of remapping, but "
918 "val 0x%08x defined\n", i, wintab->remap);
919 rv = 0;
920 }
921
922 s = wintab->size;
923 b = wintab->base;
924 e = b + s - 1;
925 if (s > (0xFFFFFFFF - b + 1)) {
926 /* XXX this boundary check should account for 64bit and
927 * remapping.. */
928 printf("IDMA window#%d: no space for size 0x%08x at "
929 "0x%08x\n", i, s, b);
930 rv = 0;
931 continue;
932 }
933
934 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
935 if (j >= 0) {
936 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
937 "with " "#%d (0x%08x - 0x%08x)\n", i, b, e, j,
938 idma_wins[j].base,
939 idma_wins[j].base + idma_wins[j].size - 1);
940 rv = 0;
941 }
942 }
943
944 return (rv);
945}
946
947void
948decode_win_idma_dump(void)
949{
950 int i;
951
952 for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
953 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
954 win_idma_br_read(i), win_idma_sz_read(i));
955
956 if (win_idma_can_remap(i))
957 printf(", ha 0x%08x", win_idma_har_read(i));
958
959 printf("\n");
960 }
961 for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
962 printf("IDMA channel#%d: ap 0x%08x\n", i,
963 win_idma_cap_read(i));
964 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read());
965}
966#else
967
968/* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
969int
970decode_win_idma_valid(void)
971{
972
973 return (1);
974}
975
976void
977decode_win_idma_setup(void)
978{
979}
980
981void
982decode_win_idma_dump(void)
983{
984}
985#endif