| discovery.c (186899) | discovery.c (186909) |
|---|---|
| 1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 16 unchanged lines hidden (view full) --- 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> | 1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 16 unchanged lines hidden (view full) --- 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> |
| 33__FBSDID("$FreeBSD: head/sys/arm/mv/discovery/discovery.c 186899 2009-01-08 13:20:28Z raj $"); | 33__FBSDID("$FreeBSD: head/sys/arm/mv/discovery/discovery.c 186909 2009-01-08 18:31:43Z raj $"); |
| 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38 39#include <machine/bus.h> 40 41#include <arm/mv/mvreg.h> --- 56 unchanged lines hidden (view full) --- 98 { -1 }, 99 CPU_PM_CTRL_XOR 100 }, 101 { "ehci", MV_USB0_BASE, MV_USB_SIZE, 102 { MV_INT_USB_ERR, MV_INT_USB0, -1 }, 103 { -1 }, 104 CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 105 }, | 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38 39#include <machine/bus.h> 40 41#include <arm/mv/mvreg.h> --- 56 unchanged lines hidden (view full) --- 98 { -1 }, 99 CPU_PM_CTRL_XOR 100 }, 101 { "ehci", MV_USB0_BASE, MV_USB_SIZE, 102 { MV_INT_USB_ERR, MV_INT_USB0, -1 }, 103 { -1 }, 104 CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 105 }, |
| 106 { "ehci", MV_USB1_BASE, MV_USB_SIZE, 107 { MV_INT_USB_ERR, MV_INT_USB1, -1 }, 108 { -1 }, 109 CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 110 }, 111 { "ehci", MV_USB2_BASE, MV_USB_SIZE, 112 { MV_INT_USB_ERR, MV_INT_USB2, -1 }, 113 { -1 }, 114 CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 115 }, |
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| 106 { "mge", MV_ETH0_BASE, MV_ETH_SIZE, 107 { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC, 108 MV_INT_GBESUM, MV_INT_GBE_ERR, -1 }, 109 { -1 }, 110 CPU_PM_CTRL_GE0 111 }, 112 { "mge", MV_ETH1_BASE, MV_ETH_SIZE, 113 { MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC, --- 58 unchanged lines hidden (view full) --- 172 MV_PCIE13_BASE, MV_PCIE_SIZE, 173 _MV_PCIE_IO(7), _MV_PCIE_IO_SIZE, 8, 0x70, 174 _MV_PCIE_MEM(7), _MV_PCIE_MEM_SIZE, 8, 0x78, 175 NULL, MV_INT_PEX13 }, 176 177 { 0, 0, 0 } 178}; 179 | 116 { "mge", MV_ETH0_BASE, MV_ETH_SIZE, 117 { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC, 118 MV_INT_GBESUM, MV_INT_GBE_ERR, -1 }, 119 { -1 }, 120 CPU_PM_CTRL_GE0 121 }, 122 { "mge", MV_ETH1_BASE, MV_ETH_SIZE, 123 { MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC, --- 58 unchanged lines hidden (view full) --- 182 MV_PCIE13_BASE, MV_PCIE_SIZE, 183 _MV_PCIE_IO(7), _MV_PCIE_IO_SIZE, 8, 0x70, 184 _MV_PCIE_MEM(7), _MV_PCIE_MEM_SIZE, 8, 0x78, 185 NULL, MV_INT_PEX13 }, 186 187 { 0, 0, 0 } 188}; 189 |
| 180struct resource_spec mv_gpio_spec[] = { | 190struct resource_spec mv_gpio_res[] = { |
| 181 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 182 { SYS_RES_IRQ, 0, RF_ACTIVE }, 183 { SYS_RES_IRQ, 1, RF_ACTIVE }, 184 { SYS_RES_IRQ, 2, RF_ACTIVE }, 185 { SYS_RES_IRQ, 3, RF_ACTIVE }, 186 { -1, 0 } 187}; 188 | 191 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 192 { SYS_RES_IRQ, 0, RF_ACTIVE }, 193 { SYS_RES_IRQ, 1, RF_ACTIVE }, 194 { SYS_RES_IRQ, 2, RF_ACTIVE }, 195 { SYS_RES_IRQ, 3, RF_ACTIVE }, 196 { -1, 0 } 197}; 198 |
| 189struct resource_spec mv_xor_spec[] = { | 199struct resource_spec mv_xor_res[] = { |
| 190 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 191 { SYS_RES_IRQ, 0, RF_ACTIVE }, 192 { SYS_RES_IRQ, 1, RF_ACTIVE }, 193 { SYS_RES_IRQ, 2, RF_ACTIVE }, 194 { -1, 0 } 195}; 196 197const struct decode_win cpu_win_tbl[] = { 198 /* Device bus BOOT */ 199 { 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 }, 200 201 /* Device bus CS0 */ 202 { 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 }, 203 204 /* Device bus CS1 */ 205 { 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 }, 206 207 /* Device bus CS2 */ 208 { 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 }, | 200 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 201 { SYS_RES_IRQ, 0, RF_ACTIVE }, 202 { SYS_RES_IRQ, 1, RF_ACTIVE }, 203 { SYS_RES_IRQ, 2, RF_ACTIVE }, 204 { -1, 0 } 205}; 206 207const struct decode_win cpu_win_tbl[] = { 208 /* Device bus BOOT */ 209 { 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 }, 210 211 /* Device bus CS0 */ 212 { 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 }, 213 214 /* Device bus CS1 */ 215 { 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 }, 216 217 /* Device bus CS2 */ 218 { 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 }, |
| 219 220 /* CESA */ 221 { 9, 0x01, MV_CESA_SRAM_PHYS_BASE, MV_CESA_SRAM_SIZE, -1 }, |
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| 209}; 210const struct decode_win *cpu_wins = cpu_win_tbl; 211int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); 212 213/* 214 * Note: the decode windows table for IDMA does not explicitly have DRAM 215 * entries, which are not statically defined: active DDR banks (== windows) 216 * are established in run time from actual DDR windows settings. All active --- 5 unchanged lines hidden (view full) --- 222const struct decode_win idma_win_tbl[] = { 223 /* PCIE MEM */ 224 { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1 }, 225 { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1 }, 226}; 227const struct decode_win *idma_wins = idma_win_tbl; 228int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); 229 | 222}; 223const struct decode_win *cpu_wins = cpu_win_tbl; 224int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); 225 226/* 227 * Note: the decode windows table for IDMA does not explicitly have DRAM 228 * entries, which are not statically defined: active DDR banks (== windows) 229 * are established in run time from actual DDR windows settings. All active --- 5 unchanged lines hidden (view full) --- 235const struct decode_win idma_win_tbl[] = { 236 /* PCIE MEM */ 237 { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1 }, 238 { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1 }, 239}; 240const struct decode_win *idma_wins = idma_win_tbl; 241int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); 242 |
| 243const struct decode_win xor_win_tbl[] = { 244 /* PCIE MEM */ 245 { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1}, 246 { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1}, 247}; 248const struct decode_win *xor_wins = xor_win_tbl; 249int xor_wins_no = sizeof(xor_win_tbl) / sizeof(struct decode_win); 250 |
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| 230uint32_t 231get_tclk(void) 232{ 233 uint32_t sar; 234 235 /* 236 * On Discovery TCLK is can be configured to 166 MHz or 200 MHz. 237 * Current setting is read from Sample At Reset register. --- 13 unchanged lines hidden --- | 251uint32_t 252get_tclk(void) 253{ 254 uint32_t sar; 255 256 /* 257 * On Discovery TCLK is can be configured to 166 MHz or 200 MHz. 258 * Current setting is read from Sample At Reset register. --- 13 unchanged lines hidden --- |