lpcreg.h (258780) | lpcreg.h (260326) |
---|---|
1/*- 2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
26 * $FreeBSD: head/sys/arm/lpc/lpcreg.h 258780 2013-11-30 22:17:27Z eadler $ | 26 * $FreeBSD: head/sys/arm/lpc/lpcreg.h 260326 2014-01-05 18:40:06Z ian $ |
27 */ 28 29#ifndef _ARM_LPC_LPCREG_H 30#define _ARM_LPC_LPCREG_H 31 32#define LPC_DEV_PHYS_BASE 0x40000000 33#define LPC_DEV_P5_PHYS_BASE 0x20000000 34#define LPC_DEV_P6_PHYS_BASE 0x30000000 | 27 */ 28 29#ifndef _ARM_LPC_LPCREG_H 30#define _ARM_LPC_LPCREG_H 31 32#define LPC_DEV_PHYS_BASE 0x40000000 33#define LPC_DEV_P5_PHYS_BASE 0x20000000 34#define LPC_DEV_P6_PHYS_BASE 0x30000000 |
35#define LPC_DEV_BASE 0xd0000000 | |
36#define LPC_DEV_SIZE 0x10000000 37 38/* 39 * Interrupt controller (from UM10326: LPC32x0 User manual, page 87) 40 41 */ 42#define LPC_INTC_MIC_ER 0x0000 43#define LPC_INTC_MIC_RSR 0x0004 --- 39 unchanged lines hidden (view full) --- 83#define LPC_TIMER_MCR_MR3R (1 << 10) 84#define LPC_TIMER_MCR_MR3S (1 << 11) 85#define LPC_TIMER_MR0 0x18 86#define LPC_TIMER_CTCR 0x70 87 88/* 89 * Watchdog timer. (from UM10326: LPC32x0 User manual, page 572) 90 */ | 35#define LPC_DEV_SIZE 0x10000000 36 37/* 38 * Interrupt controller (from UM10326: LPC32x0 User manual, page 87) 39 40 */ 41#define LPC_INTC_MIC_ER 0x0000 42#define LPC_INTC_MIC_RSR 0x0004 --- 39 unchanged lines hidden (view full) --- 82#define LPC_TIMER_MCR_MR3R (1 << 10) 83#define LPC_TIMER_MCR_MR3S (1 << 11) 84#define LPC_TIMER_MR0 0x18 85#define LPC_TIMER_CTCR 0x70 86 87/* 88 * Watchdog timer. (from UM10326: LPC32x0 User manual, page 572) 89 */ |
91#define LPC_WDTIM_BASE (LPC_DEV_BASE + 0x3c000) | 90#define LPC_WDTIM_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x3c000) |
92#define LPC_WDTIM_INT 0x00 93#define LPC_WDTIM_CTRL 0x04 94#define LPC_WDTIM_COUNTER 0x08 95#define LPC_WDTIM_MCTRL 0x0c 96#define LPC_WDTIM_MATCH0 0x10 97#define LPC_WDTIM_EMR 0x14 98#define LPC_WDTIM_PULSE 0x18 99#define LPC_WDTIM_RES 0x1c | 91#define LPC_WDTIM_INT 0x00 92#define LPC_WDTIM_CTRL 0x04 93#define LPC_WDTIM_COUNTER 0x08 94#define LPC_WDTIM_MCTRL 0x0c 95#define LPC_WDTIM_MATCH0 0x10 96#define LPC_WDTIM_EMR 0x14 97#define LPC_WDTIM_PULSE 0x18 98#define LPC_WDTIM_RES 0x1c |
99#define LPC_WDTIM_SIZE 0x20 |
|
100 101/* 102 * Clocking and power control. (from UM10326: LPC32x0 User manual, page 58) 103 */ | 100 101/* 102 * Clocking and power control. (from UM10326: LPC32x0 User manual, page 58) 103 */ |
104#define LPC_CLKPWR_BASE (LPC_DEV_BASE + 0x4000) | 104#define LPC_CLKPWR_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x4000) |
105#define LPC_CLKPWR_PWR_CTRL 0x44 106#define LPC_CLKPWR_OSC_CTRL 0x4c 107#define LPC_CLKPWR_SYSCLK_CTRL 0x50 108#define LPC_CLKPWR_PLL397_CTRL 0x48 109#define LPC_CLKPWR_HCLKPLL_CTRL 0x58 110#define LPC_CLKPWR_HCLKDIV_CTRL 0x40 111#define LPC_CLKPWR_TEST_CTRL 0xa4 112#define LPC_CLKPWR_AUTOCLK_CTRL 0xec --- 71 unchanged lines hidden (view full) --- 184#define LPC_CLKPWR_TIMCLK_CTRL_HSTIMER (1 << 1) 185#define LPC_CLKPWR_ADCLK_CTRL 0xb4 186#define LPC_CLKPWR_ADCLK_CTRL1 0x60 187#define LPC_CLKPWR_KEYCLK_CTRL 0xb0 188#define LPC_CLKPWR_PWMCLK_CTRL 0xb8 189#define LPC_CLKPWR_UARTCLK_CTRL 0xe4 190#define LPC_CLKPWR_POS0_IRAM_CTRL 0x110 191#define LPC_CLKPWR_POS1_IRAM_CTRL 0x114 | 105#define LPC_CLKPWR_PWR_CTRL 0x44 106#define LPC_CLKPWR_OSC_CTRL 0x4c 107#define LPC_CLKPWR_SYSCLK_CTRL 0x50 108#define LPC_CLKPWR_PLL397_CTRL 0x48 109#define LPC_CLKPWR_HCLKPLL_CTRL 0x58 110#define LPC_CLKPWR_HCLKDIV_CTRL 0x40 111#define LPC_CLKPWR_TEST_CTRL 0xa4 112#define LPC_CLKPWR_AUTOCLK_CTRL 0xec --- 71 unchanged lines hidden (view full) --- 184#define LPC_CLKPWR_TIMCLK_CTRL_HSTIMER (1 << 1) 185#define LPC_CLKPWR_ADCLK_CTRL 0xb4 186#define LPC_CLKPWR_ADCLK_CTRL1 0x60 187#define LPC_CLKPWR_KEYCLK_CTRL 0xb0 188#define LPC_CLKPWR_PWMCLK_CTRL 0xb8 189#define LPC_CLKPWR_UARTCLK_CTRL 0xe4 190#define LPC_CLKPWR_POS0_IRAM_CTRL 0x110 191#define LPC_CLKPWR_POS1_IRAM_CTRL 0x114 |
192#define LPC_CLKPWR_SIZE 0x118 |
|
192 193/* Additional UART registers in CLKPWR address space. */ 194#define LPC_CLKPWR_UART_U3CLK 0xd0 195#define LPC_CLKPWR_UART_U4CLK 0xd4 196#define LPC_CLKPWR_UART_U5CLK 0xd8 197#define LPC_CLKPWR_UART_U6CLK 0xdc 198#define LPC_CLKPWR_UART_UCLK_HCLK (1 << 16) 199#define LPC_CLKPWR_UART_UCLK_X(_n) (((_n) & 0xff) << 8) 200#define LPC_CLKPWR_UART_UCLK_Y(_n) ((_n) & 0xff) 201#define LPC_CLKPWR_UART_IRDACLK 0xe0 202 203/* Additional UART registers */ | 193 194/* Additional UART registers in CLKPWR address space. */ 195#define LPC_CLKPWR_UART_U3CLK 0xd0 196#define LPC_CLKPWR_UART_U4CLK 0xd4 197#define LPC_CLKPWR_UART_U5CLK 0xd8 198#define LPC_CLKPWR_UART_U6CLK 0xdc 199#define LPC_CLKPWR_UART_UCLK_HCLK (1 << 16) 200#define LPC_CLKPWR_UART_UCLK_X(_n) (((_n) & 0xff) << 8) 201#define LPC_CLKPWR_UART_UCLK_Y(_n) ((_n) & 0xff) 202#define LPC_CLKPWR_UART_IRDACLK 0xe0 203 204/* Additional UART registers */ |
204#define LPC_UART_BASE (LPC_DEV_BASE + 0x80000) 205#define LPC_UART_CONTROL_BASE (LPC_DEV_BASE + 0x54000) 206#define LPC_UART5_BASE (LPC_DEV_BASE + 0x90000) | 205#define LPC_UART_BASE 0x80000 206#define LPC_UART_CONTROL_BASE 0x54000 207#define LPC_UART5_BASE 0x90000 |
207#define LPC_UART_CTRL 0x00 208#define LPC_UART_CLKMODE 0x04 209#define LPC_UART_CLKMODE_UART3(_n) (((_n) & 0x3) << 4) 210#define LPC_UART_CLKMODE_UART4(_n) (((_n) & 0x3) << 6) 211#define LPC_UART_CLKMODE_UART5(_n) (((_n) & 0x3) << 8) 212#define LPC_UART_CLKMODE_UART6(_n) (((_n) & 0x3) << 10) 213#define LPC_UART_LOOP 0x08 | 208#define LPC_UART_CTRL 0x00 209#define LPC_UART_CLKMODE 0x04 210#define LPC_UART_CLKMODE_UART3(_n) (((_n) & 0x3) << 4) 211#define LPC_UART_CLKMODE_UART4(_n) (((_n) & 0x3) << 6) 212#define LPC_UART_CLKMODE_UART5(_n) (((_n) & 0x3) << 8) 213#define LPC_UART_CLKMODE_UART6(_n) (((_n) & 0x3) << 10) 214#define LPC_UART_LOOP 0x08 |
215#define LPC_UART_CONTROL_SIZE 0x0c |
|
214#define LPC_UART_FIFOSIZE 64 215 216/* 217 * Real time clock. (from UM10326: LPC32x0 User manual, page 566) 218 */ 219#define LPC_RTC_UCOUNT 0x00 220#define LPC_RTC_DCOUNT 0x04 221#define LPC_RTC_MATCH0 0x08 --- 9 unchanged lines hidden (view full) --- 231#define LPC_RTC_INTSTAT 0x14 232#define LPC_RTC_KEY 0x18 233#define LPC_RTC_SRAM_BEGIN 0x80 234#define LPC_RTC_SRAM_END 0xff 235 236/* 237 * MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436) 238 */ | 216#define LPC_UART_FIFOSIZE 64 217 218/* 219 * Real time clock. (from UM10326: LPC32x0 User manual, page 566) 220 */ 221#define LPC_RTC_UCOUNT 0x00 222#define LPC_RTC_DCOUNT 0x04 223#define LPC_RTC_MATCH0 0x08 --- 9 unchanged lines hidden (view full) --- 233#define LPC_RTC_INTSTAT 0x14 234#define LPC_RTC_KEY 0x18 235#define LPC_RTC_SRAM_BEGIN 0x80 236#define LPC_RTC_SRAM_END 0xff 237 238/* 239 * MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436) 240 */ |
239#define LPC_SD_BASE (LPC_DEV_P5_PHYS_BASE + 0x98000) | 241#define LPC_SD_PHYS_BASE (LPC_DEV_P5_PHYS_BASE + 0x98000) |
240#define LPC_SD_CLK (13 * 1000 * 1000) // 13Mhz 241#define LPC_SD_POWER 0x00 242#define LPC_SD_POWER_OPENDRAIN (1 << 6) 243#define LPC_SD_POWER_CTRL_OFF 0x00 244#define LPC_SD_POWER_CTRL_UP 0x02 245#define LPC_SD_POWER_CTRL_ON 0x03 246#define LPC_SD_CLOCK 0x04 247#define LPC_SD_CLOCK_WIDEBUS (1 << 11) --- 282 unchanged lines hidden (view full) --- 530#define LPC_SSP_RIS_TXRIS (1 << 3) 531#define LPC_SSP_MIS 0x1c 532#define LPC_SSP_ICR 0x20 533#define LPC_SSP_DMACR 0x24 534 535/* 536 * GPIO (from UM10326: LPC32x0 User manual, page 606) 537 */ | 242#define LPC_SD_CLK (13 * 1000 * 1000) // 13Mhz 243#define LPC_SD_POWER 0x00 244#define LPC_SD_POWER_OPENDRAIN (1 << 6) 245#define LPC_SD_POWER_CTRL_OFF 0x00 246#define LPC_SD_POWER_CTRL_UP 0x02 247#define LPC_SD_POWER_CTRL_ON 0x03 248#define LPC_SD_CLOCK 0x04 249#define LPC_SD_CLOCK_WIDEBUS (1 << 11) --- 282 unchanged lines hidden (view full) --- 532#define LPC_SSP_RIS_TXRIS (1 << 3) 533#define LPC_SSP_MIS 0x1c 534#define LPC_SSP_ICR 0x20 535#define LPC_SSP_DMACR 0x24 536 537/* 538 * GPIO (from UM10326: LPC32x0 User manual, page 606) 539 */ |
538#define LPC_GPIO_BASE (LPC_DEV_BASE + 0x28000) | 540#define LPC_GPIO_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x28000) |
539#define LPC_GPIO_P0_COUNT 8 540#define LPC_GPIO_P1_COUNT 24 541#define LPC_GPIO_P2_COUNT 13 542#define LPC_GPIO_P3_COUNT 52 543#define LPC_GPIO_P0_INP_STATE 0x40 544#define LPC_GPIO_P0_OUTP_SET 0x44 545#define LPC_GPIO_P0_OUTP_CLR 0x48 546#define LPC_GPIO_P0_OUTP_STATE 0x4c --- 12 unchanged lines hidden (view full) --- 559#define LPC_GPIO_P2_OUTP_CLR 0x24 560#define LPC_GPIO_P2_DIR_SET 0x10 561#define LPC_GPIO_P2_DIR_CLR 0x14 562#define LPC_GPIO_P2_DIR_STATE 0x14 563#define LPC_GPIO_P3_INP_STATE 0x00 564#define LPC_GPIO_P3_OUTP_SET 0x04 565#define LPC_GPIO_P3_OUTP_CLR 0x08 566#define LPC_GPIO_P3_OUTP_STATE 0x0c | 541#define LPC_GPIO_P0_COUNT 8 542#define LPC_GPIO_P1_COUNT 24 543#define LPC_GPIO_P2_COUNT 13 544#define LPC_GPIO_P3_COUNT 52 545#define LPC_GPIO_P0_INP_STATE 0x40 546#define LPC_GPIO_P0_OUTP_SET 0x44 547#define LPC_GPIO_P0_OUTP_CLR 0x48 548#define LPC_GPIO_P0_OUTP_STATE 0x4c --- 12 unchanged lines hidden (view full) --- 561#define LPC_GPIO_P2_OUTP_CLR 0x24 562#define LPC_GPIO_P2_DIR_SET 0x10 563#define LPC_GPIO_P2_DIR_CLR 0x14 564#define LPC_GPIO_P2_DIR_STATE 0x14 565#define LPC_GPIO_P3_INP_STATE 0x00 566#define LPC_GPIO_P3_OUTP_SET 0x04 567#define LPC_GPIO_P3_OUTP_CLR 0x08 568#define LPC_GPIO_P3_OUTP_STATE 0x0c |
569#define LPC_GPIO_SIZE 0x80 570 |
|
567/* Aliases for logical pin numbers: */ 568#define LPC_GPIO_GPI_00(_n) (0 + _n) 569#define LPC_GPIO_GPI_15(_n) (10 + _n) 570#define LPC_GPIO_GPI_25 (19) 571#define LPC_GPIO_GPI_27(_n) (20 + _n) 572#define LPC_GPIO_GPO_00(_n) (22 + _n) 573#define LPC_GPIO_GPIO_00(_n) (46 + _n) 574/* SPI devices chip selects: */ --- 87 unchanged lines hidden --- | 571/* Aliases for logical pin numbers: */ 572#define LPC_GPIO_GPI_00(_n) (0 + _n) 573#define LPC_GPIO_GPI_15(_n) (10 + _n) 574#define LPC_GPIO_GPI_25 (19) 575#define LPC_GPIO_GPI_27(_n) (20 + _n) 576#define LPC_GPIO_GPO_00(_n) (22 + _n) 577#define LPC_GPIO_GPIO_00(_n) (46 + _n) 578/* SPI devices chip selects: */ --- 87 unchanged lines hidden --- |