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lpc_machdep.c (257669) lpc_machdep.c (260326)
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

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34 *
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
36 */
37
38#include "opt_ddb.h"
39#include "opt_platform.h"
40
41#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 25 unchanged lines hidden (view full) ---

34 *
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
36 */
37
38#include "opt_ddb.h"
39#include "opt_platform.h"
40
41#include <sys/cdefs.h>
42__FBSDID("$FreeBSD: head/sys/arm/lpc/lpc_machdep.c 257669 2013-11-05 02:57:34Z ian $");
42__FBSDID("$FreeBSD: head/sys/arm/lpc/lpc_machdep.c 260326 2014-01-05 18:40:06Z ian $");
43
44#define _ARM32_BUS_DMA_PRIVATE
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48
49#include <vm/vm.h>
50#include <vm/pmap.h>
51
52#include <machine/bus.h>
53#include <machine/devmap.h>
54#include <machine/machdep.h>
55
56#include <arm/lpc/lpcreg.h>
57#include <arm/lpc/lpcvar.h>
58
59#include <dev/fdt/fdt_common.h>
43
44#define _ARM32_BUS_DMA_PRIVATE
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48
49#include <vm/vm.h>
50#include <vm/pmap.h>
51
52#include <machine/bus.h>
53#include <machine/devmap.h>
54#include <machine/machdep.h>
55
56#include <arm/lpc/lpcreg.h>
57#include <arm/lpc/lpcvar.h>
58
59#include <dev/fdt/fdt_common.h>
60#include <dev/ic/ns16550.h>
61
62vm_offset_t
63initarm_lastaddr(void)
64{
65
60
61vm_offset_t
62initarm_lastaddr(void)
63{
64
66 return (fdt_immr_va);
65 return (arm_devmap_lastaddr());
67}
68
69void
70initarm_early_init(void)
71{
66}
67
68void
69initarm_early_init(void)
70{
72
73 if (fdt_immr_addr(LPC_DEV_BASE) != 0)
74 while (1);
75}
76
77void
78initarm_gpio_init(void)
79{
80
81 /*
82 * Set initial values of GPIO output ports
83 */
84 platform_gpio_init();
85}
86
87void
88initarm_late_init(void)
89{
90}
91
71}
72
73void
74initarm_gpio_init(void)
75{
76
77 /*
78 * Set initial values of GPIO output ports
79 */
80 platform_gpio_init();
81}
82
83void
84initarm_late_init(void)
85{
86}
87
92#define FDT_DEVMAP_MAX (1 + 2 + 1 + 1)
93static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
94 { 0, 0, 0, 0, 0, }
95};
96
97/*
88/*
98 * Construct pmap_devmap[] with DT-derived config data.
89 * Add a single static device mapping.
90 * The values used were taken from the ranges property of the SoC node in the
91 * dts file when this code was converted to arm_devmap_add_entry().
99 */
100int
101initarm_devmap_init(void)
102{
103
92 */
93int
94initarm_devmap_init(void)
95{
96
104 /*
105 * IMMR range.
106 */
107 fdt_devmap[0].pd_va = fdt_immr_va;
108 fdt_devmap[0].pd_pa = fdt_immr_pa;
109 fdt_devmap[0].pd_size = fdt_immr_size;
110 fdt_devmap[0].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
111 fdt_devmap[0].pd_cache = PTE_NOCACHE;
112
113 arm_devmap_register_table(&fdt_devmap[0]);
97 arm_devmap_add_entry(LPC_DEV_PHYS_BASE, LPC_DEV_SIZE);
114 return (0);
115}
116
117struct arm32_dma_range *
118bus_dma_get_range(void)
119{
120
121 return (NULL);

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126{
127
128 return (0);
129}
130
131void
132cpu_reset(void)
133{
98 return (0);
99}
100
101struct arm32_dma_range *
102bus_dma_get_range(void)
103{
104
105 return (NULL);

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110{
111
112 return (0);
113}
114
115void
116cpu_reset(void)
117{
118 bus_space_tag_t bst;
119 bus_space_handle_t bsh;
120
121 bst = fdtbus_bs_tag;
122
134 /* Enable WDT */
123 /* Enable WDT */
135 bus_space_write_4(fdtbus_bs_tag,
136 LPC_CLKPWR_BASE, LPC_CLKPWR_TIMCLK_CTRL,
124 bus_space_map(bst, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0, &bsh);
125 bus_space_write_4(bst, bsh, LPC_CLKPWR_TIMCLK_CTRL,
137 LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG);
126 LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG);
127 bus_space_unmap(bst, bsh, LPC_CLKPWR_SIZE);
138
139 /* Instant assert of RESETOUT_N with pulse length 1ms */
128
129 /* Instant assert of RESETOUT_N with pulse length 1ms */
140 bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_PULSE, 13000);
141 bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_MCTRL, 0x70);
130 bus_space_map(bst, LPC_WDTIM_PHYS_BASE, LPC_WDTIM_SIZE, 0, &bsh);
131 bus_space_write_4(bst, bsh, LPC_WDTIM_PULSE, 13000);
132 bus_space_write_4(bst, bsh, LPC_WDTIM_MCTRL, 0x70);
133 bus_space_unmap(bst, bsh, LPC_WDTIM_SIZE);
142
134
143 for (;;);
135 for (;;)
136 continue;
144}
145
137}
138