| cpuconf.h (239268) | cpuconf.h (244480) |
|---|---|
| 1/* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * --- 20 unchanged lines hidden (view full) --- 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * | 1/* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * --- 20 unchanged lines hidden (view full) --- 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * |
| 37 * $FreeBSD: head/sys/arm/include/cpuconf.h 239268 2012-08-15 03:03:03Z gonzo $ | 37 * $FreeBSD: head/sys/arm/include/cpuconf.h 244480 2012-12-20 04:32:02Z gonzo $ |
| 38 * 39 */ 40 41#ifndef _MACHINE_CPUCONF_H_ 42#define _MACHINE_CPUCONF_H_ 43 44/* 45 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 46 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 47 * YOU ARE ADDING SUPPORT FOR. 48 */ 49 50/* 51 * Step 1: Count the number of CPU types configured into the kernel. 52 */ 53#define CPU_NTYPES (defined(CPU_ARM7TDMI) + \ 54 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 55 defined(CPU_ARM9E) + \ 56 defined(CPU_ARM10) + \ | 38 * 39 */ 40 41#ifndef _MACHINE_CPUCONF_H_ 42#define _MACHINE_CPUCONF_H_ 43 44/* 45 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 46 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 47 * YOU ARE ADDING SUPPORT FOR. 48 */ 49 50/* 51 * Step 1: Count the number of CPU types configured into the kernel. 52 */ 53#define CPU_NTYPES (defined(CPU_ARM7TDMI) + \ 54 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 55 defined(CPU_ARM9E) + \ 56 defined(CPU_ARM10) + \ |
| 57 defined(CPU_ARM11) + \ | 57 defined(CPU_ARM1136) + \ 58 defined(CPU_ARM1176) + \ |
| 58 defined(CPU_SA110) + defined(CPU_SA1100) + \ 59 defined(CPU_SA1110) + \ 60 defined(CPU_IXP12X0) + \ 61 defined(CPU_XSCALE_80200) + \ 62 defined(CPU_XSCALE_80321) + \ 63 defined(CPU_XSCALE_PXA2X0) + \ 64 defined(CPU_FA526) + \ 65 defined(CPU_FA626TE) + \ --- 18 unchanged lines hidden (view full) --- 84 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 85 defined(CPU_FA626TE)) 86#define ARM_ARCH_5 1 87#else 88#define ARM_ARCH_5 0 89#endif 90 91#if !defined(ARM_ARCH_6) | 59 defined(CPU_SA110) + defined(CPU_SA1100) + \ 60 defined(CPU_SA1110) + \ 61 defined(CPU_IXP12X0) + \ 62 defined(CPU_XSCALE_80200) + \ 63 defined(CPU_XSCALE_80321) + \ 64 defined(CPU_XSCALE_PXA2X0) + \ 65 defined(CPU_FA526) + \ 66 defined(CPU_FA626TE) + \ --- 18 unchanged lines hidden (view full) --- 85 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 86 defined(CPU_FA626TE)) 87#define ARM_ARCH_5 1 88#else 89#define ARM_ARCH_5 0 90#endif 91 92#if !defined(ARM_ARCH_6) |
| 92#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) | 93#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) |
| 93#define ARM_ARCH_6 1 94#else 95#define ARM_ARCH_6 0 96#endif 97#endif 98 99#if defined(CPU_CORTEXA) 100#define ARM_ARCH_7A 1 --- 43 unchanged lines hidden (view full) --- 144 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 145 defined(CPU_ARM10) || defined(CPU_FA526) || \ 146 defined(CPU_FA626TE)) 147#define ARM_MMU_GENERIC 1 148#else 149#define ARM_MMU_GENERIC 0 150#endif 151 | 94#define ARM_ARCH_6 1 95#else 96#define ARM_ARCH_6 0 97#endif 98#endif 99 100#if defined(CPU_CORTEXA) 101#define ARM_ARCH_7A 1 --- 43 unchanged lines hidden (view full) --- 145 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 146 defined(CPU_ARM10) || defined(CPU_FA526) || \ 147 defined(CPU_FA626TE)) 148#define ARM_MMU_GENERIC 1 149#else 150#define ARM_MMU_GENERIC 0 151#endif 152 |
| 152#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) | 153#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) |
| 153#define ARM_MMU_V6 1 154#else 155#define ARM_MMU_V6 0 156#endif 157 158#if defined(CPU_CORTEXA) 159#define ARM_MMU_V7 1 160#else --- 41 unchanged lines hidden --- | 154#define ARM_MMU_V6 1 155#else 156#define ARM_MMU_V6 0 157#endif 158 159#if defined(CPU_CORTEXA) 160#define ARM_MMU_V7 1 161#else --- 41 unchanged lines hidden --- |