1/* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 *
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37 * $FreeBSD: head/sys/arm/include/cpuconf.h 239268 2012-08-15 03:03:03Z gonzo $
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37 * $FreeBSD: head/sys/arm/include/cpuconf.h 244480 2012-12-20 04:32:02Z gonzo $ |
38 * 39 */ 40 41#ifndef _MACHINE_CPUCONF_H_ 42#define _MACHINE_CPUCONF_H_ 43 44/* 45 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 46 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 47 * YOU ARE ADDING SUPPORT FOR. 48 */ 49 50/* 51 * Step 1: Count the number of CPU types configured into the kernel. 52 */ 53#define CPU_NTYPES (defined(CPU_ARM7TDMI) + \ 54 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 55 defined(CPU_ARM9E) + \ 56 defined(CPU_ARM10) + \
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57 defined(CPU_ARM11) + \
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57 defined(CPU_ARM1136) + \ 58 defined(CPU_ARM1176) + \ |
59 defined(CPU_SA110) + defined(CPU_SA1100) + \ 60 defined(CPU_SA1110) + \ 61 defined(CPU_IXP12X0) + \ 62 defined(CPU_XSCALE_80200) + \ 63 defined(CPU_XSCALE_80321) + \ 64 defined(CPU_XSCALE_PXA2X0) + \ 65 defined(CPU_FA526) + \ 66 defined(CPU_FA626TE) + \ 67 defined(CPU_XSCALE_IXP425)) + \ 68 defined(CPU_CORTEXA) + \ 69 defined(CPU_MV_PJ4B) 70 71/* 72 * Step 2: Determine which ARM architecture versions are configured. 73 */ 74#if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 75 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 76 defined(CPU_IXP12X0) || defined(CPU_FA526)) 77#define ARM_ARCH_4 1 78#else 79#define ARM_ARCH_4 0 80#endif 81 82#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 83 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 84 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ 85 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 86 defined(CPU_FA626TE)) 87#define ARM_ARCH_5 1 88#else 89#define ARM_ARCH_5 0 90#endif 91 92#if !defined(ARM_ARCH_6)
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92#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B)
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93#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) |
94#define ARM_ARCH_6 1 95#else 96#define ARM_ARCH_6 0 97#endif 98#endif 99 100#if defined(CPU_CORTEXA) 101#define ARM_ARCH_7A 1 102#else 103#define ARM_ARCH_7A 0 104#endif 105 106#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A) 107#if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 108#error ARM_NARCH is 0 109#endif 110 111#if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7A 112/* 113 * We could support Thumb code on v4T, but the lack of clean interworking 114 * makes that hard. 115 */ 116#define THUMB_CODE 117#endif 118 119/* 120 * Step 3: Define which MMU classes are configured: 121 * 122 * ARM_MMU_MEMC Prehistoric, external memory controller 123 * and MMU for ARMv2 CPUs. 124 * 125 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 126 * 127 * ARM_MMU_V6 ARMv6 MMU. 128 * 129 * ARM_MMU_V7 ARMv7 MMU. 130 * 131 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 132 * ARM MMU, but has no write-through cache mode. 133 * 134 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 135 * MMU, but also has several extensions which 136 * require different PTE layout to use. 137 */ 138#if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 139#define ARM_MMU_MEMC 1 140#else 141#define ARM_MMU_MEMC 0 142#endif 143 144#if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 145 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 146 defined(CPU_ARM10) || defined(CPU_FA526) || \ 147 defined(CPU_FA626TE)) 148#define ARM_MMU_GENERIC 1 149#else 150#define ARM_MMU_GENERIC 0 151#endif 152
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152#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B)
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153#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) |
154#define ARM_MMU_V6 1 155#else 156#define ARM_MMU_V6 0 157#endif 158 159#if defined(CPU_CORTEXA) 160#define ARM_MMU_V7 1 161#else 162#define ARM_MMU_V7 0 163#endif 164 165#if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 166 defined(CPU_IXP12X0)) 167#define ARM_MMU_SA1 1 168#else 169#define ARM_MMU_SA1 0 170#endif 171 172#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 173 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 174 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) 175#define ARM_MMU_XSCALE 1 176#else 177#define ARM_MMU_XSCALE 0 178#endif 179 180#define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_V6 + \ 181 ARM_MMU_V7 + ARM_MMU_SA1 + ARM_MMU_XSCALE) 182#if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 183#error ARM_NMMUS is 0 184#endif 185 186/* 187 * Step 4: Define features that may be present on a subset of CPUs 188 * 189 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 190 */ 191 192#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 193 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) 194#define ARM_XSCALE_PMU 1 195#else 196#define ARM_XSCALE_PMU 0 197#endif 198 199#if defined(CPU_XSCALE_81342) 200#define CPU_XSCALE_CORE3 201#endif 202#endif /* _MACHINE_CPUCONF_H_ */
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