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cpu-v6.h (277415) cpu-v6.h (279811)
1/*-
2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 10 unchanged lines hidden (view full) ---

19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
1/*-
2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 10 unchanged lines hidden (view full) ---

19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/arm/include/cpu-v6.h 277415 2015-01-20 11:11:32Z andrew $
27 * $FreeBSD: head/sys/arm/include/cpu-v6.h 279811 2015-03-09 14:46:10Z ian $
28 */
29#ifndef MACHINE_CPU_V6_H
30#define MACHINE_CPU_V6_H
31
32#include "machine/atomic.h"
33#include "machine/cpufunc.h"
34#include "machine/cpuinfo.h"
35#include "machine/sysreg.h"
36
37
38#define CPU_ASID_KERNEL 0
39
28 */
29#ifndef MACHINE_CPU_V6_H
30#define MACHINE_CPU_V6_H
31
32#include "machine/atomic.h"
33#include "machine/cpufunc.h"
34#include "machine/cpuinfo.h"
35#include "machine/sysreg.h"
36
37
38#define CPU_ASID_KERNEL 0
39
40vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
41vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
42
40/*
41 * Macros to generate CP15 (system control processor) read/write functions.
42 */
43#define _FX(s...) #s
44
45#define _RF0(fname, aname...) \
46static __inline register_t \
47fname(void) \

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297/* Sync I and D caches to PoU */
298static __inline void
299icache_sync(vm_offset_t sva, vm_size_t size)
300{
301 vm_offset_t va;
302 vm_offset_t eva = sva + size;
303
304 dsb();
43/*
44 * Macros to generate CP15 (system control processor) read/write functions.
45 */
46#define _FX(s...) #s
47
48#define _RF0(fname, aname...) \
49static __inline register_t \
50fname(void) \

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300/* Sync I and D caches to PoU */
301static __inline void
302icache_sync(vm_offset_t sva, vm_size_t size)
303{
304 vm_offset_t va;
305 vm_offset_t eva = sva + size;
306
307 dsb();
305 for (va = sva; va < eva; va += arm_dcache_align) {
308 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
306#if __ARM_ARCH >= 7 && defined SMP
307 _CP15_DCCMVAU(va);
308#else
309 _CP15_DCCMVAC(va);
310#endif
311 }
312 dsb();
313#if __ARM_ARCH >= 7 && defined SMP

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327 _CP15_ICIALLUIS();
328#else
329 _CP15_ICIALLU();
330#endif
331 dsb();
332 isb();
333}
334
309#if __ARM_ARCH >= 7 && defined SMP
310 _CP15_DCCMVAU(va);
311#else
312 _CP15_DCCMVAC(va);
313#endif
314 }
315 dsb();
316#if __ARM_ARCH >= 7 && defined SMP

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330 _CP15_ICIALLUIS();
331#else
332 _CP15_ICIALLU();
333#endif
334 dsb();
335 isb();
336}
337
338/* Invalidate branch predictor buffer */
339static __inline void
340bpb_inv_all(void)
341{
342#if __ARM_ARCH >= 7 && defined SMP
343 _CP15_BPIALLIS();
344#else
345 _CP15_BPIALL();
346#endif
347 dsb();
348 isb();
349}
350
335/* Write back D-cache to PoU */
336static __inline void
337dcache_wb_pou(vm_offset_t sva, vm_size_t size)
338{
339 vm_offset_t va;
340 vm_offset_t eva = sva + size;
341
342 dsb();
351/* Write back D-cache to PoU */
352static __inline void
353dcache_wb_pou(vm_offset_t sva, vm_size_t size)
354{
355 vm_offset_t va;
356 vm_offset_t eva = sva + size;
357
358 dsb();
343 for (va = sva; va < eva; va += arm_dcache_align) {
359 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
344#if __ARM_ARCH >= 7 && defined SMP
345 _CP15_DCCMVAU(va);
346#else
347 _CP15_DCCMVAC(va);
348#endif
349 }
350 dsb();
351}
352
353/* Invalidate D-cache to PoC */
354static __inline void
355dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
356{
357 vm_offset_t va;
358 vm_offset_t eva = sva + size;
359
360 /* invalidate L1 first */
360#if __ARM_ARCH >= 7 && defined SMP
361 _CP15_DCCMVAU(va);
362#else
363 _CP15_DCCMVAC(va);
364#endif
365 }
366 dsb();
367}
368
369/* Invalidate D-cache to PoC */
370static __inline void
371dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
372{
373 vm_offset_t va;
374 vm_offset_t eva = sva + size;
375
376 /* invalidate L1 first */
361 for (va = sva; va < eva; va += arm_dcache_align) {
377 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
362 _CP15_DCIMVAC(va);
363 }
364 dsb();
365
366 /* then L2 */
367 cpu_l2cache_inv_range(pa, size);
368 dsb();
369
370 /* then L1 again */
378 _CP15_DCIMVAC(va);
379 }
380 dsb();
381
382 /* then L2 */
383 cpu_l2cache_inv_range(pa, size);
384 dsb();
385
386 /* then L1 again */
371 for (va = sva; va < eva; va += arm_dcache_align) {
387 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
372 _CP15_DCIMVAC(va);
373 }
374 dsb();
375}
376
377/* Write back D-cache to PoC */
378static __inline void
379dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
380{
381 vm_offset_t va;
382 vm_offset_t eva = sva + size;
383
384 dsb();
385
388 _CP15_DCIMVAC(va);
389 }
390 dsb();
391}
392
393/* Write back D-cache to PoC */
394static __inline void
395dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
396{
397 vm_offset_t va;
398 vm_offset_t eva = sva + size;
399
400 dsb();
401
386 for (va = sva; va < eva; va += arm_dcache_align) {
402 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
387 _CP15_DCCMVAC(va);
388 }
389 dsb();
390
391 cpu_l2cache_wb_range(pa, size);
392}
393
394/* Write back and invalidate D-cache to PoC */
395static __inline void
396dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
397{
398 vm_offset_t va;
399 vm_offset_t eva = sva + size;
400
401 dsb();
402
403 /* write back L1 first */
403 _CP15_DCCMVAC(va);
404 }
405 dsb();
406
407 cpu_l2cache_wb_range(pa, size);
408}
409
410/* Write back and invalidate D-cache to PoC */
411static __inline void
412dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
413{
414 vm_offset_t va;
415 vm_offset_t eva = sva + size;
416
417 dsb();
418
419 /* write back L1 first */
404 for (va = sva; va < eva; va += arm_dcache_align) {
420 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
405 _CP15_DCCMVAC(va);
406 }
407 dsb();
408
409 /* then write back and invalidate L2 */
410 cpu_l2cache_wbinv_range(pa, size);
411
412 /* then invalidate L1 */
421 _CP15_DCCMVAC(va);
422 }
423 dsb();
424
425 /* then write back and invalidate L2 */
426 cpu_l2cache_wbinv_range(pa, size);
427
428 /* then invalidate L1 */
413 for (va = sva; va < eva; va += arm_dcache_align) {
429 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
414 _CP15_DCIMVAC(va);
415 }
416 dsb();
417}
418
419/* Set TTB0 register */
420static __inline void
421cp15_ttbr_set(uint32_t reg)
422{
423 dsb();
424 _CP15_TTB_SET(reg);
425 dsb();
426 _CP15_BPIALL();
427 dsb();
428 isb();
429 tlb_flush_all_ng_local();
430}
431
432#endif /* !MACHINE_CPU_V6_H */
430 _CP15_DCIMVAC(va);
431 }
432 dsb();
433}
434
435/* Set TTB0 register */
436static __inline void
437cp15_ttbr_set(uint32_t reg)
438{
439 dsb();
440 _CP15_TTB_SET(reg);
441 dsb();
442 _CP15_BPIALL();
443 dsb();
444 isb();
445 tlb_flush_all_ng_local();
446}
447
448#endif /* !MACHINE_CPU_V6_H */