1/*-
2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/arm/include/cpu-v6.h 277415 2015-01-20 11:11:32Z andrew $
28 */
29#ifndef MACHINE_CPU_V6_H
30#define MACHINE_CPU_V6_H
31
32#include "machine/atomic.h"
33#include "machine/cpufunc.h"
34#include "machine/cpuinfo.h"
35#include "machine/sysreg.h"
36
37
38#define CPU_ASID_KERNEL 0
39
40/*
41 * Macros to generate CP15 (system control processor) read/write functions.
42 */
43#define _FX(s...) #s
44
45#define _RF0(fname, aname...) \
46static __inline register_t \
47fname(void) \

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297/* Sync I and D caches to PoU */
298static __inline void
299icache_sync(vm_offset_t sva, vm_size_t size)
300{
301 vm_offset_t va;
302 vm_offset_t eva = sva + size;
303
304 dsb();
305 for (va = sva; va < eva; va += arm_dcache_align) {
306#if __ARM_ARCH >= 7 && defined SMP
307 _CP15_DCCMVAU(va);
308#else
309 _CP15_DCCMVAC(va);
310#endif
311 }
312 dsb();
313#if __ARM_ARCH >= 7 && defined SMP

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327 _CP15_ICIALLUIS();
328#else
329 _CP15_ICIALLU();
330#endif
331 dsb();
332 isb();
333}
334
335/* Write back D-cache to PoU */
336static __inline void
337dcache_wb_pou(vm_offset_t sva, vm_size_t size)
338{
339 vm_offset_t va;
340 vm_offset_t eva = sva + size;
341
342 dsb();
343 for (va = sva; va < eva; va += arm_dcache_align) {
344#if __ARM_ARCH >= 7 && defined SMP
345 _CP15_DCCMVAU(va);
346#else
347 _CP15_DCCMVAC(va);
348#endif
349 }
350 dsb();
351}
352
353/* Invalidate D-cache to PoC */
354static __inline void
355dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
356{
357 vm_offset_t va;
358 vm_offset_t eva = sva + size;
359
360 /* invalidate L1 first */
361 for (va = sva; va < eva; va += arm_dcache_align) {
362 _CP15_DCIMVAC(va);
363 }
364 dsb();
365
366 /* then L2 */
367 cpu_l2cache_inv_range(pa, size);
368 dsb();
369
370 /* then L1 again */
371 for (va = sva; va < eva; va += arm_dcache_align) {
372 _CP15_DCIMVAC(va);
373 }
374 dsb();
375}
376
377/* Write back D-cache to PoC */
378static __inline void
379dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
380{
381 vm_offset_t va;
382 vm_offset_t eva = sva + size;
383
384 dsb();
385
386 for (va = sva; va < eva; va += arm_dcache_align) {
387 _CP15_DCCMVAC(va);
388 }
389 dsb();
390
391 cpu_l2cache_wb_range(pa, size);
392}
393
394/* Write back and invalidate D-cache to PoC */
395static __inline void
396dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
397{
398 vm_offset_t va;
399 vm_offset_t eva = sva + size;
400
401 dsb();
402
403 /* write back L1 first */
404 for (va = sva; va < eva; va += arm_dcache_align) {
405 _CP15_DCCMVAC(va);
406 }
407 dsb();
408
409 /* then write back and invalidate L2 */
410 cpu_l2cache_wbinv_range(pa, size);
411
412 /* then invalidate L1 */
413 for (va = sva; va < eva; va += arm_dcache_align) {
414 _CP15_DCIMVAC(va);
415 }
416 dsb();
417}
418
419/* Set TTB0 register */
420static __inline void
421cp15_ttbr_set(uint32_t reg)
422{
423 dsb();
424 _CP15_TTB_SET(reg);
425 dsb();
426 _CP15_BPIALL();
427 dsb();
428 isb();
429 tlb_flush_all_ng_local();
430}
431
432#endif /* !MACHINE_CPU_V6_H */