| armreg.h (244480) | armreg.h (249999) |
|---|---|
| 1/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * --- 21 unchanged lines hidden (view full) --- 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * | 1/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * --- 21 unchanged lines hidden (view full) --- 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * |
| 38 * $FreeBSD: head/sys/arm/include/armreg.h 244480 2012-12-20 04:32:02Z gonzo $ | 38 * $FreeBSD: head/sys/arm/include/armreg.h 249999 2013-04-27 23:07:49Z wkoszek $ |
| 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43 44#define INSN_SIZE 4 45#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46#define PSR_MODE 0x0000001f /* mode mask */ --- 100 unchanged lines hidden (view full) --- 147#define CPU_ID_ARM1136JS 0x4107b360 148#define CPU_ID_ARM1136JSR1 0x4117b360 149#define CPU_ID_ARM1176JZS 0x410fb760 150#define CPU_ID_CORTEXA8R1 0x411fc080 151#define CPU_ID_CORTEXA8R2 0x412fc080 152#define CPU_ID_CORTEXA8R3 0x413fc080 153#define CPU_ID_CORTEXA9R1 0x411fc090 154#define CPU_ID_CORTEXA9R2 0x412fc090 | 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43 44#define INSN_SIZE 4 45#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46#define PSR_MODE 0x0000001f /* mode mask */ --- 100 unchanged lines hidden (view full) --- 147#define CPU_ID_ARM1136JS 0x4107b360 148#define CPU_ID_ARM1136JSR1 0x4117b360 149#define CPU_ID_ARM1176JZS 0x410fb760 150#define CPU_ID_CORTEXA8R1 0x411fc080 151#define CPU_ID_CORTEXA8R2 0x412fc080 152#define CPU_ID_CORTEXA8R3 0x413fc080 153#define CPU_ID_CORTEXA9R1 0x411fc090 154#define CPU_ID_CORTEXA9R2 0x412fc090 |
| 155#define CPU_ID_CORTEXA9R3 0x413fc090 |
|
| 155#define CPU_ID_SA110 0x4401a100 156#define CPU_ID_SA1100 0x4401a110 157#define CPU_ID_TI925T 0x54029250 158#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 159#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 160#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 161 162/* --- 271 unchanged lines hidden --- | 156#define CPU_ID_SA110 0x4401a100 157#define CPU_ID_SA1100 0x4401a110 158#define CPU_ID_TI925T 0x54029250 159#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 160#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 161#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 162 163/* --- 271 unchanged lines hidden --- |