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uart_dev_at91usart.c (164969) uart_dev_at91usart.c (166100)
1/*-
2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/arm/at91/uart_dev_at91usart.c 164969 2006-12-07 00:24:15Z cognet $");
29__FBSDID("$FreeBSD: head/sys/arm/at91/uart_dev_at91usart.c 166100 2007-01-18 22:01:19Z marius $");
30
31#include "opt_comconsole.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/conf.h>
37#include <sys/cons.h>
38#include <sys/tty.h>
39#include <machine/bus.h>
40
41#include <dev/uart/uart.h>
42#include <dev/uart/uart_cpu.h>
43#include <dev/uart/uart_bus.h>
44#include <arm/at91/at91rm92reg.h>
45#include <arm/at91/at91_usartreg.h>
46#include <arm/at91/at91_pdcreg.h>
47
48#include "uart_if.h"
49
50#define DEFAULT_RCLK AT91C_MASTER_CLOCK
51#define USART_BUFFER_SIZE 128
52
53/*
54 * High-level UART interface.
55 */
56struct at91_usart_rx {
57 bus_addr_t pa;
58 uint8_t buffer[USART_BUFFER_SIZE];
59 bus_dmamap_t map;
60};
61
62struct at91_usart_softc {
63 struct uart_softc base;
64 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
65 bus_dmamap_t tx_map;
66 uint32_t flags;
67#define HAS_TIMEOUT 1
68 struct at91_usart_rx ping_pong[2];
69 struct at91_usart_rx *ping;
70 struct at91_usart_rx *pong;
71};
72
73#define RD4(bas, reg) \
74 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
75#define WR4(bas, reg, value) \
76 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
77
78#define SIGCHG(c, i, s, d) \
79 do { \
80 if (c) { \
81 i |= (i & s) ? s : s | d; \
82 } else { \
83 i = (i & s) ? (i & ~s) | d : i; \
84 } \
85 } while (0);
86
87#define BAUD2DIVISOR(b) \
88 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
89
90/*
91 * Low-level UART interface.
92 */
93static int at91_usart_probe(struct uart_bas *bas);
94static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
95static void at91_usart_term(struct uart_bas *bas);
96static void at91_usart_putc(struct uart_bas *bas, int);
30
31#include "opt_comconsole.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/conf.h>
37#include <sys/cons.h>
38#include <sys/tty.h>
39#include <machine/bus.h>
40
41#include <dev/uart/uart.h>
42#include <dev/uart/uart_cpu.h>
43#include <dev/uart/uart_bus.h>
44#include <arm/at91/at91rm92reg.h>
45#include <arm/at91/at91_usartreg.h>
46#include <arm/at91/at91_pdcreg.h>
47
48#include "uart_if.h"
49
50#define DEFAULT_RCLK AT91C_MASTER_CLOCK
51#define USART_BUFFER_SIZE 128
52
53/*
54 * High-level UART interface.
55 */
56struct at91_usart_rx {
57 bus_addr_t pa;
58 uint8_t buffer[USART_BUFFER_SIZE];
59 bus_dmamap_t map;
60};
61
62struct at91_usart_softc {
63 struct uart_softc base;
64 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
65 bus_dmamap_t tx_map;
66 uint32_t flags;
67#define HAS_TIMEOUT 1
68 struct at91_usart_rx ping_pong[2];
69 struct at91_usart_rx *ping;
70 struct at91_usart_rx *pong;
71};
72
73#define RD4(bas, reg) \
74 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
75#define WR4(bas, reg, value) \
76 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
77
78#define SIGCHG(c, i, s, d) \
79 do { \
80 if (c) { \
81 i |= (i & s) ? s : s | d; \
82 } else { \
83 i = (i & s) ? (i & ~s) | d : i; \
84 } \
85 } while (0);
86
87#define BAUD2DIVISOR(b) \
88 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
89
90/*
91 * Low-level UART interface.
92 */
93static int at91_usart_probe(struct uart_bas *bas);
94static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
95static void at91_usart_term(struct uart_bas *bas);
96static void at91_usart_putc(struct uart_bas *bas, int);
97static int at91_usart_poll(struct uart_bas *bas);
97static int at91_usart_rxready(struct uart_bas *bas);
98static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx);
99
100extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
101
102static int
103at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
104 int stopbits, int parity)
105{
106 uint32_t mr;
107
108 /*
109 * Assume 3-write RS-232 configuration.
110 * XXX Not sure how uart will present the other modes to us, so
111 * XXX they are unimplemented. maybe ioctl?
112 */
113 mr = USART_MR_MODE_NORMAL;
114 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
115
116 /*
117 * Or in the databits requested
118 */
119 if (databits < 9)
120 mr &= ~USART_MR_MODE9;
121 switch (databits) {
122 case 5:
123 mr |= USART_MR_CHRL_5BITS;
124 break;
125 case 6:
126 mr |= USART_MR_CHRL_6BITS;
127 break;
128 case 7:
129 mr |= USART_MR_CHRL_7BITS;
130 break;
131 case 8:
132 mr |= USART_MR_CHRL_8BITS;
133 break;
134 case 9:
135 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
136 break;
137 default:
138 return (EINVAL);
139 }
140
141 /*
142 * Or in the parity
143 */
144 switch (parity) {
145 case UART_PARITY_NONE:
146 mr |= USART_MR_PAR_NONE;
147 break;
148 case UART_PARITY_ODD:
149 mr |= USART_MR_PAR_ODD;
150 break;
151 case UART_PARITY_EVEN:
152 mr |= USART_MR_PAR_EVEN;
153 break;
154 case UART_PARITY_MARK:
155 mr |= USART_MR_PAR_MARK;
156 break;
157 case UART_PARITY_SPACE:
158 mr |= USART_MR_PAR_SPACE;
159 break;
160 default:
161 return (EINVAL);
162 }
163
164 /*
165 * Or in the stop bits. Note: The hardware supports 1.5 stop
166 * bits in async mode, but there's no way to specify that
167 * AFAICT. Instead, rely on the convention documented at
168 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
169 * states that 1.5 stop bits are used for 5 bit bytes and
170 * 2 stop bits only for longer bytes.
171 */
172 if (stopbits == 1)
173 mr |= USART_MR_NBSTOP_1;
174 else if (databits > 5)
175 mr |= USART_MR_NBSTOP_2;
176 else
177 mr |= USART_MR_NBSTOP_1_5;
178
179 /*
180 * We want normal plumbing mode too, none of this fancy
181 * loopback or echo mode.
182 */
183 mr |= USART_MR_CHMODE_NORMAL;
184
185 mr &= ~USART_MR_MSBF; /* lsb first */
186 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
187
188 WR4(bas, USART_MR, mr);
189
190 /*
191 * Set the baud rate
192 */
193 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
194
195 /* XXX Need to take possible synchronous mode into account */
196 return (0);
197}
198
199struct uart_ops at91_usart_ops = {
200 .probe = at91_usart_probe,
201 .init = at91_usart_init,
202 .term = at91_usart_term,
203 .putc = at91_usart_putc,
98static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx);
99
100extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
101
102static int
103at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
104 int stopbits, int parity)
105{
106 uint32_t mr;
107
108 /*
109 * Assume 3-write RS-232 configuration.
110 * XXX Not sure how uart will present the other modes to us, so
111 * XXX they are unimplemented. maybe ioctl?
112 */
113 mr = USART_MR_MODE_NORMAL;
114 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
115
116 /*
117 * Or in the databits requested
118 */
119 if (databits < 9)
120 mr &= ~USART_MR_MODE9;
121 switch (databits) {
122 case 5:
123 mr |= USART_MR_CHRL_5BITS;
124 break;
125 case 6:
126 mr |= USART_MR_CHRL_6BITS;
127 break;
128 case 7:
129 mr |= USART_MR_CHRL_7BITS;
130 break;
131 case 8:
132 mr |= USART_MR_CHRL_8BITS;
133 break;
134 case 9:
135 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
136 break;
137 default:
138 return (EINVAL);
139 }
140
141 /*
142 * Or in the parity
143 */
144 switch (parity) {
145 case UART_PARITY_NONE:
146 mr |= USART_MR_PAR_NONE;
147 break;
148 case UART_PARITY_ODD:
149 mr |= USART_MR_PAR_ODD;
150 break;
151 case UART_PARITY_EVEN:
152 mr |= USART_MR_PAR_EVEN;
153 break;
154 case UART_PARITY_MARK:
155 mr |= USART_MR_PAR_MARK;
156 break;
157 case UART_PARITY_SPACE:
158 mr |= USART_MR_PAR_SPACE;
159 break;
160 default:
161 return (EINVAL);
162 }
163
164 /*
165 * Or in the stop bits. Note: The hardware supports 1.5 stop
166 * bits in async mode, but there's no way to specify that
167 * AFAICT. Instead, rely on the convention documented at
168 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
169 * states that 1.5 stop bits are used for 5 bit bytes and
170 * 2 stop bits only for longer bytes.
171 */
172 if (stopbits == 1)
173 mr |= USART_MR_NBSTOP_1;
174 else if (databits > 5)
175 mr |= USART_MR_NBSTOP_2;
176 else
177 mr |= USART_MR_NBSTOP_1_5;
178
179 /*
180 * We want normal plumbing mode too, none of this fancy
181 * loopback or echo mode.
182 */
183 mr |= USART_MR_CHMODE_NORMAL;
184
185 mr &= ~USART_MR_MSBF; /* lsb first */
186 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
187
188 WR4(bas, USART_MR, mr);
189
190 /*
191 * Set the baud rate
192 */
193 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
194
195 /* XXX Need to take possible synchronous mode into account */
196 return (0);
197}
198
199struct uart_ops at91_usart_ops = {
200 .probe = at91_usart_probe,
201 .init = at91_usart_init,
202 .term = at91_usart_term,
203 .putc = at91_usart_putc,
204 .poll = at91_usart_poll,
204 .rxready = at91_usart_rxready,
205 .getc = at91_usart_getc,
206};
207
208static int
209at91_usart_probe(struct uart_bas *bas)
210{
211 /* We know that this is always here */
212 return (0);
213}
214
215/*
216 * Initialize this device for use as a console.
217 */
218static void
219at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
220 int parity)
221{
222
223 at91_usart_param(bas, baudrate, databits, stopbits, parity);
224
225 /* Reset the rx and tx buffers and turn on rx and tx */
226 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
227 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
228 WR4(bas, USART_IDR, 0xffffffff);
229}
230
231/*
232 * Free resources now that we're no longer the console. This appears to
233 * be never called, and I'm unsure quite what to do if I am called.
234 */
235static void
236at91_usart_term(struct uart_bas *bas)
237{
238 /* XXX */
239}
240
241/*
242 * Put a character of console output (so we do it here polling rather than
243 * interrutp driven).
244 */
245static void
246at91_usart_putc(struct uart_bas *bas, int c)
247{
248
249 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
250 continue;
251 WR4(bas, USART_THR, c);
252}
253
254/*
205 .getc = at91_usart_getc,
206};
207
208static int
209at91_usart_probe(struct uart_bas *bas)
210{
211 /* We know that this is always here */
212 return (0);
213}
214
215/*
216 * Initialize this device for use as a console.
217 */
218static void
219at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
220 int parity)
221{
222
223 at91_usart_param(bas, baudrate, databits, stopbits, parity);
224
225 /* Reset the rx and tx buffers and turn on rx and tx */
226 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
227 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
228 WR4(bas, USART_IDR, 0xffffffff);
229}
230
231/*
232 * Free resources now that we're no longer the console. This appears to
233 * be never called, and I'm unsure quite what to do if I am called.
234 */
235static void
236at91_usart_term(struct uart_bas *bas)
237{
238 /* XXX */
239}
240
241/*
242 * Put a character of console output (so we do it here polling rather than
243 * interrutp driven).
244 */
245static void
246at91_usart_putc(struct uart_bas *bas, int c)
247{
248
249 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
250 continue;
251 WR4(bas, USART_THR, c);
252}
253
254/*
255 * Poll for a character available
255 * Check for a character available.
256 */
257static int
256 */
257static int
258at91_usart_poll(struct uart_bas *bas)
258at91_usart_rxready(struct uart_bas *bas)
259{
260
259{
260
261 if (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
262 return (-1);
263 return (RD4(bas, USART_RHR) & 0xff);
261 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
264}
265
266/*
267 * Block waiting for a character.
268 */
269static int
270at91_usart_getc(struct uart_bas *bas, struct mtx *mtx)
271{
272 int c;
273
274 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
275 continue;
276 c = RD4(bas, USART_RHR);
277 c &= 0xff;
278 return (c);
279}
280
281static int at91_usart_bus_probe(struct uart_softc *sc);
282static int at91_usart_bus_attach(struct uart_softc *sc);
283static int at91_usart_bus_flush(struct uart_softc *, int);
284static int at91_usart_bus_getsig(struct uart_softc *);
285static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
286static int at91_usart_bus_ipend(struct uart_softc *);
287static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
288static int at91_usart_bus_receive(struct uart_softc *);
289static int at91_usart_bus_setsig(struct uart_softc *, int);
290static int at91_usart_bus_transmit(struct uart_softc *);
291
292static kobj_method_t at91_usart_methods[] = {
293 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
294 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
295 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
296 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
297 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
298 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
299 KOBJMETHOD(uart_param, at91_usart_bus_param),
300 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
301 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
302 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
303
304 { 0, 0 }
305};
306
307int
308at91_usart_bus_probe(struct uart_softc *sc)
309{
310 return (0);
311}
312
313#ifndef SKYEYE_WORKAROUNDS
314static void
315at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
316{
317 if (error != 0)
318 return;
319 *(bus_addr_t *)arg = segs[0].ds_addr;
320}
321#endif
322
323static int
324at91_usart_bus_attach(struct uart_softc *sc)
325{
326#ifndef SKYEYE_WORKAROUNDS
327 int err;
328 int i;
329#endif
330 uint32_t cr;
331 struct at91_usart_softc *atsc;
332
333 atsc = (struct at91_usart_softc *)sc;
334
335 /*
336 * See if we have a TIMEOUT bit. We disable all interrupts as
337 * a side effect. Boot loaders may have enabled them. Since
338 * a TIMEOUT interrupt can't happen without other setup, the
339 * apparent race here can't actually happen.
340 */
341 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
342 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
343 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
344 atsc->flags |= HAS_TIMEOUT;
345 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
346
347 sc->sc_txfifosz = USART_BUFFER_SIZE;
348 sc->sc_rxfifosz = USART_BUFFER_SIZE;
349 sc->sc_hwiflow = 0;
350
351#ifndef SKYEYE_WORKAROUNDS
352 /*
353 * Allocate DMA tags and maps
354 */
355 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
356 BUS_SPACE_MAXADDR, NULL, NULL, USART_BUFFER_SIZE, 1,
357 USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &atsc->dmatag);
358 if (err != 0)
359 goto errout;
360 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
361 if (err != 0)
362 goto errout;
363 if (atsc->flags & HAS_TIMEOUT) {
364 for (i = 0; i < 2; i++) {
365 err = bus_dmamap_create(atsc->dmatag, 0,
366 &atsc->ping_pong[i].map);
367 if (err != 0)
368 goto errout;
369 err = bus_dmamap_load(atsc->dmatag,
370 atsc->ping_pong[i].map,
371 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
372 at91_getaddr, &atsc->ping_pong[i].pa, 0);
373 if (err != 0)
374 goto errout;
375 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
376 BUS_DMASYNC_PREREAD);
377 }
378 atsc->ping = &atsc->ping_pong[0];
379 atsc->pong = &atsc->ping_pong[1];
380 }
381#endif
382
383 /*
384 * Prime the pump with the RX buffer. We use two 64 byte bounce
385 * buffers here to avoid data overflow.
386 */
387
388 /* Turn on rx and tx */
389 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
390 WR4(&sc->sc_bas, USART_CR, cr);
391 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
392
393 /*
394 * Setup the PDC to receive data. We use the ping-pong buffers
395 * so that we can more easily bounce between the two and so that
396 * we get an interrupt 1/2 way through the software 'fifo' we have
397 * to avoid overruns.
398 */
399 if (atsc->flags & HAS_TIMEOUT) {
400 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
401 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
402 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
403 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
404 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
405
406 /* Set the receive timeout to be 1.5 character times. */
407 WR4(&sc->sc_bas, USART_RTOR, 12);
408 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
409 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
410 USART_CSR_RXBUFF | USART_CSR_ENDRX);
411 } else {
412 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
413 }
414 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
415#ifndef SKYEYE_WORKAROUNDS
416errout:;
417 // XXX bad
418 return (err);
419#else
420 return (0);
421#endif
422}
423
424static int
425at91_usart_bus_transmit(struct uart_softc *sc)
426{
427#ifndef SKYEYE_WORKAROUNDS
428 bus_addr_t addr;
429#endif
430 struct at91_usart_softc *atsc;
431
432 atsc = (struct at91_usart_softc *)sc;
433#ifndef SKYEYE_WORKAROUNDS
434 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
435 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
436 return (EAGAIN);
437 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
438#endif
439
440 uart_lock(sc->sc_hwmtx);
441 sc->sc_txbusy = 1;
442#ifndef SKYEYE_WORKAROUNDS
443 /*
444 * Setup the PDC to transfer the data and interrupt us when it
445 * is done. We've already requested the interrupt.
446 */
447 WR4(&sc->sc_bas, PDC_TPR, addr);
448 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
449 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
450 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
451 uart_unlock(sc->sc_hwmtx);
452#else
453 for (int i = 0; i < sc->sc_txdatasz; i++)
454 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
455 /*
456 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the
457 * transfer is done, so simulate it.
458 */
459 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY);
460#endif
461 return (0);
462}
463static int
464at91_usart_bus_setsig(struct uart_softc *sc, int sig)
465{
466 uint32_t new, old, cr;
467 struct uart_bas *bas;
468
469 do {
470 old = sc->sc_hwsig;
471 new = old;
472 if (sig & SER_DDTR)
473 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
474 if (sig & SER_DRTS)
475 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
476 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
477 bas = &sc->sc_bas;
478 uart_lock(sc->sc_hwmtx);
479 cr = 0;
480 if (new & SER_DTR)
481 cr |= USART_CR_DTREN;
482 else
483 cr |= USART_CR_DTRDIS;
484 if (new & SER_RTS)
485 cr |= USART_CR_RTSEN;
486 else
487 cr |= USART_CR_RTSDIS;
488 WR4(bas, USART_CR, cr);
489 uart_unlock(sc->sc_hwmtx);
490 return (0);
491}
492static int
493at91_usart_bus_receive(struct uart_softc *sc)
494{
495
496 return (0);
497}
498static int
499at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
500 int stopbits, int parity)
501{
502
503 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
504 parity));
505}
506
507static __inline void
508at91_rx_put(struct uart_softc *sc, int key)
509{
510#if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER)
511 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
512 if (kdb_alt_break(key, &sc->sc_altbrk))
513 kdb_enter("Break sequence to console");
514 }
515#endif
516 uart_rx_put(sc, key);
517}
518
519static int
520at91_usart_bus_ipend(struct uart_softc *sc)
521{
522 int csr = RD4(&sc->sc_bas, USART_CSR);
523 int ipend = 0, i, len;
524 struct at91_usart_softc *atsc;
525 struct at91_usart_rx *p;
526
527 atsc = (struct at91_usart_softc *)sc;
528 if (csr & USART_CSR_ENDTX) {
529 bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
530 BUS_DMASYNC_POSTWRITE);
531 bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
532 }
533 uart_lock(sc->sc_hwmtx);
534 if (csr & USART_CSR_TXRDY) {
535 if (sc->sc_txbusy)
536 ipend |= SER_INT_TXIDLE;
537 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
538 }
539 if (csr & USART_CSR_ENDTX) {
540 if (sc->sc_txbusy)
541 ipend |= SER_INT_TXIDLE;
542 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
543 }
544
545 /*
546 * Due to the contraints of the DMA engine present in the
547 * atmel chip, I can't just say I have a rx interrupt pending
548 * and do all the work elsewhere. I need to look at the CSR
549 * bits right now and do things based on them to avoid races.
550 */
551 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
552 // Have a buffer overflow. Copy all data from both
553 // ping and pong. Insert overflow character. Reset
554 // ping and pong and re-enable the PDC to receive
555 // characters again.
556 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
557 BUS_DMASYNC_POSTREAD);
558 bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
559 BUS_DMASYNC_POSTREAD);
560 for (i = 0; i < sc->sc_rxfifosz; i++)
561 at91_rx_put(sc, atsc->ping->buffer[i]);
562 for (i = 0; i < sc->sc_rxfifosz; i++)
563 at91_rx_put(sc, atsc->pong->buffer[i]);
564 uart_rx_put(sc, UART_STAT_OVERRUN);
565 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
566 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
567 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
568 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
569 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
570 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
571 ipend |= SER_INT_RXREADY;
572 }
573 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
574 // Shuffle data from 'ping' of ping pong buffer, but
575 // leave current 'pong' in place, as it has become the
576 // new 'ping'. We need to copy data and setup the old
577 // 'ping' as the new 'pong' when we're done.
578 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
579 BUS_DMASYNC_POSTREAD);
580 for (i = 0; i < sc->sc_rxfifosz; i++)
581 at91_rx_put(sc, atsc->ping->buffer[i]);
582 p = atsc->ping;
583 atsc->ping = atsc->pong;
584 atsc->pong = p;
585 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
586 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
587 ipend |= SER_INT_RXREADY;
588 }
589 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
590 // We have one partial buffer. We need to stop the
591 // PDC, get the number of characters left and from
592 // that compute number of valid characters. We then
593 // need to reset ping and pong and reenable the PDC.
594 // Not sure if there's a race here at fast baud rates
595 // we need to worry about.
596 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
597 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
598 BUS_DMASYNC_POSTREAD);
599 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
600 for (i = 0; i < len; i++)
601 at91_rx_put(sc, atsc->ping->buffer[i]);
602 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
603 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
604 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
605 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
606 ipend |= SER_INT_RXREADY;
607 }
608 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
609 // We have another charater in a device that doesn't support
610 // timeouts, so we do it one character at a time.
611 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
612 ipend |= SER_INT_RXREADY;
613 }
614
615 if (csr & USART_CSR_RXBRK) {
616 unsigned int cr = USART_CR_RSTSTA;
617
618 ipend |= SER_INT_BREAK;
619 WR4(&sc->sc_bas, USART_CR, cr);
620 }
621 uart_unlock(sc->sc_hwmtx);
622 return (ipend);
623}
624static int
625at91_usart_bus_flush(struct uart_softc *sc, int what)
626{
627 return (0);
628}
629
630static int
631at91_usart_bus_getsig(struct uart_softc *sc)
632{
633 uint32_t new, sig;
634 uint8_t csr;
635
636 uart_lock(sc->sc_hwmtx);
637 csr = RD4(&sc->sc_bas, USART_CSR);
638 sig = 0;
639 if (csr & USART_CSR_CTS)
640 sig |= SER_CTS;
641 if (csr & USART_CSR_DCD)
642 sig |= SER_DCD;
643 if (csr & USART_CSR_DSR)
644 sig |= SER_DSR;
645 if (csr & USART_CSR_RI)
646 sig |= SER_RI;
647 new = sig & ~SER_MASK_DELTA;
648 sc->sc_hwsig = new;
649 uart_unlock(sc->sc_hwmtx);
650 return (sig);
651}
652
653static int
654at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
655{
656 switch (request) {
657 case UART_IOCTL_BREAK:
658 case UART_IOCTL_IFLOW:
659 case UART_IOCTL_OFLOW:
660 break;
661 case UART_IOCTL_BAUD:
662 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data));
663 return (0);
664 }
665 return (EINVAL);
666}
667struct uart_class at91_usart_class = {
668 "at91_usart class",
669 at91_usart_methods,
670 sizeof(struct at91_usart_softc),
671 .uc_range = 8,
672 .uc_rclk = DEFAULT_RCLK
673};
262}
263
264/*
265 * Block waiting for a character.
266 */
267static int
268at91_usart_getc(struct uart_bas *bas, struct mtx *mtx)
269{
270 int c;
271
272 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
273 continue;
274 c = RD4(bas, USART_RHR);
275 c &= 0xff;
276 return (c);
277}
278
279static int at91_usart_bus_probe(struct uart_softc *sc);
280static int at91_usart_bus_attach(struct uart_softc *sc);
281static int at91_usart_bus_flush(struct uart_softc *, int);
282static int at91_usart_bus_getsig(struct uart_softc *);
283static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
284static int at91_usart_bus_ipend(struct uart_softc *);
285static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
286static int at91_usart_bus_receive(struct uart_softc *);
287static int at91_usart_bus_setsig(struct uart_softc *, int);
288static int at91_usart_bus_transmit(struct uart_softc *);
289
290static kobj_method_t at91_usart_methods[] = {
291 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
292 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
293 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
294 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
295 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
296 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
297 KOBJMETHOD(uart_param, at91_usart_bus_param),
298 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
299 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
300 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
301
302 { 0, 0 }
303};
304
305int
306at91_usart_bus_probe(struct uart_softc *sc)
307{
308 return (0);
309}
310
311#ifndef SKYEYE_WORKAROUNDS
312static void
313at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
314{
315 if (error != 0)
316 return;
317 *(bus_addr_t *)arg = segs[0].ds_addr;
318}
319#endif
320
321static int
322at91_usart_bus_attach(struct uart_softc *sc)
323{
324#ifndef SKYEYE_WORKAROUNDS
325 int err;
326 int i;
327#endif
328 uint32_t cr;
329 struct at91_usart_softc *atsc;
330
331 atsc = (struct at91_usart_softc *)sc;
332
333 /*
334 * See if we have a TIMEOUT bit. We disable all interrupts as
335 * a side effect. Boot loaders may have enabled them. Since
336 * a TIMEOUT interrupt can't happen without other setup, the
337 * apparent race here can't actually happen.
338 */
339 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
340 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
341 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
342 atsc->flags |= HAS_TIMEOUT;
343 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
344
345 sc->sc_txfifosz = USART_BUFFER_SIZE;
346 sc->sc_rxfifosz = USART_BUFFER_SIZE;
347 sc->sc_hwiflow = 0;
348
349#ifndef SKYEYE_WORKAROUNDS
350 /*
351 * Allocate DMA tags and maps
352 */
353 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
354 BUS_SPACE_MAXADDR, NULL, NULL, USART_BUFFER_SIZE, 1,
355 USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &atsc->dmatag);
356 if (err != 0)
357 goto errout;
358 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
359 if (err != 0)
360 goto errout;
361 if (atsc->flags & HAS_TIMEOUT) {
362 for (i = 0; i < 2; i++) {
363 err = bus_dmamap_create(atsc->dmatag, 0,
364 &atsc->ping_pong[i].map);
365 if (err != 0)
366 goto errout;
367 err = bus_dmamap_load(atsc->dmatag,
368 atsc->ping_pong[i].map,
369 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
370 at91_getaddr, &atsc->ping_pong[i].pa, 0);
371 if (err != 0)
372 goto errout;
373 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
374 BUS_DMASYNC_PREREAD);
375 }
376 atsc->ping = &atsc->ping_pong[0];
377 atsc->pong = &atsc->ping_pong[1];
378 }
379#endif
380
381 /*
382 * Prime the pump with the RX buffer. We use two 64 byte bounce
383 * buffers here to avoid data overflow.
384 */
385
386 /* Turn on rx and tx */
387 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
388 WR4(&sc->sc_bas, USART_CR, cr);
389 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
390
391 /*
392 * Setup the PDC to receive data. We use the ping-pong buffers
393 * so that we can more easily bounce between the two and so that
394 * we get an interrupt 1/2 way through the software 'fifo' we have
395 * to avoid overruns.
396 */
397 if (atsc->flags & HAS_TIMEOUT) {
398 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
399 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
400 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
401 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
402 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
403
404 /* Set the receive timeout to be 1.5 character times. */
405 WR4(&sc->sc_bas, USART_RTOR, 12);
406 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
407 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
408 USART_CSR_RXBUFF | USART_CSR_ENDRX);
409 } else {
410 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
411 }
412 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
413#ifndef SKYEYE_WORKAROUNDS
414errout:;
415 // XXX bad
416 return (err);
417#else
418 return (0);
419#endif
420}
421
422static int
423at91_usart_bus_transmit(struct uart_softc *sc)
424{
425#ifndef SKYEYE_WORKAROUNDS
426 bus_addr_t addr;
427#endif
428 struct at91_usart_softc *atsc;
429
430 atsc = (struct at91_usart_softc *)sc;
431#ifndef SKYEYE_WORKAROUNDS
432 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
433 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
434 return (EAGAIN);
435 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
436#endif
437
438 uart_lock(sc->sc_hwmtx);
439 sc->sc_txbusy = 1;
440#ifndef SKYEYE_WORKAROUNDS
441 /*
442 * Setup the PDC to transfer the data and interrupt us when it
443 * is done. We've already requested the interrupt.
444 */
445 WR4(&sc->sc_bas, PDC_TPR, addr);
446 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
447 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
448 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
449 uart_unlock(sc->sc_hwmtx);
450#else
451 for (int i = 0; i < sc->sc_txdatasz; i++)
452 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
453 /*
454 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the
455 * transfer is done, so simulate it.
456 */
457 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY);
458#endif
459 return (0);
460}
461static int
462at91_usart_bus_setsig(struct uart_softc *sc, int sig)
463{
464 uint32_t new, old, cr;
465 struct uart_bas *bas;
466
467 do {
468 old = sc->sc_hwsig;
469 new = old;
470 if (sig & SER_DDTR)
471 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
472 if (sig & SER_DRTS)
473 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
474 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
475 bas = &sc->sc_bas;
476 uart_lock(sc->sc_hwmtx);
477 cr = 0;
478 if (new & SER_DTR)
479 cr |= USART_CR_DTREN;
480 else
481 cr |= USART_CR_DTRDIS;
482 if (new & SER_RTS)
483 cr |= USART_CR_RTSEN;
484 else
485 cr |= USART_CR_RTSDIS;
486 WR4(bas, USART_CR, cr);
487 uart_unlock(sc->sc_hwmtx);
488 return (0);
489}
490static int
491at91_usart_bus_receive(struct uart_softc *sc)
492{
493
494 return (0);
495}
496static int
497at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
498 int stopbits, int parity)
499{
500
501 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
502 parity));
503}
504
505static __inline void
506at91_rx_put(struct uart_softc *sc, int key)
507{
508#if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER)
509 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
510 if (kdb_alt_break(key, &sc->sc_altbrk))
511 kdb_enter("Break sequence to console");
512 }
513#endif
514 uart_rx_put(sc, key);
515}
516
517static int
518at91_usart_bus_ipend(struct uart_softc *sc)
519{
520 int csr = RD4(&sc->sc_bas, USART_CSR);
521 int ipend = 0, i, len;
522 struct at91_usart_softc *atsc;
523 struct at91_usart_rx *p;
524
525 atsc = (struct at91_usart_softc *)sc;
526 if (csr & USART_CSR_ENDTX) {
527 bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
528 BUS_DMASYNC_POSTWRITE);
529 bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
530 }
531 uart_lock(sc->sc_hwmtx);
532 if (csr & USART_CSR_TXRDY) {
533 if (sc->sc_txbusy)
534 ipend |= SER_INT_TXIDLE;
535 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
536 }
537 if (csr & USART_CSR_ENDTX) {
538 if (sc->sc_txbusy)
539 ipend |= SER_INT_TXIDLE;
540 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
541 }
542
543 /*
544 * Due to the contraints of the DMA engine present in the
545 * atmel chip, I can't just say I have a rx interrupt pending
546 * and do all the work elsewhere. I need to look at the CSR
547 * bits right now and do things based on them to avoid races.
548 */
549 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
550 // Have a buffer overflow. Copy all data from both
551 // ping and pong. Insert overflow character. Reset
552 // ping and pong and re-enable the PDC to receive
553 // characters again.
554 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
555 BUS_DMASYNC_POSTREAD);
556 bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
557 BUS_DMASYNC_POSTREAD);
558 for (i = 0; i < sc->sc_rxfifosz; i++)
559 at91_rx_put(sc, atsc->ping->buffer[i]);
560 for (i = 0; i < sc->sc_rxfifosz; i++)
561 at91_rx_put(sc, atsc->pong->buffer[i]);
562 uart_rx_put(sc, UART_STAT_OVERRUN);
563 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
564 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
565 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
566 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
567 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
568 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
569 ipend |= SER_INT_RXREADY;
570 }
571 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
572 // Shuffle data from 'ping' of ping pong buffer, but
573 // leave current 'pong' in place, as it has become the
574 // new 'ping'. We need to copy data and setup the old
575 // 'ping' as the new 'pong' when we're done.
576 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
577 BUS_DMASYNC_POSTREAD);
578 for (i = 0; i < sc->sc_rxfifosz; i++)
579 at91_rx_put(sc, atsc->ping->buffer[i]);
580 p = atsc->ping;
581 atsc->ping = atsc->pong;
582 atsc->pong = p;
583 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
584 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
585 ipend |= SER_INT_RXREADY;
586 }
587 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
588 // We have one partial buffer. We need to stop the
589 // PDC, get the number of characters left and from
590 // that compute number of valid characters. We then
591 // need to reset ping and pong and reenable the PDC.
592 // Not sure if there's a race here at fast baud rates
593 // we need to worry about.
594 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
595 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
596 BUS_DMASYNC_POSTREAD);
597 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
598 for (i = 0; i < len; i++)
599 at91_rx_put(sc, atsc->ping->buffer[i]);
600 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
601 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
602 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
603 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
604 ipend |= SER_INT_RXREADY;
605 }
606 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
607 // We have another charater in a device that doesn't support
608 // timeouts, so we do it one character at a time.
609 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
610 ipend |= SER_INT_RXREADY;
611 }
612
613 if (csr & USART_CSR_RXBRK) {
614 unsigned int cr = USART_CR_RSTSTA;
615
616 ipend |= SER_INT_BREAK;
617 WR4(&sc->sc_bas, USART_CR, cr);
618 }
619 uart_unlock(sc->sc_hwmtx);
620 return (ipend);
621}
622static int
623at91_usart_bus_flush(struct uart_softc *sc, int what)
624{
625 return (0);
626}
627
628static int
629at91_usart_bus_getsig(struct uart_softc *sc)
630{
631 uint32_t new, sig;
632 uint8_t csr;
633
634 uart_lock(sc->sc_hwmtx);
635 csr = RD4(&sc->sc_bas, USART_CSR);
636 sig = 0;
637 if (csr & USART_CSR_CTS)
638 sig |= SER_CTS;
639 if (csr & USART_CSR_DCD)
640 sig |= SER_DCD;
641 if (csr & USART_CSR_DSR)
642 sig |= SER_DSR;
643 if (csr & USART_CSR_RI)
644 sig |= SER_RI;
645 new = sig & ~SER_MASK_DELTA;
646 sc->sc_hwsig = new;
647 uart_unlock(sc->sc_hwmtx);
648 return (sig);
649}
650
651static int
652at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
653{
654 switch (request) {
655 case UART_IOCTL_BREAK:
656 case UART_IOCTL_IFLOW:
657 case UART_IOCTL_OFLOW:
658 break;
659 case UART_IOCTL_BAUD:
660 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data));
661 return (0);
662 }
663 return (EINVAL);
664}
665struct uart_class at91_usart_class = {
666 "at91_usart class",
667 at91_usart_methods,
668 sizeof(struct at91_usart_softc),
669 .uc_range = 8,
670 .uc_rclk = DEFAULT_RCLK
671};