1#include <machine/asm.h>
2#include <arm/at91/at91_rstreg.h>
3#include <arm/at91/at91sam9g20reg.h>
| 1#include <machine/asm.h>
2#include <arm/at91/at91_rstreg.h>
3#include <arm/at91/at91sam9g20reg.h>
|
4__FBSDID("$FreeBSD: head/sys/arm/at91/at91_reset.S 213496 2010-10-06 22:25:21Z cognet $");
| 4__FBSDID("$FreeBSD: head/sys/arm/at91/at91_reset.S 236498 2012-06-03 05:36:25Z imp $");
|
5
6#define SDRAM_TR (AT91SAM9G20_BASE + \
7 AT91SAM9G20_SDRAMC_BASE + AT91SAM9G20_SDRAMC_TR)
8#define SDRAM_LPR (AT91SAM9G20_BASE + \
9 AT91SAM9G20_SDRAMC_BASE + AT91SAM9G20_SDRAMC_LPR)
10#define RSTC_RCR (AT91SAM9G20_BASE + \
11 AT91SAM9G20_RSTC_BASE + RST_CR)
12
13/*
14 * From AT91SAM9G20 Datasheet errata 44:3.5:
15 *
16 * When User Reset occurs durring SDRAM read acces, eh SDRAM clock is turned
17 * off while data are ready to be read on the data bus. The SDRAM maintains
18 * the data until the clock restarts.
19 *
20 * If the User reset is programed to assert a general reset, the data
| 5
6#define SDRAM_TR (AT91SAM9G20_BASE + \
7 AT91SAM9G20_SDRAMC_BASE + AT91SAM9G20_SDRAMC_TR)
8#define SDRAM_LPR (AT91SAM9G20_BASE + \
9 AT91SAM9G20_SDRAMC_BASE + AT91SAM9G20_SDRAMC_LPR)
10#define RSTC_RCR (AT91SAM9G20_BASE + \
11 AT91SAM9G20_RSTC_BASE + RST_CR)
12
13/*
14 * From AT91SAM9G20 Datasheet errata 44:3.5:
15 *
16 * When User Reset occurs durring SDRAM read acces, eh SDRAM clock is turned
17 * off while data are ready to be read on the data bus. The SDRAM maintains
18 * the data until the clock restarts.
19 *
20 * If the User reset is programed to assert a general reset, the data
|
21 * If the User reset is programed to assert a general reset, the data
| |
22 * maintained by the SDRAM leads to a data bus conflict and adversly affects
23 * the boot memories connected to the EBI:
24 * + NAND Flash boot functionality, if the system boots out of internal ROM.
25 * + NOR Flash boot, if the system boots on an external memory connected to
26 * the EBI CS0.
27 *
28 * Assembly code is mandatory for the following sequnce as ARM
29 * instructions need to be piplined.
--- 28 unchanged lines hidden --- | 21 * maintained by the SDRAM leads to a data bus conflict and adversly affects
22 * the boot memories connected to the EBI:
23 * + NAND Flash boot functionality, if the system boots out of internal ROM.
24 * + NOR Flash boot, if the system boots on an external memory connected to
25 * the EBI CS0.
26 *
27 * Assembly code is mandatory for the following sequnce as ARM
28 * instructions need to be piplined.
--- 28 unchanged lines hidden --- |