1/*-
2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (c) 2012 Luiz Otavio O Souza.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (c) 2012 Luiz Otavio O Souza.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29#include <sys/cdefs.h>
|
30__FBSDID("$FreeBSD: head/sys/arm/allwinner/a10_gpio.c 277968 2015-01-31 12:17:07Z loos $");
| 30__FBSDID("$FreeBSD: head/sys/arm/allwinner/a10_gpio.c 277996 2015-01-31 19:32:14Z loos $");
|
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35
36#include <sys/kernel.h>
37#include <sys/module.h>
38#include <sys/rman.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/gpio.h>
42
43#include <machine/bus.h>
44#include <machine/cpu.h>
45#include <machine/cpufunc.h>
46#include <machine/resource.h>
47#include <machine/fdt.h>
48#include <machine/intr.h>
49
50#include <dev/fdt/fdt_common.h>
| 31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35
36#include <sys/kernel.h>
37#include <sys/module.h>
38#include <sys/rman.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/gpio.h>
42
43#include <machine/bus.h>
44#include <machine/cpu.h>
45#include <machine/cpufunc.h>
46#include <machine/resource.h>
47#include <machine/fdt.h>
48#include <machine/intr.h>
49
50#include <dev/fdt/fdt_common.h>
|
| 51#include <dev/gpio/gpiobusvar.h>
|
51#include <dev/ofw/ofw_bus.h>
52#include <dev/ofw/ofw_bus_subr.h>
53
54#include "gpio_if.h"
55#include "a10_gpio.h"
56
57/*
58 * A10 have 9 banks of gpio.
59 * 32 pins per bank:
60 * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
61 * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
62 * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
63 */
64
65#define A10_GPIO_PINS 288
66#define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
67 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
68
69#define A10_GPIO_NONE 0
70#define A10_GPIO_PULLUP 1
71#define A10_GPIO_PULLDOWN 2
72
73#define A10_GPIO_INPUT 0
74#define A10_GPIO_OUTPUT 1
75
76struct a10_gpio_softc {
77 device_t sc_dev;
| 52#include <dev/ofw/ofw_bus.h>
53#include <dev/ofw/ofw_bus_subr.h>
54
55#include "gpio_if.h"
56#include "a10_gpio.h"
57
58/*
59 * A10 have 9 banks of gpio.
60 * 32 pins per bank:
61 * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
62 * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
63 * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
64 */
65
66#define A10_GPIO_PINS 288
67#define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
68 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
69
70#define A10_GPIO_NONE 0
71#define A10_GPIO_PULLUP 1
72#define A10_GPIO_PULLDOWN 2
73
74#define A10_GPIO_INPUT 0
75#define A10_GPIO_OUTPUT 1
76
77struct a10_gpio_softc {
78 device_t sc_dev;
|
| 79 device_t sc_busdev;
|
78 struct mtx sc_mtx;
79 struct resource * sc_mem_res;
80 struct resource * sc_irq_res;
81 bus_space_tag_t sc_bst;
82 bus_space_handle_t sc_bsh;
83 void * sc_intrhand;
84 int sc_gpio_npins;
85 struct gpio_pin sc_gpio_pins[A10_GPIO_PINS];
86};
87
88#define A10_GPIO_LOCK(_sc) mtx_lock(&_sc->sc_mtx)
89#define A10_GPIO_UNLOCK(_sc) mtx_unlock(&_sc->sc_mtx)
90#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
91
92#define A10_GPIO_GP_CFG(_bank, _pin) 0x00 + ((_bank) * 0x24) + ((_pin)<<2)
93#define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
94#define A10_GPIO_GP_DRV(_bank, _pin) 0x14 + ((_bank) * 0x24) + ((_pin)<<2)
95#define A10_GPIO_GP_PUL(_bank, _pin) 0x1c + ((_bank) * 0x24) + ((_pin)<<2)
96
97#define A10_GPIO_GP_INT_CFG0 0x200
98#define A10_GPIO_GP_INT_CFG1 0x204
99#define A10_GPIO_GP_INT_CFG2 0x208
100#define A10_GPIO_GP_INT_CFG3 0x20c
101
102#define A10_GPIO_GP_INT_CTL 0x210
103#define A10_GPIO_GP_INT_STA 0x214
104#define A10_GPIO_GP_INT_DEB 0x218
105
106static struct a10_gpio_softc *a10_gpio_sc;
107
108#define A10_GPIO_WRITE(_sc, _off, _val) \
109 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
110#define A10_GPIO_READ(_sc, _off) \
111 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
112
113static uint32_t
114a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
115{
116 uint32_t bank, func, offset;
117
118 bank = pin / 32;
119 pin = pin - 32 * bank;
120 func = pin >> 3;
121 offset = ((pin & 0x07) << 2);
122
123 A10_GPIO_LOCK(sc);
124 func = (A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func)) >> offset) & 7;
125 A10_GPIO_UNLOCK(sc);
126
127 return (func);
128}
129
130static uint32_t
131a10_gpio_func_flag(uint32_t nfunc)
132{
133
134 switch (nfunc) {
135 case A10_GPIO_INPUT:
136 return (GPIO_PIN_INPUT);
137 case A10_GPIO_OUTPUT:
138 return (GPIO_PIN_OUTPUT);
139 }
140 return (0);
141}
142
143static void
144a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
145{
146 uint32_t bank, func, data, offset;
147
148 /* Must be called with lock held. */
149 A10_GPIO_LOCK_ASSERT(sc);
150
151 bank = pin / 32;
152 pin = pin - 32 * bank;
153 func = pin >> 3;
154 offset = ((pin & 0x07) << 2);
155
156 data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func));
157 data &= ~(7 << offset);
158 data |= (f << offset);
159 A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, func), data);
160}
161
162static void
163a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state)
164{
165 uint32_t bank, offset, pull, val;
166
167 /* Must be called with lock held. */
168 A10_GPIO_LOCK_ASSERT(sc);
169
170 bank = pin / 32;
171 pin = pin - 32 * bank;
172 pull = pin >> 4;
173 offset = ((pin & 0x0f) << 1);
174
175 val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pull));
176 val &= ~(0x03 << offset);
177 val |= (state << offset);
178 A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pull), val);
179}
180
181static void
182a10_gpio_pin_configure(struct a10_gpio_softc *sc, struct gpio_pin *pin,
183 unsigned int flags)
184{
185
186 A10_GPIO_LOCK(sc);
187
188 /*
189 * Manage input/output.
190 */
191 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
192 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
193 if (flags & GPIO_PIN_OUTPUT) {
194 pin->gp_flags |= GPIO_PIN_OUTPUT;
195 a10_gpio_set_function(sc, pin->gp_pin,
196 A10_GPIO_OUTPUT);
197 } else {
198 pin->gp_flags |= GPIO_PIN_INPUT;
199 a10_gpio_set_function(sc, pin->gp_pin,
200 A10_GPIO_INPUT);
201 }
202 }
203
204 /* Manage Pull-up/pull-down. */
205 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
206 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
207 if (flags & GPIO_PIN_PULLUP) {
208 pin->gp_flags |= GPIO_PIN_PULLUP;
209 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLUP);
210 } else {
211 pin->gp_flags |= GPIO_PIN_PULLDOWN;
212 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLDOWN);
213 }
214 } else
215 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_NONE);
216
217 A10_GPIO_UNLOCK(sc);
218}
219
| 80 struct mtx sc_mtx;
81 struct resource * sc_mem_res;
82 struct resource * sc_irq_res;
83 bus_space_tag_t sc_bst;
84 bus_space_handle_t sc_bsh;
85 void * sc_intrhand;
86 int sc_gpio_npins;
87 struct gpio_pin sc_gpio_pins[A10_GPIO_PINS];
88};
89
90#define A10_GPIO_LOCK(_sc) mtx_lock(&_sc->sc_mtx)
91#define A10_GPIO_UNLOCK(_sc) mtx_unlock(&_sc->sc_mtx)
92#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
93
94#define A10_GPIO_GP_CFG(_bank, _pin) 0x00 + ((_bank) * 0x24) + ((_pin)<<2)
95#define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
96#define A10_GPIO_GP_DRV(_bank, _pin) 0x14 + ((_bank) * 0x24) + ((_pin)<<2)
97#define A10_GPIO_GP_PUL(_bank, _pin) 0x1c + ((_bank) * 0x24) + ((_pin)<<2)
98
99#define A10_GPIO_GP_INT_CFG0 0x200
100#define A10_GPIO_GP_INT_CFG1 0x204
101#define A10_GPIO_GP_INT_CFG2 0x208
102#define A10_GPIO_GP_INT_CFG3 0x20c
103
104#define A10_GPIO_GP_INT_CTL 0x210
105#define A10_GPIO_GP_INT_STA 0x214
106#define A10_GPIO_GP_INT_DEB 0x218
107
108static struct a10_gpio_softc *a10_gpio_sc;
109
110#define A10_GPIO_WRITE(_sc, _off, _val) \
111 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
112#define A10_GPIO_READ(_sc, _off) \
113 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
114
115static uint32_t
116a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
117{
118 uint32_t bank, func, offset;
119
120 bank = pin / 32;
121 pin = pin - 32 * bank;
122 func = pin >> 3;
123 offset = ((pin & 0x07) << 2);
124
125 A10_GPIO_LOCK(sc);
126 func = (A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func)) >> offset) & 7;
127 A10_GPIO_UNLOCK(sc);
128
129 return (func);
130}
131
132static uint32_t
133a10_gpio_func_flag(uint32_t nfunc)
134{
135
136 switch (nfunc) {
137 case A10_GPIO_INPUT:
138 return (GPIO_PIN_INPUT);
139 case A10_GPIO_OUTPUT:
140 return (GPIO_PIN_OUTPUT);
141 }
142 return (0);
143}
144
145static void
146a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
147{
148 uint32_t bank, func, data, offset;
149
150 /* Must be called with lock held. */
151 A10_GPIO_LOCK_ASSERT(sc);
152
153 bank = pin / 32;
154 pin = pin - 32 * bank;
155 func = pin >> 3;
156 offset = ((pin & 0x07) << 2);
157
158 data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func));
159 data &= ~(7 << offset);
160 data |= (f << offset);
161 A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, func), data);
162}
163
164static void
165a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state)
166{
167 uint32_t bank, offset, pull, val;
168
169 /* Must be called with lock held. */
170 A10_GPIO_LOCK_ASSERT(sc);
171
172 bank = pin / 32;
173 pin = pin - 32 * bank;
174 pull = pin >> 4;
175 offset = ((pin & 0x0f) << 1);
176
177 val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pull));
178 val &= ~(0x03 << offset);
179 val |= (state << offset);
180 A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pull), val);
181}
182
183static void
184a10_gpio_pin_configure(struct a10_gpio_softc *sc, struct gpio_pin *pin,
185 unsigned int flags)
186{
187
188 A10_GPIO_LOCK(sc);
189
190 /*
191 * Manage input/output.
192 */
193 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
194 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
195 if (flags & GPIO_PIN_OUTPUT) {
196 pin->gp_flags |= GPIO_PIN_OUTPUT;
197 a10_gpio_set_function(sc, pin->gp_pin,
198 A10_GPIO_OUTPUT);
199 } else {
200 pin->gp_flags |= GPIO_PIN_INPUT;
201 a10_gpio_set_function(sc, pin->gp_pin,
202 A10_GPIO_INPUT);
203 }
204 }
205
206 /* Manage Pull-up/pull-down. */
207 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
208 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
209 if (flags & GPIO_PIN_PULLUP) {
210 pin->gp_flags |= GPIO_PIN_PULLUP;
211 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLUP);
212 } else {
213 pin->gp_flags |= GPIO_PIN_PULLDOWN;
214 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLDOWN);
215 }
216 } else
217 a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_NONE);
218
219 A10_GPIO_UNLOCK(sc);
220}
221
|
| 222static device_t
223a10_gpio_get_bus(device_t dev)
224{
225 struct a10_gpio_softc *sc;
226
227 sc = device_get_softc(dev);
228
229 return (sc->sc_busdev);
230}
231
|
220static int
221a10_gpio_pin_max(device_t dev, int *maxpin)
222{
223
224 *maxpin = A10_GPIO_PINS - 1;
225 return (0);
226}
227
228static int
229a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
230{
231 struct a10_gpio_softc *sc = device_get_softc(dev);
232 int i;
233
234 for (i = 0; i < sc->sc_gpio_npins; i++) {
235 if (sc->sc_gpio_pins[i].gp_pin == pin)
236 break;
237 }
238
239 if (i >= sc->sc_gpio_npins)
240 return (EINVAL);
241
242 A10_GPIO_LOCK(sc);
243 *caps = sc->sc_gpio_pins[i].gp_caps;
244 A10_GPIO_UNLOCK(sc);
245
246 return (0);
247}
248
249static int
250a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
251{
252 struct a10_gpio_softc *sc = device_get_softc(dev);
253 int i;
254
255 for (i = 0; i < sc->sc_gpio_npins; i++) {
256 if (sc->sc_gpio_pins[i].gp_pin == pin)
257 break;
258 }
259
260 if (i >= sc->sc_gpio_npins)
261 return (EINVAL);
262
263 A10_GPIO_LOCK(sc);
264 *flags = sc->sc_gpio_pins[i].gp_flags;
265 A10_GPIO_UNLOCK(sc);
266
267 return (0);
268}
269
270static int
271a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
272{
273 struct a10_gpio_softc *sc = device_get_softc(dev);
274 int i;
275
276 for (i = 0; i < sc->sc_gpio_npins; i++) {
277 if (sc->sc_gpio_pins[i].gp_pin == pin)
278 break;
279 }
280
281 if (i >= sc->sc_gpio_npins)
282 return (EINVAL);
283
284 A10_GPIO_LOCK(sc);
285 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
286 A10_GPIO_UNLOCK(sc);
287
288 return (0);
289}
290
291static int
292a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
293{
294 struct a10_gpio_softc *sc = device_get_softc(dev);
295 int i;
296
297 for (i = 0; i < sc->sc_gpio_npins; i++) {
298 if (sc->sc_gpio_pins[i].gp_pin == pin)
299 break;
300 }
301
302 if (i >= sc->sc_gpio_npins)
303 return (EINVAL);
304
305 a10_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
306
307 return (0);
308}
309
310static int
311a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
312{
313 struct a10_gpio_softc *sc = device_get_softc(dev);
314 uint32_t bank, offset, data;
315 int i;
316
317 for (i = 0; i < sc->sc_gpio_npins; i++) {
318 if (sc->sc_gpio_pins[i].gp_pin == pin)
319 break;
320 }
321
322 if (i >= sc->sc_gpio_npins)
323 return (EINVAL);
324
325 bank = pin / 32;
326 pin = pin - 32 * bank;
327 offset = pin & 0x1f;
328
329 A10_GPIO_LOCK(sc);
330 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
331 if (value)
332 data |= (1 << offset);
333 else
334 data &= ~(1 << offset);
335 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
336 A10_GPIO_UNLOCK(sc);
337
338 return (0);
339}
340
341static int
342a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
343{
344 struct a10_gpio_softc *sc = device_get_softc(dev);
345 uint32_t bank, offset, reg_data;
346 int i;
347
348 for (i = 0; i < sc->sc_gpio_npins; i++) {
349 if (sc->sc_gpio_pins[i].gp_pin == pin)
350 break;
351 }
352
353 if (i >= sc->sc_gpio_npins)
354 return (EINVAL);
355
356 bank = pin / 32;
357 pin = pin - 32 * bank;
358 offset = pin & 0x1f;
359
360 A10_GPIO_LOCK(sc);
361 reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
362 A10_GPIO_UNLOCK(sc);
363 *val = (reg_data & (1 << offset)) ? 1 : 0;
364
365 return (0);
366}
367
368static int
369a10_gpio_pin_toggle(device_t dev, uint32_t pin)
370{
371 struct a10_gpio_softc *sc = device_get_softc(dev);
372 uint32_t bank, data, offset;
373 int i;
374
375 for (i = 0; i < sc->sc_gpio_npins; i++) {
376 if (sc->sc_gpio_pins[i].gp_pin == pin)
377 break;
378 }
379
380 if (i >= sc->sc_gpio_npins)
381 return (EINVAL);
382
383 bank = pin / 32;
384 pin = pin - 32 * bank;
385 offset = pin & 0x1f;
386
387 A10_GPIO_LOCK(sc);
388 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
389 if (data & (1 << offset))
390 data &= ~(1 << offset);
391 else
392 data |= (1 << offset);
393 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
394 A10_GPIO_UNLOCK(sc);
395
396 return (0);
397}
398
399static int
400a10_gpio_probe(device_t dev)
401{
402
403 if (!ofw_bus_status_okay(dev))
404 return (ENXIO);
405
406 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-gpio"))
407 return (ENXIO);
408
409 device_set_desc(dev, "Allwinner GPIO controller");
410 return (BUS_PROBE_DEFAULT);
411}
412
413static int
414a10_gpio_attach(device_t dev)
415{
416 struct a10_gpio_softc *sc = device_get_softc(dev);
417 uint32_t func;
418 int i, rid;
419 phandle_t gpio;
420
421 sc->sc_dev = dev;
422
423 mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_DEF);
424
425 rid = 0;
426 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
427 RF_ACTIVE);
428 if (!sc->sc_mem_res) {
429 device_printf(dev, "cannot allocate memory window\n");
430 goto fail;
431 }
432
433 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
434 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
435
436 rid = 0;
437 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
438 RF_ACTIVE);
439 if (!sc->sc_irq_res) {
440 device_printf(dev, "cannot allocate interrupt\n");
441 goto fail;
442 }
443
444 /* Find our node. */
445 gpio = ofw_bus_get_node(sc->sc_dev);
446
447 if (!OF_hasprop(gpio, "gpio-controller"))
448 /* Node is not a GPIO controller. */
449 goto fail;
450
451 /* Initialize the software controlled pins. */
452 for (i = 0; i < A10_GPIO_PINS; i++) {
453 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
454 "pin %d", i);
455 func = a10_gpio_get_function(sc, i);
456 sc->sc_gpio_pins[i].gp_pin = i;
457 sc->sc_gpio_pins[i].gp_caps = A10_GPIO_DEFAULT_CAPS;
458 sc->sc_gpio_pins[i].gp_flags = a10_gpio_func_flag(func);
459 }
460 sc->sc_gpio_npins = i;
| 232static int
233a10_gpio_pin_max(device_t dev, int *maxpin)
234{
235
236 *maxpin = A10_GPIO_PINS - 1;
237 return (0);
238}
239
240static int
241a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
242{
243 struct a10_gpio_softc *sc = device_get_softc(dev);
244 int i;
245
246 for (i = 0; i < sc->sc_gpio_npins; i++) {
247 if (sc->sc_gpio_pins[i].gp_pin == pin)
248 break;
249 }
250
251 if (i >= sc->sc_gpio_npins)
252 return (EINVAL);
253
254 A10_GPIO_LOCK(sc);
255 *caps = sc->sc_gpio_pins[i].gp_caps;
256 A10_GPIO_UNLOCK(sc);
257
258 return (0);
259}
260
261static int
262a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
263{
264 struct a10_gpio_softc *sc = device_get_softc(dev);
265 int i;
266
267 for (i = 0; i < sc->sc_gpio_npins; i++) {
268 if (sc->sc_gpio_pins[i].gp_pin == pin)
269 break;
270 }
271
272 if (i >= sc->sc_gpio_npins)
273 return (EINVAL);
274
275 A10_GPIO_LOCK(sc);
276 *flags = sc->sc_gpio_pins[i].gp_flags;
277 A10_GPIO_UNLOCK(sc);
278
279 return (0);
280}
281
282static int
283a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
284{
285 struct a10_gpio_softc *sc = device_get_softc(dev);
286 int i;
287
288 for (i = 0; i < sc->sc_gpio_npins; i++) {
289 if (sc->sc_gpio_pins[i].gp_pin == pin)
290 break;
291 }
292
293 if (i >= sc->sc_gpio_npins)
294 return (EINVAL);
295
296 A10_GPIO_LOCK(sc);
297 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
298 A10_GPIO_UNLOCK(sc);
299
300 return (0);
301}
302
303static int
304a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
305{
306 struct a10_gpio_softc *sc = device_get_softc(dev);
307 int i;
308
309 for (i = 0; i < sc->sc_gpio_npins; i++) {
310 if (sc->sc_gpio_pins[i].gp_pin == pin)
311 break;
312 }
313
314 if (i >= sc->sc_gpio_npins)
315 return (EINVAL);
316
317 a10_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
318
319 return (0);
320}
321
322static int
323a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
324{
325 struct a10_gpio_softc *sc = device_get_softc(dev);
326 uint32_t bank, offset, data;
327 int i;
328
329 for (i = 0; i < sc->sc_gpio_npins; i++) {
330 if (sc->sc_gpio_pins[i].gp_pin == pin)
331 break;
332 }
333
334 if (i >= sc->sc_gpio_npins)
335 return (EINVAL);
336
337 bank = pin / 32;
338 pin = pin - 32 * bank;
339 offset = pin & 0x1f;
340
341 A10_GPIO_LOCK(sc);
342 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
343 if (value)
344 data |= (1 << offset);
345 else
346 data &= ~(1 << offset);
347 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
348 A10_GPIO_UNLOCK(sc);
349
350 return (0);
351}
352
353static int
354a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
355{
356 struct a10_gpio_softc *sc = device_get_softc(dev);
357 uint32_t bank, offset, reg_data;
358 int i;
359
360 for (i = 0; i < sc->sc_gpio_npins; i++) {
361 if (sc->sc_gpio_pins[i].gp_pin == pin)
362 break;
363 }
364
365 if (i >= sc->sc_gpio_npins)
366 return (EINVAL);
367
368 bank = pin / 32;
369 pin = pin - 32 * bank;
370 offset = pin & 0x1f;
371
372 A10_GPIO_LOCK(sc);
373 reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
374 A10_GPIO_UNLOCK(sc);
375 *val = (reg_data & (1 << offset)) ? 1 : 0;
376
377 return (0);
378}
379
380static int
381a10_gpio_pin_toggle(device_t dev, uint32_t pin)
382{
383 struct a10_gpio_softc *sc = device_get_softc(dev);
384 uint32_t bank, data, offset;
385 int i;
386
387 for (i = 0; i < sc->sc_gpio_npins; i++) {
388 if (sc->sc_gpio_pins[i].gp_pin == pin)
389 break;
390 }
391
392 if (i >= sc->sc_gpio_npins)
393 return (EINVAL);
394
395 bank = pin / 32;
396 pin = pin - 32 * bank;
397 offset = pin & 0x1f;
398
399 A10_GPIO_LOCK(sc);
400 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
401 if (data & (1 << offset))
402 data &= ~(1 << offset);
403 else
404 data |= (1 << offset);
405 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
406 A10_GPIO_UNLOCK(sc);
407
408 return (0);
409}
410
411static int
412a10_gpio_probe(device_t dev)
413{
414
415 if (!ofw_bus_status_okay(dev))
416 return (ENXIO);
417
418 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-gpio"))
419 return (ENXIO);
420
421 device_set_desc(dev, "Allwinner GPIO controller");
422 return (BUS_PROBE_DEFAULT);
423}
424
425static int
426a10_gpio_attach(device_t dev)
427{
428 struct a10_gpio_softc *sc = device_get_softc(dev);
429 uint32_t func;
430 int i, rid;
431 phandle_t gpio;
432
433 sc->sc_dev = dev;
434
435 mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_DEF);
436
437 rid = 0;
438 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
439 RF_ACTIVE);
440 if (!sc->sc_mem_res) {
441 device_printf(dev, "cannot allocate memory window\n");
442 goto fail;
443 }
444
445 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
446 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
447
448 rid = 0;
449 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
450 RF_ACTIVE);
451 if (!sc->sc_irq_res) {
452 device_printf(dev, "cannot allocate interrupt\n");
453 goto fail;
454 }
455
456 /* Find our node. */
457 gpio = ofw_bus_get_node(sc->sc_dev);
458
459 if (!OF_hasprop(gpio, "gpio-controller"))
460 /* Node is not a GPIO controller. */
461 goto fail;
462
463 /* Initialize the software controlled pins. */
464 for (i = 0; i < A10_GPIO_PINS; i++) {
465 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
466 "pin %d", i);
467 func = a10_gpio_get_function(sc, i);
468 sc->sc_gpio_pins[i].gp_pin = i;
469 sc->sc_gpio_pins[i].gp_caps = A10_GPIO_DEFAULT_CAPS;
470 sc->sc_gpio_pins[i].gp_flags = a10_gpio_func_flag(func);
471 }
472 sc->sc_gpio_npins = i;
|
461
462 device_add_child(dev, "gpioc", -1);
463 device_add_child(dev, "gpiobus", -1);
464
| |
465 a10_gpio_sc = sc;
| 473 a10_gpio_sc = sc;
|
| 474 sc->sc_busdev = gpiobus_attach_bus(dev);
475 if (sc->sc_busdev == NULL)
476 goto fail;
|
466
| 477
|
467 return (bus_generic_attach(dev));
| 478 return (0);
|
468
469fail:
470 if (sc->sc_irq_res)
471 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
472 if (sc->sc_mem_res)
473 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
474 mtx_destroy(&sc->sc_mtx);
475
476 return (ENXIO);
477}
478
479static int
480a10_gpio_detach(device_t dev)
481{
482
483 return (EBUSY);
484}
485
486static device_method_t a10_gpio_methods[] = {
487 /* Device interface */
488 DEVMETHOD(device_probe, a10_gpio_probe),
489 DEVMETHOD(device_attach, a10_gpio_attach),
490 DEVMETHOD(device_detach, a10_gpio_detach),
491
492 /* GPIO protocol */
| 479
480fail:
481 if (sc->sc_irq_res)
482 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
483 if (sc->sc_mem_res)
484 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
485 mtx_destroy(&sc->sc_mtx);
486
487 return (ENXIO);
488}
489
490static int
491a10_gpio_detach(device_t dev)
492{
493
494 return (EBUSY);
495}
496
497static device_method_t a10_gpio_methods[] = {
498 /* Device interface */
499 DEVMETHOD(device_probe, a10_gpio_probe),
500 DEVMETHOD(device_attach, a10_gpio_attach),
501 DEVMETHOD(device_detach, a10_gpio_detach),
502
503 /* GPIO protocol */
|
| 504 DEVMETHOD(gpio_get_bus, a10_gpio_get_bus),
|
493 DEVMETHOD(gpio_pin_max, a10_gpio_pin_max),
494 DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname),
495 DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags),
496 DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps),
497 DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags),
498 DEVMETHOD(gpio_pin_get, a10_gpio_pin_get),
499 DEVMETHOD(gpio_pin_set, a10_gpio_pin_set),
500 DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle),
501
502 DEVMETHOD_END
503};
504
505static devclass_t a10_gpio_devclass;
506
507static driver_t a10_gpio_driver = {
508 "gpio",
509 a10_gpio_methods,
510 sizeof(struct a10_gpio_softc),
511};
512
513DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0);
514
515int
516a10_emac_gpio_config(uint32_t pin)
517{
518 struct a10_gpio_softc *sc = a10_gpio_sc;
519
520 if (sc == NULL)
521 return (ENXIO);
522
523 /* Configure pin mux settings for MII. */
524 A10_GPIO_LOCK(sc);
525 a10_gpio_set_function(sc, pin, A10_GPIO_PULLDOWN);
526 A10_GPIO_UNLOCK(sc);
527
528 return (0);
529}
| 505 DEVMETHOD(gpio_pin_max, a10_gpio_pin_max),
506 DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname),
507 DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags),
508 DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps),
509 DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags),
510 DEVMETHOD(gpio_pin_get, a10_gpio_pin_get),
511 DEVMETHOD(gpio_pin_set, a10_gpio_pin_set),
512 DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle),
513
514 DEVMETHOD_END
515};
516
517static devclass_t a10_gpio_devclass;
518
519static driver_t a10_gpio_driver = {
520 "gpio",
521 a10_gpio_methods,
522 sizeof(struct a10_gpio_softc),
523};
524
525DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0);
526
527int
528a10_emac_gpio_config(uint32_t pin)
529{
530 struct a10_gpio_softc *sc = a10_gpio_sc;
531
532 if (sc == NULL)
533 return (ENXIO);
534
535 /* Configure pin mux settings for MII. */
536 A10_GPIO_LOCK(sc);
537 a10_gpio_set_function(sc, pin, A10_GPIO_PULLDOWN);
538 A10_GPIO_UNLOCK(sc);
539
540 return (0);
541}
|