| intr_machdep.h (163219) | intr_machdep.h (164265) |
|---|---|
| 1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/amd64/include/intr_machdep.h 163219 2006-10-10 23:23:12Z jhb $ | 26 * $FreeBSD: head/sys/amd64/include/intr_machdep.h 164265 2006-11-13 22:23:34Z jhb $ |
| 27 */ 28 29#ifndef __MACHINE_INTR_MACHDEP_H__ 30#define __MACHINE_INTR_MACHDEP_H__ 31 32#ifdef _KERNEL 33 34/* 35 * The maximum number of I/O interrupts we allow. This number is rather 36 * arbitrary as it is just the maximum IRQ resource value. The interrupt 37 * source for a given IRQ maps that I/O interrupt to device interrupt 38 * source whether it be a pin on an interrupt controller or an MSI interrupt. 39 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 40 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 41 * vectors available for device interrupts. On many systems with I/O APICs, 42 * a lot of the IRQs are not used, so this number can be much larger than 43 * 191 and still be safe since only interrupt sources in actual use will 44 * allocate IDT vectors. 45 * | 27 */ 28 29#ifndef __MACHINE_INTR_MACHDEP_H__ 30#define __MACHINE_INTR_MACHDEP_H__ 31 32#ifdef _KERNEL 33 34/* 35 * The maximum number of I/O interrupts we allow. This number is rather 36 * arbitrary as it is just the maximum IRQ resource value. The interrupt 37 * source for a given IRQ maps that I/O interrupt to device interrupt 38 * source whether it be a pin on an interrupt controller or an MSI interrupt. 39 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 40 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 41 * vectors available for device interrupts. On many systems with I/O APICs, 42 * a lot of the IRQs are not used, so this number can be much larger than 43 * 191 and still be safe since only interrupt sources in actual use will 44 * allocate IDT vectors. 45 * |
| 46 * For now we stick with 255 as ISA IRQs and PCI intline IRQs only allow 47 * for IRQs in the range 0 - 254. When MSI support is added this number 48 * will likely increase. | 46 * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 47 * IRQ values beyond 256 are used by MSI. We leave 255 unused to avoid 48 * confusion since 255 is used in PCI to indicate an invalid IRQ. |
| 49 */ | 49 */ |
| 50#define NUM_IO_INTS 255 | 50#define NUM_MSI_INTS 128 51#define FIRST_MSI_INT 256 52#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS) |
| 51 52/* | 53 54/* |
| 55 * Default base address for MSI messages on x86 platforms. 56 */ 57#define MSI_INTEL_ADDR_BASE 0xfee00000 58 59/* |
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| 53 * - 1 ??? dummy counter. 54 * - 2 counters for each I/O interrupt. 55 * - 1 counter for each CPU for lapic timer. 56 * - 7 counters for each CPU for IPI counters for SMP. 57 */ 58#ifdef SMP 59#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU) 60#else --- 74 unchanged lines hidden (view full) --- 135void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 136struct intsrc *intr_lookup_source(int vector); 137int intr_register_pic(struct pic *pic); 138int intr_register_source(struct intsrc *isrc); 139int intr_remove_handler(void *cookie); 140void intr_resume(void); 141void intr_suspend(void); 142void intrcnt_add(const char *name, u_long **countp); | 60 * - 1 ??? dummy counter. 61 * - 2 counters for each I/O interrupt. 62 * - 1 counter for each CPU for lapic timer. 63 * - 7 counters for each CPU for IPI counters for SMP. 64 */ 65#ifdef SMP 66#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU) 67#else --- 74 unchanged lines hidden (view full) --- 142void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 143struct intsrc *intr_lookup_source(int vector); 144int intr_register_pic(struct pic *pic); 145int intr_register_source(struct intsrc *isrc); 146int intr_remove_handler(void *cookie); 147void intr_resume(void); 148void intr_suspend(void); 149void intrcnt_add(const char *name, u_long **countp); |
| 150void msi_init(void); 151int msi_alloc(device_t dev, int count, int maxcount, int *irqs, int *newirq, 152 int *newcount); 153int msi_release(int *irqs, int count); 154int msix_alloc(device_t dev, int index, int *irq, int *new); 155int msix_release(int irq); |
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| 143 144#endif /* !LOCORE */ 145#endif /* _KERNEL */ 146#endif /* !__MACHINE_INTR_MACHDEP_H__ */ | 156 157#endif /* !LOCORE */ 158#endif /* _KERNEL */ 159#endif /* !__MACHINE_INTR_MACHDEP_H__ */ |