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machdep.c (778) machdep.c (798)
1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *

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30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *

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30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $Id: machdep.c,v 1.17 1993/11/16 09:54:47 davidg Exp $
38 * $Id: machdep.c,v 1.18 1993/11/17 23:24:56 wollman Exp $
39 */
40
41#include "npx.h"
42#include "isa.h"
43
44#include <stddef.h>
45#include "param.h"
46#include "systm.h"

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84#include "machine/reg.h"
85#include "machine/psl.h"
86#include "machine/specialreg.h"
87#include "machine/sysarch.h"
88
89#include "i386/isa/isa.h"
90#include "i386/isa/rtc.h"
91
39 */
40
41#include "npx.h"
42#include "isa.h"
43
44#include <stddef.h>
45#include "param.h"
46#include "systm.h"

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84#include "machine/reg.h"
85#include "machine/psl.h"
86#include "machine/specialreg.h"
87#include "machine/sysarch.h"
88
89#include "i386/isa/isa.h"
90#include "i386/isa/rtc.h"
91
92static void identifycpu(void);
93static void initcpu(void);
92
93#define EXPECT_BASEMEM 640 /* The expected base memory*/
94#define INFORM_WAIT 1 /* Set to pause berfore crash in weird cases*/
95
96#ifndef PANIC_REBOOT_WAIT_TIME
97#define PANIC_REBOOT_WAIT_TIME 15 /* default to 15 seconds */
98#endif
99

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139 register int unixsize;
140 register unsigned i;
141 register struct pte *pte;
142 int mapaddr, j;
143 register caddr_t v;
144 int maxbufs, base, residual;
145 extern long Usrptsize;
146 vm_offset_t minaddr, maxaddr;
94
95#define EXPECT_BASEMEM 640 /* The expected base memory*/
96#define INFORM_WAIT 1 /* Set to pause berfore crash in weird cases*/
97
98#ifndef PANIC_REBOOT_WAIT_TIME
99#define PANIC_REBOOT_WAIT_TIME 15 /* default to 15 seconds */
100#endif
101

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141 register int unixsize;
142 register unsigned i;
143 register struct pte *pte;
144 int mapaddr, j;
145 register caddr_t v;
146 int maxbufs, base, residual;
147 extern long Usrptsize;
148 vm_offset_t minaddr, maxaddr;
147 vm_size_t size;
149 vm_size_t size = 0;
148 int firstaddr;
149
150 /*
151 * Initialize error message buffer (at end of core).
152 */
153
154 /* avail_end was pre-decremented in pmap_bootstrap to compensate */
155 for (i = 0; i < btoc(sizeof (struct msgbuf)); i++)

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310 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
311 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
312 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
313 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
314 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
315 { "i586", CPUCLASS_586 }, /* CPU_586 */
316};
317
150 int firstaddr;
151
152 /*
153 * Initialize error message buffer (at end of core).
154 */
155
156 /* avail_end was pre-decremented in pmap_bootstrap to compensate */
157 for (i = 0; i < btoc(sizeof (struct msgbuf)); i++)

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312 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
313 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
314 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
315 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
316 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
317 { "i586", CPUCLASS_586 }, /* CPU_586 */
318};
319
320static void
318identifycpu() /* translated from hp300 -- cgd */
319{
320 printf("CPU: ");
321 if (cpu >= 0 && cpu < (sizeof i386_cpus/sizeof(struct cpu_nameclass))) {
322 printf("%s", i386_cpus[cpu].cpu_name);
323 cpu_class = i386_cpus[cpu].cpu_class;
324 } else {
325 printf("unknown cpu type %d\n", cpu);

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500 * make sure that the user has not modified the
501 * psl to gain improper priviledges or to cause
502 * a machine fault.
503 */
504struct sigreturn_args {
505 struct sigcontext *sigcntxp;
506};
507
321identifycpu() /* translated from hp300 -- cgd */
322{
323 printf("CPU: ");
324 if (cpu >= 0 && cpu < (sizeof i386_cpus/sizeof(struct cpu_nameclass))) {
325 printf("%s", i386_cpus[cpu].cpu_name);
326 cpu_class = i386_cpus[cpu].cpu_class;
327 } else {
328 printf("unknown cpu type %d\n", cpu);

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503 * make sure that the user has not modified the
504 * psl to gain improper priviledges or to cause
505 * a machine fault.
506 */
507struct sigreturn_args {
508 struct sigcontext *sigcntxp;
509};
510
511int
508sigreturn(p, uap, retval)
509 struct proc *p;
510 struct sigreturn_args *uap;
511 int *retval;
512{
513 register struct sigcontext *scp;
514 register struct sigframe *fp;
515 register int *regs = p->p_regs;

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724 while (tvp->tv_usec > 1000000) {
725 tvp->tv_sec++;
726 tvp->tv_usec -= 1000000;
727 }
728 splx(s);
729}
730#endif /* HZ */
731
512sigreturn(p, uap, retval)
513 struct proc *p;
514 struct sigreturn_args *uap;
515 int *retval;
516{
517 register struct sigcontext *scp;
518 register struct sigframe *fp;
519 register int *regs = p->p_regs;

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728 while (tvp->tv_usec > 1000000) {
729 tvp->tv_sec++;
730 tvp->tv_usec -= 1000000;
731 }
732 splx(s);
733}
734#endif /* HZ */
735
736void
732physstrat(bp, strat, prio)
733 struct buf *bp;
734 int (*strat)(), prio;
735{
736 register int s;
737 caddr_t baddr;
738
737physstrat(bp, strat, prio)
738 struct buf *bp;
739 int (*strat)(), prio;
740{
741 register int s;
742 caddr_t baddr;
743
739 /*
740 * vmapbuf clobbers b_addr so we must remember it so that it
741 * can be restored after vunmapbuf. This is truely rude, we
742 * should really be storing this in a field in the buf struct
743 * but none are available and I didn't want to add one at
744 * this time. Note that b_addr for dirty page pushes is
745 * restored in vunmapbuf. (ugh!)
746 */
747 baddr = bp->b_un.b_addr;
748 vmapbuf(bp);
749 (*strat)(bp);
750 /* pageout daemon doesn't wait for pushed pages */
751 if (bp->b_flags & B_DIRTY)
752 return;
753 s = splbio();
754 while ((bp->b_flags & B_DONE) == 0)
755 tsleep((caddr_t)bp, prio, "physstr", 0);
756 splx(s);
757 vunmapbuf(bp);
744 vmapbuf(bp);
745 (*strat)(bp);
746 /* pageout daemon doesn't wait for pushed pages */
747 if (bp->b_flags & B_DIRTY)
748 return;
749 s = splbio();
750 while ((bp->b_flags & B_DONE) == 0)
751 tsleep((caddr_t)bp, prio, "physstr", 0);
752 splx(s);
753 vunmapbuf(bp);
758 bp->b_un.b_addr = baddr;
759}
760
754}
755
756static void
761initcpu()
762{
763}
764
765/*
766 * Clear registers on exec
767 */
768void

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927 0xfffff, /* length - all address space */
928 SDT_MEMRWA, /* segment type */
929 SEL_UPL, /* segment descriptor priority level */
930 1, /* segment descriptor present */
931 0, 0,
932 1, /* default 32 vs 16 bit size */
933 1 /* limit granularity (byte/page units)*/ } };
934
757initcpu()
758{
759}
760
761/*
762 * Clear registers on exec
763 */
764void

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923 0xfffff, /* length - all address space */
924 SDT_MEMRWA, /* segment type */
925 SEL_UPL, /* segment descriptor priority level */
926 1, /* segment descriptor present */
927 0, 0,
928 1, /* default 32 vs 16 bit size */
929 1 /* limit granularity (byte/page units)*/ } };
930
935setidt(idx, func, typ, dpl) char *func; {
931void
932setidt(idx, func, typ, dpl)
933 int idx;
934 caddr_t func;
935 int typ;
936 int dpl;
937{
936 struct gate_descriptor *ip = idt + idx;
937
938 ip->gd_looffset = (int)func;
939 ip->gd_selector = 8;
940 ip->gd_stkcpy = 0;
941 ip->gd_xx = 0;
942 ip->gd_type = typ;
943 ip->gd_dpl = dpl;

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953 IDTVEC(rsvd1), IDTVEC(rsvd2), IDTVEC(rsvd3), IDTVEC(rsvd4),
954 IDTVEC(rsvd5), IDTVEC(rsvd6), IDTVEC(rsvd7), IDTVEC(rsvd8),
955 IDTVEC(rsvd9), IDTVEC(rsvd10), IDTVEC(rsvd11), IDTVEC(rsvd12),
956 IDTVEC(rsvd13), IDTVEC(rsvd14), IDTVEC(rsvd14), IDTVEC(syscall);
957
958int lcr0(), lcr3(), rcr0(), rcr2();
959int _gsel_tss;
960
938 struct gate_descriptor *ip = idt + idx;
939
940 ip->gd_looffset = (int)func;
941 ip->gd_selector = 8;
942 ip->gd_stkcpy = 0;
943 ip->gd_xx = 0;
944 ip->gd_type = typ;
945 ip->gd_dpl = dpl;

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955 IDTVEC(rsvd1), IDTVEC(rsvd2), IDTVEC(rsvd3), IDTVEC(rsvd4),
956 IDTVEC(rsvd5), IDTVEC(rsvd6), IDTVEC(rsvd7), IDTVEC(rsvd8),
957 IDTVEC(rsvd9), IDTVEC(rsvd10), IDTVEC(rsvd11), IDTVEC(rsvd12),
958 IDTVEC(rsvd13), IDTVEC(rsvd14), IDTVEC(rsvd14), IDTVEC(syscall);
959
960int lcr0(), lcr3(), rcr0(), rcr2();
961int _gsel_tss;
962
963void
961init386(first)
964init386(first)
965 int first;
962{
963 extern ssdtosd(), lgdt(), lidt(), lldt(), etext;
964 int x, *pi;
965 unsigned biosbasemem, biosextmem;
966 struct gate_descriptor *gdp;
967 extern int sigcode,szsigcode;
968 /* table descriptors - used to load tables by microp */
969 unsigned short r_gdt[3], r_idt[3];

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1165}
1166
1167extern struct pte *CMAP1, *CMAP2;
1168extern caddr_t CADDR1, CADDR2;
1169/*
1170 * zero out physical memory
1171 * specified in relocation units (NBPG bytes)
1172 */
966{
967 extern ssdtosd(), lgdt(), lidt(), lldt(), etext;
968 int x, *pi;
969 unsigned biosbasemem, biosextmem;
970 struct gate_descriptor *gdp;
971 extern int sigcode,szsigcode;
972 /* table descriptors - used to load tables by microp */
973 unsigned short r_gdt[3], r_idt[3];

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1169}
1170
1171extern struct pte *CMAP1, *CMAP2;
1172extern caddr_t CADDR1, CADDR2;
1173/*
1174 * zero out physical memory
1175 * specified in relocation units (NBPG bytes)
1176 */
1173clearseg(n) {
1177void
1178clearseg(n)
1179 int n;
1180{
1174
1175 *(int *)CMAP2 = PG_V | PG_KW | ctob(n);
1176 load_cr3(rcr3());
1177 bzero(CADDR2,NBPG);
1178#ifndef MACHINE_NONCONTIG
1179 *(int *) CADDR2 = 0;
1180#endif /* MACHINE_NONCONTIG */
1181}
1182
1183/*
1184 * copy a page of physical memory
1185 * specified in relocation units (NBPG bytes)
1186 */
1187void
1181
1182 *(int *)CMAP2 = PG_V | PG_KW | ctob(n);
1183 load_cr3(rcr3());
1184 bzero(CADDR2,NBPG);
1185#ifndef MACHINE_NONCONTIG
1186 *(int *) CADDR2 = 0;
1187#endif /* MACHINE_NONCONTIG */
1188}
1189
1190/*
1191 * copy a page of physical memory
1192 * specified in relocation units (NBPG bytes)
1193 */
1194void
1188copyseg(frm, n) {
1195copyseg(frm, n)
1196 int frm;
1197 int n;
1198{
1189
1190 *(int *)CMAP2 = PG_V | PG_KW | ctob(n);
1191 load_cr3(rcr3());
1192 bcopy((void *)frm, (void *)CADDR2, NBPG);
1193}
1194
1195/*
1196 * copy a page of physical memory
1197 * specified in relocation units (NBPG bytes)
1198 */
1199void
1199
1200 *(int *)CMAP2 = PG_V | PG_KW | ctob(n);
1201 load_cr3(rcr3());
1202 bcopy((void *)frm, (void *)CADDR2, NBPG);
1203}
1204
1205/*
1206 * copy a page of physical memory
1207 * specified in relocation units (NBPG bytes)
1208 */
1209void
1200physcopyseg(frm, to) {
1210physcopyseg(frm, to)
1211 int frm;
1212 int to;
1213{
1201
1202 *(int *)CMAP1 = PG_V | PG_KW | ctob(frm);
1203 *(int *)CMAP2 = PG_V | PG_KW | ctob(to);
1204 load_cr3(rcr3());
1205 bcopy(CADDR1, CADDR2, NBPG);
1206}
1207
1208/*aston() {

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1213setsoftclock() {
1214 schednetisr(NETISR_SCLK);
1215}
1216
1217/*
1218 * insert an element into a queue
1219 */
1220#undef insque
1214
1215 *(int *)CMAP1 = PG_V | PG_KW | ctob(frm);
1216 *(int *)CMAP2 = PG_V | PG_KW | ctob(to);
1217 load_cr3(rcr3());
1218 bcopy(CADDR1, CADDR2, NBPG);
1219}
1220
1221/*aston() {

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1226setsoftclock() {
1227 schednetisr(NETISR_SCLK);
1228}
1229
1230/*
1231 * insert an element into a queue
1232 */
1233#undef insque
1234void /* XXX replace with inline FIXME! */
1221_insque(element, head)
1222 register struct prochd *element, *head;
1223{
1224 element->ph_link = head->ph_link;
1225 head->ph_link = (struct proc *)element;
1226 element->ph_rlink = (struct proc *)head;
1227 ((struct prochd *)(element->ph_link))->ph_rlink=(struct proc *)element;
1228}
1229
1230/*
1231 * remove an element from a queue
1232 */
1233#undef remque
1235_insque(element, head)
1236 register struct prochd *element, *head;
1237{
1238 element->ph_link = head->ph_link;
1239 head->ph_link = (struct proc *)element;
1240 element->ph_rlink = (struct proc *)head;
1241 ((struct prochd *)(element->ph_link))->ph_rlink=(struct proc *)element;
1242}
1243
1244/*
1245 * remove an element from a queue
1246 */
1247#undef remque
1248void /* XXX replace with inline FIXME! */
1234_remque(element)
1235 register struct prochd *element;
1236{
1237 ((struct prochd *)(element->ph_link))->ph_rlink = element->ph_rlink;
1238 ((struct prochd *)(element->ph_rlink))->ph_link = element->ph_link;
1239 element->ph_rlink = (struct proc *)0;
1240}
1241

--- 234 unchanged lines hidden --- 		1249_remque(element)
1250 register struct prochd *element;
1251{
1252 ((struct prochd *)(element->ph_link))->ph_rlink = element->ph_rlink;
1253 ((struct prochd *)(element->ph_rlink))->ph_link = element->ph_link;
1254 element->ph_rlink = (struct proc *)0;
1255}
1256

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