| ppbus.4 (56460) | ppbus.4 (57676) |
|---|---|
| 1.\" Copyright (c) 1998, 1999 Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" | 1.\" Copyright (c) 1998, 1999 Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" |
| 25.\" $FreeBSD: head/share/man/man4/ppbus.4 56460 2000-01-23 15:04:20Z asmodai $ | 25.\" $FreeBSD: head/share/man/man4/ppbus.4 57676 2000-03-01 14:50:24Z sheldonh $ |
| 26.\" 27.Dd March 1, 1998 28.Dt PPBUS 4 29.Os FreeBSD 30.Sh NAME 31.Nm ppbus 32.Nd 33Parallel port bus system --- 59 unchanged lines hidden (view full) --- 93.Pp 94The ppbus system provides functions and macros to allocate a new 95parallel port bus, then initialize it and upper peripheral device drivers. 96.Pp 97ppc makes chipset detection and initialization and then calls ppbus attach 98functions to initialize the ppbus system. 99.Sh PARALLEL PORT MODEL 100The logical parallel port model chosen for the ppbus system is the PC's | 26.\" 27.Dd March 1, 1998 28.Dt PPBUS 4 29.Os FreeBSD 30.Sh NAME 31.Nm ppbus 32.Nd 33Parallel port bus system --- 59 unchanged lines hidden (view full) --- 93.Pp 94The ppbus system provides functions and macros to allocate a new 95parallel port bus, then initialize it and upper peripheral device drivers. 96.Pp 97ppc makes chipset detection and initialization and then calls ppbus attach 98functions to initialize the ppbus system. 99.Sh PARALLEL PORT MODEL 100The logical parallel port model chosen for the ppbus system is the PC's |
| 101parallel port model. Consequently, for the i386 implementation of ppbus, | 101parallel port model. 102Consequently, for the i386 implementation of ppbus, |
| 102most of the services provided by ppc are macros for inb() | 103most of the services provided by ppc are macros for inb() |
| 103and outb() calls. But, for an other architecture, accesses to one of our logical | 104and outb() calls. 105But, for an other architecture, accesses to one of our logical |
| 104registers (data, status, control...) may require more than one I/O access. 105.Ss Description 106The parallel port may operate in the following modes: 107.Bl -bullet -item -offset indent 108.It 109compatible mode, also called Centronics mode 110.It 111bidirectional 8/4-bits mode, also called NIBBLE mode --- 8 unchanged lines hidden (view full) --- 120.El 121.Ss Compatible mode 122This mode defines the protocol used by most PCs to transfer data to a printer. 123In this mode, data is placed on the port's data lines, the printer status is 124checked for no errors and that it is not busy, and then a data Strobe is 125generated by the software to clock the data to the printer. 126.Pp 127Many I/O controllers have implemented a mode that uses a FIFO buffer to | 106registers (data, status, control...) may require more than one I/O access. 107.Ss Description 108The parallel port may operate in the following modes: 109.Bl -bullet -item -offset indent 110.It 111compatible mode, also called Centronics mode 112.It 113bidirectional 8/4-bits mode, also called NIBBLE mode --- 8 unchanged lines hidden (view full) --- 122.El 123.Ss Compatible mode 124This mode defines the protocol used by most PCs to transfer data to a printer. 125In this mode, data is placed on the port's data lines, the printer status is 126checked for no errors and that it is not busy, and then a data Strobe is 127generated by the software to clock the data to the printer. 128.Pp 129Many I/O controllers have implemented a mode that uses a FIFO buffer to |
| 128transfer data with the Compatibility mode protocol. This mode is referred to as | 130transfer data with the Compatibility mode protocol. 131This mode is referred to as |
| 129"Fast Centronics" or "Parallel Port FIFO mode". 130.Ss Bidirectional mode 131The NIBBLE mode is the most common way to get reverse channel data from a | 132"Fast Centronics" or "Parallel Port FIFO mode". 133.Ss Bidirectional mode 134The NIBBLE mode is the most common way to get reverse channel data from a |
| 132printer or peripheral. Combined with the standard host to printer mode, it | 135printer or peripheral. 136Combined with the standard host to printer mode, it |
| 133provides a complete bidirectional channel. 134.Pp | 137provides a complete bidirectional channel. 138.Pp |
| 135In this mode, outputs are 8-bits long. Inputs are accomplished by reading | 139In this mode, outputs are 8-bits long. 140Inputs are accomplished by reading |
| 1364 of the 8 bits of the status register. 137.Ss Byte mode | 1414 of the 8 bits of the status register. 142.Ss Byte mode |
| 138In this mode, the data register is used either for outputs and inputs. Then, | 143In this mode, the data register is used either for outputs and inputs. 144Then, |
| 139any transfer is 8-bits long. 140.Ss Extended Capability Port mode 141The ECP protocol was proposed as an advanced mode for communication with | 145any transfer is 8-bits long. 146.Ss Extended Capability Port mode 147The ECP protocol was proposed as an advanced mode for communication with |
| 142printer and scanner type peripherals. Like the EPP protocol, ECP mode provides | 148printer and scanner type peripherals. 149Like the EPP protocol, ECP mode provides |
| 143for a high performance bidirectional communication path between the host 144adapter and the peripheral. 145.Pp 146ECP protocol features include: 147.Bl -item -offset indent 148.It 149Run_Length_Encoding (RLE) data compression for host adapters 150.It 151FIFOs for both the forward and reverse channels 152.It 153DMA as well as programmed I/O for the host register interface. 154.El 155.Ss Enhanced Parallel Port mode 156The EPP protocol was originally developed as a means to provide a high 157performance parallel port link that would still be compatible with the 158standard parallel port. 159.Pp | 150for a high performance bidirectional communication path between the host 151adapter and the peripheral. 152.Pp 153ECP protocol features include: 154.Bl -item -offset indent 155.It 156Run_Length_Encoding (RLE) data compression for host adapters 157.It 158FIFOs for both the forward and reverse channels 159.It 160DMA as well as programmed I/O for the host register interface. 161.El 162.Ss Enhanced Parallel Port mode 163The EPP protocol was originally developed as a means to provide a high 164performance parallel port link that would still be compatible with the 165standard parallel port. 166.Pp |
| 160The EPP mode has two types of cycle: address and data. What makes the | 167The EPP mode has two types of cycle: address and data. 168What makes the |
| 161difference at hardware level is the strobe of the byte placed on the data | 169difference at hardware level is the strobe of the byte placed on the data |
| 162lines. Data are strobed with nAutofeed, addresses are strobed with | 170lines. 171Data are strobed with nAutofeed, addresses are strobed with |
| 163nSelectin signals. 164.Pp 165A particularity of the ISA implementation of the EPP protocol is that an | 172nSelectin signals. 173.Pp 174A particularity of the ISA implementation of the EPP protocol is that an |
| 166EPP cycle fits in an ISA cycle. In this fashion, parallel port peripherals can | 175EPP cycle fits in an ISA cycle. 176In this fashion, parallel port peripherals can |
| 167operate at close to the same performance levels as an equivalent ISA plug-in 168card. 169.Pp 170At software level, you may implement the protocol you wish, using data and | 177operate at close to the same performance levels as an equivalent ISA plug-in 178card. 179.Pp 180At software level, you may implement the protocol you wish, using data and |
| 171address cycles as you want. This is for the IEEE1284 compatible part. Then, | 181address cycles as you want. This is for the IEEE1284 compatible part. 182Then, |
| 172peripheral vendors may implement protocol handshake with the following | 183peripheral vendors may implement protocol handshake with the following |
| 173status lines: PError, nFault and Select. Try to know how these lines toggle | 184status lines: PError, nFault and Select. 185Try to know how these lines toggle |
| 174with your peripheral, allowing the peripheral to request more data, stop the 175transfer and so on. 176.Pp 177At any time, the peripheral may interrupt the host with the nAck signal without 178disturbing the current transfer. 179.Ss Mixed modes 180Some manufacturers, like SMC, have implemented chipsets that support mixed | 186with your peripheral, allowing the peripheral to request more data, stop the 187transfer and so on. 188.Pp 189At any time, the peripheral may interrupt the host with the nAck signal without 190disturbing the current transfer. 191.Ss Mixed modes 192Some manufacturers, like SMC, have implemented chipsets that support mixed |
| 181modes. With such chipsets, mode switching is available at any time by | 193modes. 194With such chipsets, mode switching is available at any time by |
| 182accessing the extended control register. 183.Sh IEEE1284-1994 Standard 184.Ss Background 185This standard is also named "IEEE Standard Signaling Method for a 186Bidirectional Parallel Peripheral Interface for Personal Computers". It 187defines a signaling method for asynchronous, fully interlocked, bidirectional | 195accessing the extended control register. 196.Sh IEEE1284-1994 Standard 197.Ss Background 198This standard is also named "IEEE Standard Signaling Method for a 199Bidirectional Parallel Peripheral Interface for Personal Computers". It 200defines a signaling method for asynchronous, fully interlocked, bidirectional |
| 188parallel communications between hosts and printers or other peripherals. It | 201parallel communications between hosts and printers or other peripherals. 202It |
| 189also specifies a format for a peripheral identification string and a method of 190returning this string to the host outside of the bidirectional data stream. 191.Pp 192This standard is architecture independent and only specifies dialog handshake | 203also specifies a format for a peripheral identification string and a method of 204returning this string to the host outside of the bidirectional data stream. 205.Pp 206This standard is architecture independent and only specifies dialog handshake |
| 193at signal level. One should refer to architecture specific documentation in | 207at signal level. 208One should refer to architecture specific documentation in |
| 194order to manipulate machine dependent registers, mapped memory or other 195methods to control these signals. 196.Pp 197The IEEE1284 protocol is fully oriented with all supported parallel port | 209order to manipulate machine dependent registers, mapped memory or other 210methods to control these signals. 211.Pp 212The IEEE1284 protocol is fully oriented with all supported parallel port |
| 198modes. The computer acts as master and the peripheral as slave. | 213modes. 214The computer acts as master and the peripheral as slave. |
| 199.Pp | 215.Pp |
| 200Any transfer is defined as a finite state automate. It allows software to | 216Any transfer is defined as a finite state automate. 217It allows software to |
| 201properly manage the fully interlocked scheme of the signaling method. 202The compatible mode is supported "as is" without any negotiation because it | 218properly manage the fully interlocked scheme of the signaling method. 219The compatible mode is supported "as is" without any negotiation because it |
| 203is compatible. Any other mode must be firstly negotiated by the host to check | 220is compatible. 221Any other mode must be firstly negotiated by the host to check |
| 204it is supported by the peripheral, then to enter one of the forward idle 205states. 206.Pp | 222it is supported by the peripheral, then to enter one of the forward idle 223states. 224.Pp |
| 207At any time, the slave may want to send data to the host. This is only | 225At any time, the slave may want to send data to the host. 226This is only |
| 208possible from forward idle states (nibble, byte, ecp...). So, the 209host must have previously negotiated to permit the peripheral to | 227possible from forward idle states (nibble, byte, ecp...). So, the 228host must have previously negotiated to permit the peripheral to |
| 210request transfer. Interrupt lines may be dedicated to the requesting signals | 229request transfer. 230Interrupt lines may be dedicated to the requesting signals |
| 211to prevent time consuming polling methods. 212.Pp | 231to prevent time consuming polling methods. 232.Pp |
| 213But peripheral requests are only a hint to the master host. If the host | 233But peripheral requests are only a hint to the master host. 234If the host |
| 214accepts the transfer, it must firstly negotiate the reverse mode and then | 235accepts the transfer, it must firstly negotiate the reverse mode and then |
| 215starts the transfer. At any time during reverse transfer, the host may | 236starts the transfer. 237At any time during reverse transfer, the host may |
| 216terminate the transfer or the slave may drive wires to signal that no more 217data is available. 218.Ss Implementation 219IEEE1284 Standard support has been implemented at the top of the ppbus system 220as a set of procedures that perform high level functions like negotiation, 221termination, transfer in any mode without bothering you with low level 222characteristics of the standard. 223.Pp | 238terminate the transfer or the slave may drive wires to signal that no more 239data is available. 240.Ss Implementation 241IEEE1284 Standard support has been implemented at the top of the ppbus system 242as a set of procedures that perform high level functions like negotiation, 243termination, transfer in any mode without bothering you with low level 244characteristics of the standard. 245.Pp |
| 224IEEE1284 interacts with the ppbus system as least as possible. That means | 246IEEE1284 interacts with the ppbus system as least as possible. 247That means |
| 225you still have to request the ppbus when you want to access it, the negotiate | 248you still have to request the ppbus when you want to access it, the negotiate |
| 226function doesn't do it for you. And of course, release it later. | 249function doesn't do it for you. 250And of course, release it later. |
| 227.Sh ARCHITECTURE 228.Ss adapter, ppbus and device layers 229First, there is the 230.Em adapter | 251.Sh ARCHITECTURE 252.Ss adapter, ppbus and device layers 253First, there is the 254.Em adapter |
| 231layer, the lowest of the ppbus system. It provides | 255layer, the lowest of the ppbus system. 256It provides |
| 232chipset abstraction throw a set of low level functions that maps the logical 233model to the underlying hardware. 234.Pp 235Secondly, there is the 236.Em ppbus 237layer that provides functions to: 238.Bl -enum -offset indent 239.It --- 10 unchanged lines hidden (view full) --- 250.Pp 251.Ss Parallel modes management 252We have to differentiate operating modes at various ppbus system layers. 253Actually, ppbus and adapter operating modes on one hands and for each 254one, current and available modes are separated. 255.Pp 256With this level of abstraction a particular chipset may commute from any 257native mode the any other mode emulated with extended modes without | 257chipset abstraction throw a set of low level functions that maps the logical 258model to the underlying hardware. 259.Pp 260Secondly, there is the 261.Em ppbus 262layer that provides functions to: 263.Bl -enum -offset indent 264.It --- 10 unchanged lines hidden (view full) --- 275.Pp 276.Ss Parallel modes management 277We have to differentiate operating modes at various ppbus system layers. 278Actually, ppbus and adapter operating modes on one hands and for each 279one, current and available modes are separated. 280.Pp 281With this level of abstraction a particular chipset may commute from any 282native mode the any other mode emulated with extended modes without |
| 258disturbing upper layers. For example, most chipsets support NIBBLE mode as | 283disturbing upper layers. 284For example, most chipsets support NIBBLE mode as |
| 259native and emulated with ECP and/or EPP. 260.Pp 261This architecture should support IEEE1284-1994 modes. 262.Sh FEATURES 263.Ss The boot process 264The boot process starts with the probe phasis of the 265.Xr ppc 4 | 285native and emulated with ECP and/or EPP. 286.Pp 287This architecture should support IEEE1284-1994 modes. 288.Sh FEATURES 289.Ss The boot process 290The boot process starts with the probe phasis of the 291.Xr ppc 4 |
| 266driver during ISA bus (PC architecture) initialization. During attachment of | 292driver during ISA bus (PC architecture) initialization. 293During attachment of |
| 267the ppc driver, a new ppbus structure is allocated, then probe and attachment 268for this new bus node are called. 269.Pp 270ppbus attachment tries to detect any PnP parallel peripheral (according to 271.%T "Plug and Play Parallel Port Devices" 272draft from (c)1993-4 Microsoft Corporation) 273then probes and attaches known device drivers. 274.Pp 275During probe, device drivers are supposed to request the ppbus and try to | 294the ppc driver, a new ppbus structure is allocated, then probe and attachment 295for this new bus node are called. 296.Pp 297ppbus attachment tries to detect any PnP parallel peripheral (according to 298.%T "Plug and Play Parallel Port Devices" 299draft from (c)1993-4 Microsoft Corporation) 300then probes and attaches known device drivers. 301.Pp 302During probe, device drivers are supposed to request the ppbus and try to |
| 276set their operating mode. This mode will be saved in the context structure and | 303set their operating mode. 304This mode will be saved in the context structure and |
| 277returned each time the driver requests the ppbus. 278.Ss Bus allocation and interrupts | 305returned each time the driver requests the ppbus. 306.Ss Bus allocation and interrupts |
| 279ppbus allocation is mandatory not to corrupt I/O of other devices. An other | 307ppbus allocation is mandatory not to corrupt I/O of other devices. 308An other |
| 280usage of ppbus allocation is to reserve the port and receive incoming 281interrupts. 282.Pp 283High level interrupt handlers are connected to the ppbus system thanks to the 284newbus 285.Fn BUS_SETUP_INTR 286and 287.Fn BUS_TEARDOWN_INTR | 309usage of ppbus allocation is to reserve the port and receive incoming 310interrupts. 311.Pp 312High level interrupt handlers are connected to the ppbus system thanks to the 313newbus 314.Fn BUS_SETUP_INTR 315and 316.Fn BUS_TEARDOWN_INTR |
| 288functions. But, in order to attach a handler, drivers must 289own the bus. Consequently, a ppbus request is mandatory in order to call the above | 317functions. 318But, in order to attach a handler, drivers must 319own the bus. 320Consequently, a ppbus request is mandatory in order to call the above |
| 290functions (see existing drivers for more info). Note that the interrupt handler 291is automatically released when the ppbus is released. 292.Ss Microsequences 293.Em Microsequences 294is a general purpose mechanism to allow fast low-level | 321functions (see existing drivers for more info). Note that the interrupt handler 322is automatically released when the ppbus is released. 323.Ss Microsequences 324.Em Microsequences 325is a general purpose mechanism to allow fast low-level |
| 295manipulation of the parallel port. Microsequences may be used to do either 296standard (in IEEE1284 modes) or non-standard transfers. The philosophy of | 326manipulation of the parallel port. 327Microsequences may be used to do either 328standard (in IEEE1284 modes) or non-standard transfers. 329The philosophy of |
| 297microsequences is to avoid the overhead of the ppbus layer and do most of 298the job at adapter level. 299.Pp | 330microsequences is to avoid the overhead of the ppbus layer and do most of 331the job at adapter level. 332.Pp |
| 300A microsequence is an array of opcodes and parameters. Each opcode codes an | 333A microsequence is an array of opcodes and parameters. 334Each opcode codes an |
| 301operation (opcodes are described in 302.Xr microseq 9 ). 303Standard I/O operations are implemented at ppbus level whereas basic I/O 304operations and microseq language are coded at adapter level for efficiency. 305.Pp 306As an example, the 307.Xr vpo 4 308driver uses microsequences to implement: --- 21 unchanged lines hidden --- | 335operation (opcodes are described in 336.Xr microseq 9 ). 337Standard I/O operations are implemented at ppbus level whereas basic I/O 338operations and microseq language are coded at adapter level for efficiency. 339.Pp 340As an example, the 341.Xr vpo 4 342driver uses microsequences to implement: --- 21 unchanged lines hidden --- |