| iicbus.4 (56460) | iicbus.4 (57676) |
|---|---|
| 1.\" Copyright (c) 1998, Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" | 1.\" Copyright (c) 1998, Nicolas Souchu 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" |
| 25.\" $FreeBSD: head/share/man/man4/iicbus.4 56460 2000-01-23 15:04:20Z asmodai $ | 25.\" $FreeBSD: head/share/man/man4/iicbus.4 57676 2000-03-01 14:50:24Z sheldonh $ |
| 26.\" 27.Dd August 6, 1998 28.Dt IICBUS 4 29.Os FreeBSD 30.Sh NAME 31.Nm iicbus 32.Nd 33I2C bus system --- 6 unchanged lines hidden (view full) --- 40.Cd "device iicsmb" 41.Sh DESCRIPTION 42The 43.Em iicbus 44system provides a uniform, modular and architecture-independent 45system for the implementation of drivers to control various I2C devices 46and to utilize different I2C controllers. 47.Sh I2C | 26.\" 27.Dd August 6, 1998 28.Dt IICBUS 4 29.Os FreeBSD 30.Sh NAME 31.Nm iicbus 32.Nd 33I2C bus system --- 6 unchanged lines hidden (view full) --- 40.Cd "device iicsmb" 41.Sh DESCRIPTION 42The 43.Em iicbus 44system provides a uniform, modular and architecture-independent 45system for the implementation of drivers to control various I2C devices 46and to utilize different I2C controllers. 47.Sh I2C |
| 48I2C is an acronym for Inter Integrated Circuit bus. The I2C bus was developed 49in the early 1980's by Philips semiconductors. It's purpose was to provide an | 48I2C is an acronym for Inter Integrated Circuit bus. 49The I2C bus was developed 50in the early 1980's by Philips semiconductors. 51It's purpose was to provide an |
| 50easy way to connect a CPU to peripheral chips in a TV-set. 51.Pp 52The BUS physically consists of 2 active wires and a ground connection. | 52easy way to connect a CPU to peripheral chips in a TV-set. 53.Pp 54The BUS physically consists of 2 active wires and a ground connection. |
| 53The active wires, SDA and SCL, are both bidirectional. Where SDA is the | 55The active wires, SDA and SCL, are both bidirectional. 56Where SDA is the |
| 54Serial DAta line and SCL is the Serial CLock line. 55 56Every component hooked up to the bus has its own unique address whether it | 57Serial DAta line and SCL is the Serial CLock line. 58 59Every component hooked up to the bus has its own unique address whether it |
| 57is a CPU, LCD driver, memory, or complex function chip. Each of these chips | 60is a CPU, LCD driver, memory, or complex function chip. 61Each of these chips |
| 58can act as a receiver and/or transmitter depending on it's functionality. 59Obviously an LCD driver is only a receiver, while a memory or I/O chip can | 62can act as a receiver and/or transmitter depending on it's functionality. 63Obviously an LCD driver is only a receiver, while a memory or I/O chip can |
| 60both be transmitter and receiver. Furthermore there may be one or | 64both be transmitter and receiver. 65Furthermore there may be one or |
| 61more BUS MASTER's. 62 | 66more BUS MASTER's. 67 |
| 63The BUS MASTER is the chip issuing the commands on the BUS. In the I2C protocol | 68The BUS MASTER is the chip issuing the commands on the BUS. 69In the I2C protocol |
| 64specification it is stated that the IC that initiates a data transfer on the | 70specification it is stated that the IC that initiates a data transfer on the |
| 65bus is considered the BUS MASTER. At that time all the others are regarded to 66as the BUS SLAVEs. As mentioned before, the IC bus is a Multi-MASTER BUS. | 71bus is considered the BUS MASTER. 72At that time all the others are regarded to 73as the BUS SLAVEs. 74As mentioned before, the IC bus is a Multi-MASTER BUS. |
| 67This means that more than one IC capable of initiating data transfer can be 68connected to it. 69.Sh DEVICES 70Some I2C device drivers are available: 71.Pp 72.Bl -column "Device drivers" -compact 73.It Em Devices Ta Em Description 74.It Sy iic Ta "general i/o operation" 75.It Sy ic Ta "network IP interface" 76.It Sy iicsmb Ta "I2C to SMB software bridge" 77.El 78.Sh INTERFACES | 75This means that more than one IC capable of initiating data transfer can be 76connected to it. 77.Sh DEVICES 78Some I2C device drivers are available: 79.Pp 80.Bl -column "Device drivers" -compact 81.It Em Devices Ta Em Description 82.It Sy iic Ta "general i/o operation" 83.It Sy ic Ta "network IP interface" 84.It Sy iicsmb Ta "I2C to SMB software bridge" 85.El 86.Sh INTERFACES |
| 79The I2C protocol may be implemented by hardware or software. Software | 87The I2C protocol may be implemented by hardware or software. 88Software |
| 80interfaces rely on very simple hardware, usually two lines | 89interfaces rely on very simple hardware, usually two lines |
| 81twiddled by 2 registers. Hardware interfaces are more intelligent and receive | 90twiddled by 2 registers. 91Hardware interfaces are more intelligent and receive |
| 828-bit characters they write to the bus according to the I2C protocol. 83 84I2C interfaces may act on the bus as slave devices, allowing spontaneous 85bidirectional communications, thanks to the mutli-master capabilities of the 86I2C protocol. 87 88Some I2C interfaces are available: 89.Pp --- 20 unchanged lines hidden --- | 928-bit characters they write to the bus according to the I2C protocol. 93 94I2C interfaces may act on the bus as slave devices, allowing spontaneous 95bidirectional communications, thanks to the mutli-master capabilities of the 96I2C protocol. 97 98Some I2C interfaces are available: 99.Pp --- 20 unchanged lines hidden --- |