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fenv.h (176530) fenv.h (226218)
1/*-
2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/lib/msun/powerpc/fenv.h 176530 2008-02-24 19:22:53Z raj $
26 * $FreeBSD: head/lib/msun/powerpc/fenv.h 226218 2011-10-10 15:43:09Z das $
27 */
28
29#ifndef _FENV_H_
30#define _FENV_H_
31
32#include <sys/_types.h>
33
27 */
28
29#ifndef _FENV_H_
30#define _FENV_H_
31
32#include <sys/_types.h>
33
34#ifndef __fenv_static
35#define __fenv_static static
36#endif
37
34typedef __uint32_t fenv_t;
35typedef __uint32_t fexcept_t;
36
37/* Exception flags */
38#define FE_INEXACT 0x02000000
39#define FE_DIVBYZERO 0x04000000
40#define FE_UNDERFLOW 0x08000000
41#define FE_OVERFLOW 0x10000000

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93union __fpscr {
94 double __d;
95 struct {
96 __uint32_t __junk;
97 fenv_t __reg;
98 } __bits;
99};
100
38typedef __uint32_t fenv_t;
39typedef __uint32_t fexcept_t;
40
41/* Exception flags */
42#define FE_INEXACT 0x02000000
43#define FE_DIVBYZERO 0x04000000
44#define FE_UNDERFLOW 0x08000000
45#define FE_OVERFLOW 0x10000000

--- 51 unchanged lines hidden (view full) ---

97union __fpscr {
98 double __d;
99 struct {
100 __uint32_t __junk;
101 fenv_t __reg;
102 } __bits;
103};
104
101static __inline int
105__fenv_static inline int
102feclearexcept(int __excepts)
103{
104 union __fpscr __r;
105
106 if (__excepts & FE_INVALID)
107 __excepts |= FE_ALL_INVALID;
108 __mffs(&__r.__d);
109 __r.__bits.__reg &= ~__excepts;
110 __mtfsf(__r.__d);
111 return (0);
112}
113
106feclearexcept(int __excepts)
107{
108 union __fpscr __r;
109
110 if (__excepts & FE_INVALID)
111 __excepts |= FE_ALL_INVALID;
112 __mffs(&__r.__d);
113 __r.__bits.__reg &= ~__excepts;
114 __mtfsf(__r.__d);
115 return (0);
116}
117
114static __inline int
118__fenv_static inline int
115fegetexceptflag(fexcept_t *__flagp, int __excepts)
116{
117 union __fpscr __r;
118
119 __mffs(&__r.__d);
120 *__flagp = __r.__bits.__reg & __excepts;
121 return (0);
122}
123
119fegetexceptflag(fexcept_t *__flagp, int __excepts)
120{
121 union __fpscr __r;
122
123 __mffs(&__r.__d);
124 *__flagp = __r.__bits.__reg & __excepts;
125 return (0);
126}
127
124static __inline int
128__fenv_static inline int
125fesetexceptflag(const fexcept_t *__flagp, int __excepts)
126{
127 union __fpscr __r;
128
129 if (__excepts & FE_INVALID)
130 __excepts |= FE_ALL_EXCEPT;
131 __mffs(&__r.__d);
132 __r.__bits.__reg &= ~__excepts;
133 __r.__bits.__reg |= *__flagp & __excepts;
134 __mtfsf(__r.__d);
135 return (0);
136}
137
129fesetexceptflag(const fexcept_t *__flagp, int __excepts)
130{
131 union __fpscr __r;
132
133 if (__excepts & FE_INVALID)
134 __excepts |= FE_ALL_EXCEPT;
135 __mffs(&__r.__d);
136 __r.__bits.__reg &= ~__excepts;
137 __r.__bits.__reg |= *__flagp & __excepts;
138 __mtfsf(__r.__d);
139 return (0);
140}
141
138static __inline int
142__fenv_static inline int
139feraiseexcept(int __excepts)
140{
141 union __fpscr __r;
142
143 if (__excepts & FE_INVALID)
144 __excepts |= FE_VXSOFT;
145 __mffs(&__r.__d);
146 __r.__bits.__reg |= __excepts;
147 __mtfsf(__r.__d);
148 return (0);
149}
150
143feraiseexcept(int __excepts)
144{
145 union __fpscr __r;
146
147 if (__excepts & FE_INVALID)
148 __excepts |= FE_VXSOFT;
149 __mffs(&__r.__d);
150 __r.__bits.__reg |= __excepts;
151 __mtfsf(__r.__d);
152 return (0);
153}
154
151static __inline int
155__fenv_static inline int
152fetestexcept(int __excepts)
153{
154 union __fpscr __r;
155
156 __mffs(&__r.__d);
157 return (__r.__bits.__reg & __excepts);
158}
159
156fetestexcept(int __excepts)
157{
158 union __fpscr __r;
159
160 __mffs(&__r.__d);
161 return (__r.__bits.__reg & __excepts);
162}
163
160static __inline int
164__fenv_static inline int
161fegetround(void)
162{
163 union __fpscr __r;
164
165 __mffs(&__r.__d);
166 return (__r.__bits.__reg & _ROUND_MASK);
167}
168
165fegetround(void)
166{
167 union __fpscr __r;
168
169 __mffs(&__r.__d);
170 return (__r.__bits.__reg & _ROUND_MASK);
171}
172
169static __inline int
173__fenv_static inline int
170fesetround(int __round)
171{
172 union __fpscr __r;
173
174 if (__round & ~_ROUND_MASK)
175 return (-1);
176 __mffs(&__r.__d);
177 __r.__bits.__reg &= ~_ROUND_MASK;
178 __r.__bits.__reg |= __round;
179 __mtfsf(__r.__d);
180 return (0);
181}
182
174fesetround(int __round)
175{
176 union __fpscr __r;
177
178 if (__round & ~_ROUND_MASK)
179 return (-1);
180 __mffs(&__r.__d);
181 __r.__bits.__reg &= ~_ROUND_MASK;
182 __r.__bits.__reg |= __round;
183 __mtfsf(__r.__d);
184 return (0);
185}
186
183static __inline int
187__fenv_static inline int
184fegetenv(fenv_t *__envp)
185{
186 union __fpscr __r;
187
188 __mffs(&__r.__d);
189 *__envp = __r.__bits.__reg;
190 return (0);
191}
192
188fegetenv(fenv_t *__envp)
189{
190 union __fpscr __r;
191
192 __mffs(&__r.__d);
193 *__envp = __r.__bits.__reg;
194 return (0);
195}
196
193static __inline int
197__fenv_static inline int
194feholdexcept(fenv_t *__envp)
195{
196 union __fpscr __r;
197
198 __mffs(&__r.__d);
199 *__envp = __r.__d;
200 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
201 __mtfsf(__r.__d);
202 return (0);
203}
204
198feholdexcept(fenv_t *__envp)
199{
200 union __fpscr __r;
201
202 __mffs(&__r.__d);
203 *__envp = __r.__d;
204 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
205 __mtfsf(__r.__d);
206 return (0);
207}
208
205static __inline int
209__fenv_static inline int
206fesetenv(const fenv_t *__envp)
207{
208 union __fpscr __r;
209
210 __r.__bits.__reg = *__envp;
211 __mtfsf(__r.__d);
212 return (0);
213}
214
210fesetenv(const fenv_t *__envp)
211{
212 union __fpscr __r;
213
214 __r.__bits.__reg = *__envp;
215 __mtfsf(__r.__d);
216 return (0);
217}
218
215static __inline int
219__fenv_static inline int
216feupdateenv(const fenv_t *__envp)
217{
218 union __fpscr __r;
219
220 __mffs(&__r.__d);
221 __r.__bits.__reg &= FE_ALL_EXCEPT;
222 __r.__bits.__reg |= *__envp;
223 __mtfsf(__r.__d);
224 return (0);
225}
226
227#if __BSD_VISIBLE
228
220feupdateenv(const fenv_t *__envp)
221{
222 union __fpscr __r;
223
224 __mffs(&__r.__d);
225 __r.__bits.__reg &= FE_ALL_EXCEPT;
226 __r.__bits.__reg |= *__envp;
227 __mtfsf(__r.__d);
228 return (0);
229}
230
231#if __BSD_VISIBLE
232
229static __inline int
233/* We currently provide no external definitions of the functions below. */
234
235static inline int
230feenableexcept(int __mask)
231{
232 union __fpscr __r;
233 fenv_t __oldmask;
234
235 __mffs(&__r.__d);
236 __oldmask = __r.__bits.__reg;
237 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
238 __mtfsf(__r.__d);
239 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
240}
241
236feenableexcept(int __mask)
237{
238 union __fpscr __r;
239 fenv_t __oldmask;
240
241 __mffs(&__r.__d);
242 __oldmask = __r.__bits.__reg;
243 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
244 __mtfsf(__r.__d);
245 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
246}
247
242static __inline int
248static inline int
243fedisableexcept(int __mask)
244{
245 union __fpscr __r;
246 fenv_t __oldmask;
247
248 __mffs(&__r.__d);
249 __oldmask = __r.__bits.__reg;
250 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
251 __mtfsf(__r.__d);
252 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
253}
254
249fedisableexcept(int __mask)
250{
251 union __fpscr __r;
252 fenv_t __oldmask;
253
254 __mffs(&__r.__d);
255 __oldmask = __r.__bits.__reg;
256 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
257 __mtfsf(__r.__d);
258 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
259}
260
255static __inline int
261static inline int
256fegetexcept(void)
257{
258 union __fpscr __r;
259
260 __mffs(&__r.__d);
261 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
262}
263
264#endif /* __BSD_VISIBLE */
265
266__END_DECLS
267
268#endif /* !_FENV_H_ */
262fegetexcept(void)
263{
264 union __fpscr __r;
265
266 __mffs(&__r.__d);
267 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
268}
269
270#endif /* __BSD_VISIBLE */
271
272__END_DECLS
273
274#endif /* !_FENV_H_ */