1/*-
2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: head/lib/msun/arm/fenv.h 226218 2011-10-10 15:43:09Z das $
| 26 * $FreeBSD: head/lib/msun/arm/fenv.h 230192 2012-01-16 04:09:17Z das $
|
27 */
28
29#ifndef _FENV_H_
30#define _FENV_H_
31
32#include <sys/_types.h>
33
34#ifndef __fenv_static
35#define __fenv_static static
36#endif
37
38typedef __uint32_t fenv_t;
39typedef __uint32_t fexcept_t;
40
41/* Exception flags */
42#define FE_INVALID 0x0001
43#define FE_DIVBYZERO 0x0002
44#define FE_OVERFLOW 0x0004
45#define FE_UNDERFLOW 0x0008
46#define FE_INEXACT 0x0010
47#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
48 FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
49
50/* Rounding modes */
51#define FE_TONEAREST 0x0000
52#define FE_TOWARDZERO 0x0001
53#define FE_UPWARD 0x0002
54#define FE_DOWNWARD 0x0003
55#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
56 FE_UPWARD | FE_TOWARDZERO)
57__BEGIN_DECLS
58
59/* Default floating-point environment */
60extern const fenv_t __fe_dfl_env;
61#define FE_DFL_ENV (&__fe_dfl_env)
62
63/* We need to be able to map status flag positions to mask flag positions */
64#define _FPUSW_SHIFT 16
65#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
66
| 27 */
28
29#ifndef _FENV_H_
30#define _FENV_H_
31
32#include <sys/_types.h>
33
34#ifndef __fenv_static
35#define __fenv_static static
36#endif
37
38typedef __uint32_t fenv_t;
39typedef __uint32_t fexcept_t;
40
41/* Exception flags */
42#define FE_INVALID 0x0001
43#define FE_DIVBYZERO 0x0002
44#define FE_OVERFLOW 0x0004
45#define FE_UNDERFLOW 0x0008
46#define FE_INEXACT 0x0010
47#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
48 FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
49
50/* Rounding modes */
51#define FE_TONEAREST 0x0000
52#define FE_TOWARDZERO 0x0001
53#define FE_UPWARD 0x0002
54#define FE_DOWNWARD 0x0003
55#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
56 FE_UPWARD | FE_TOWARDZERO)
57__BEGIN_DECLS
58
59/* Default floating-point environment */
60extern const fenv_t __fe_dfl_env;
61#define FE_DFL_ENV (&__fe_dfl_env)
62
63/* We need to be able to map status flag positions to mask flag positions */
64#define _FPUSW_SHIFT 16
65#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
66
|
67#ifdef ARM_HARD_FLOAT
| 67#ifndef ARM_HARD_FLOAT
68/*
69 * The following macros map between the softfloat emulator's flags and
70 * the hardware's FPSR. The hardware this file was written for doesn't
71 * have rounding control bits, so we stick those in the system ID byte.
72 */
73#define __set_env(env, flags, mask, rnd) env = ((flags) \
74 | (mask)<<_FPUSW_SHIFT \
75 | (rnd) << 24)
76#define __env_flags(env) ((env) & FE_ALL_EXCEPT)
77#define __env_mask(env) (((env) >> _FPUSW_SHIFT) \
78 & FE_ALL_EXCEPT)
79#define __env_round(env) (((env) >> 24) & _ROUND_MASK)
80#include <fenv-softfloat.h>
81
82#else /* ARM_HARD_FLOAT */
83
|
68#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr)))
69#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr))
| 84#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr)))
85#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr))
|
70#else
71#define __rfs(__fpsr)
72#define __wfs(__fpsr)
73#endif
| |
74
75__fenv_static inline int
76feclearexcept(int __excepts)
77{
78 fexcept_t __fpsr;
79
80 __rfs(&__fpsr);
81 __fpsr &= ~__excepts;
82 __wfs(__fpsr);
83 return (0);
84}
85
86__fenv_static inline int
87fegetexceptflag(fexcept_t *__flagp, int __excepts)
88{
89 fexcept_t __fpsr;
90
91 __rfs(&__fpsr);
92 *__flagp = __fpsr & __excepts;
93 return (0);
94}
95
96__fenv_static inline int
97fesetexceptflag(const fexcept_t *__flagp, int __excepts)
98{
99 fexcept_t __fpsr;
100
101 __rfs(&__fpsr);
102 __fpsr &= ~__excepts;
103 __fpsr |= *__flagp & __excepts;
104 __wfs(__fpsr);
105 return (0);
106}
107
108__fenv_static inline int
109feraiseexcept(int __excepts)
110{
111 fexcept_t __ex = __excepts;
112
113 fesetexceptflag(&__ex, __excepts); /* XXX */
114 return (0);
115}
116
117__fenv_static inline int
118fetestexcept(int __excepts)
119{
120 fexcept_t __fpsr;
121
122 __rfs(&__fpsr);
123 return (__fpsr & __excepts);
124}
125
126__fenv_static inline int
127fegetround(void)
128{
129
130 /*
131 * Apparently, the rounding mode is specified as part of the
132 * instruction format on ARM, so the dynamic rounding mode is
133 * indeterminate. Some FPUs may differ.
134 */
135 return (-1);
136}
137
138__fenv_static inline int
139fesetround(int __round)
140{
141
142 return (-1);
143}
144
145__fenv_static inline int
146fegetenv(fenv_t *__envp)
147{
148
149 __rfs(__envp);
150 return (0);
151}
152
153__fenv_static inline int
154feholdexcept(fenv_t *__envp)
155{
156 fenv_t __env;
157
158 __rfs(&__env);
159 *__envp = __env;
160 __env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
161 __wfs(__env);
162 return (0);
163}
164
165__fenv_static inline int
166fesetenv(const fenv_t *__envp)
167{
168
169 __wfs(*__envp);
170 return (0);
171}
172
173__fenv_static inline int
174feupdateenv(const fenv_t *__envp)
175{
176 fexcept_t __fpsr;
177
178 __rfs(&__fpsr);
179 __wfs(*__envp);
180 feraiseexcept(__fpsr & FE_ALL_EXCEPT);
181 return (0);
182}
183
184#if __BSD_VISIBLE
185
186/* We currently provide no external definitions of the functions below. */
187
188static inline int
189feenableexcept(int __mask)
190{
191 fenv_t __old_fpsr, __new_fpsr;
192
193 __rfs(&__old_fpsr);
194 __new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT;
195 __wfs(__new_fpsr);
196 return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
197}
198
199static inline int
200fedisableexcept(int __mask)
201{
202 fenv_t __old_fpsr, __new_fpsr;
203
204 __rfs(&__old_fpsr);
205 __new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
206 __wfs(__new_fpsr);
207 return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
208}
209
210static inline int
211fegetexcept(void)
212{
213 fenv_t __fpsr;
214
215 __rfs(&__fpsr);
216 return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT);
217}
218
219#endif /* __BSD_VISIBLE */
220
| 86
87__fenv_static inline int
88feclearexcept(int __excepts)
89{
90 fexcept_t __fpsr;
91
92 __rfs(&__fpsr);
93 __fpsr &= ~__excepts;
94 __wfs(__fpsr);
95 return (0);
96}
97
98__fenv_static inline int
99fegetexceptflag(fexcept_t *__flagp, int __excepts)
100{
101 fexcept_t __fpsr;
102
103 __rfs(&__fpsr);
104 *__flagp = __fpsr & __excepts;
105 return (0);
106}
107
108__fenv_static inline int
109fesetexceptflag(const fexcept_t *__flagp, int __excepts)
110{
111 fexcept_t __fpsr;
112
113 __rfs(&__fpsr);
114 __fpsr &= ~__excepts;
115 __fpsr |= *__flagp & __excepts;
116 __wfs(__fpsr);
117 return (0);
118}
119
120__fenv_static inline int
121feraiseexcept(int __excepts)
122{
123 fexcept_t __ex = __excepts;
124
125 fesetexceptflag(&__ex, __excepts); /* XXX */
126 return (0);
127}
128
129__fenv_static inline int
130fetestexcept(int __excepts)
131{
132 fexcept_t __fpsr;
133
134 __rfs(&__fpsr);
135 return (__fpsr & __excepts);
136}
137
138__fenv_static inline int
139fegetround(void)
140{
141
142 /*
143 * Apparently, the rounding mode is specified as part of the
144 * instruction format on ARM, so the dynamic rounding mode is
145 * indeterminate. Some FPUs may differ.
146 */
147 return (-1);
148}
149
150__fenv_static inline int
151fesetround(int __round)
152{
153
154 return (-1);
155}
156
157__fenv_static inline int
158fegetenv(fenv_t *__envp)
159{
160
161 __rfs(__envp);
162 return (0);
163}
164
165__fenv_static inline int
166feholdexcept(fenv_t *__envp)
167{
168 fenv_t __env;
169
170 __rfs(&__env);
171 *__envp = __env;
172 __env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
173 __wfs(__env);
174 return (0);
175}
176
177__fenv_static inline int
178fesetenv(const fenv_t *__envp)
179{
180
181 __wfs(*__envp);
182 return (0);
183}
184
185__fenv_static inline int
186feupdateenv(const fenv_t *__envp)
187{
188 fexcept_t __fpsr;
189
190 __rfs(&__fpsr);
191 __wfs(*__envp);
192 feraiseexcept(__fpsr & FE_ALL_EXCEPT);
193 return (0);
194}
195
196#if __BSD_VISIBLE
197
198/* We currently provide no external definitions of the functions below. */
199
200static inline int
201feenableexcept(int __mask)
202{
203 fenv_t __old_fpsr, __new_fpsr;
204
205 __rfs(&__old_fpsr);
206 __new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT;
207 __wfs(__new_fpsr);
208 return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
209}
210
211static inline int
212fedisableexcept(int __mask)
213{
214 fenv_t __old_fpsr, __new_fpsr;
215
216 __rfs(&__old_fpsr);
217 __new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
218 __wfs(__new_fpsr);
219 return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
220}
221
222static inline int
223fegetexcept(void)
224{
225 fenv_t __fpsr;
226
227 __rfs(&__fpsr);
228 return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT);
229}
230
231#endif /* __BSD_VISIBLE */
232
|
| 233#endif /* ARM_HARD_FLOAT */
234
|
221__END_DECLS
222
223#endif /* !_FENV_H_ */
| 235__END_DECLS
236
237#endif /* !_FENV_H_ */
|