1.\" Copyright (c) 2009, 2010 Rui Paulo. All rights reserved.
2.\"
3.\" Redistribution and use in source and binary forms, with or without
4.\" modification, are permitted provided that the following conditions
5.\" are met:
6.\" 1. Redistributions of source code must retain the above copyright
7.\" notice, this list of conditions and the following disclaimer.
8.\" 2. Redistributions in binary form must reproduce the above copyright
9.\" notice, this list of conditions and the following disclaimer in the
10.\" documentation and/or other materials provided with the distribution.
11.\"
12.\" This software is provided by Rui Paulo ``as is'' and
13.\" any express or implied warranties, including, but not limited to, the
14.\" implied warranties of merchantability and fitness for a particular purpose
15.\" are disclaimed. in no event shall Joseph Koshy be liable
16.\" for any direct, indirect, incidental, special, exemplary, or consequential
17.\" damages (including, but not limited to, procurement of substitute goods
18.\" or services; loss of use, data, or profits; or business interruption)
19.\" however caused and on any theory of liability, whether in contract, strict
20.\" liability, or tort (including negligence or otherwise) arising in any way
21.\" out of the use of this software, even if advised of the possibility of
22.\" such damage.
23.\"
| 1.\" Copyright (c) 2009, 2010 Rui Paulo. All rights reserved.
2.\"
3.\" Redistribution and use in source and binary forms, with or without
4.\" modification, are permitted provided that the following conditions
5.\" are met:
6.\" 1. Redistributions of source code must retain the above copyright
7.\" notice, this list of conditions and the following disclaimer.
8.\" 2. Redistributions in binary form must reproduce the above copyright
9.\" notice, this list of conditions and the following disclaimer in the
10.\" documentation and/or other materials provided with the distribution.
11.\"
12.\" This software is provided by Rui Paulo ``as is'' and
13.\" any express or implied warranties, including, but not limited to, the
14.\" implied warranties of merchantability and fitness for a particular purpose
15.\" are disclaimed. in no event shall Joseph Koshy be liable
16.\" for any direct, indirect, incidental, special, exemplary, or consequential
17.\" damages (including, but not limited to, procurement of substitute goods
18.\" or services; loss of use, data, or profits; or business interruption)
19.\" however caused and on any theory of liability, whether in contract, strict
20.\" liability, or tort (including negligence or otherwise) arising in any way
21.\" out of the use of this software, even if advised of the possibility of
22.\" such damage.
23.\"
|
25.\"
26.Dd December 23, 2009
27.Os
28.Dt PMC.XSCALE 3
29.Sh NAME
30.Nm pmc.xscale
31.Nd measurement events for
32.Tn Intel
33.Tn XScale
34family CPUs
35.Sh LIBRARY
36.Lb libpmc
37.Sh SYNOPSIS
38.In pmc.h
39.Sh DESCRIPTION
40.Tn Intel XScale
41CPUs are ARM CPUs based on the ARMv5e core.
42.Pp
43Second generation cores have 2 counters, while third generation cores
44have 4 counters.
45Third generation cores also have an increased number of PMC events.
46.Pp
47.Tn Intel XScale
48PMCs are documented in
49.Rs
50.%B "3rd Generation Intel XScale Microarchitecture Developer's Manual"
51.%D May 2007
52.Re
53.Ss Event Specifiers (Programmable PMCs)
54.Tn Intel XScale
55programmable PMCs support the following events:
56.Bl -tag -width indent
57.It Li IC_FETCH
58External memory fetch due to L1 instruction cache miss.
59.It Li IC_MISS
60Instruction cache or TLB miss.
61.It Li DATA_DEPENDENCY_STALLED
62A data dependency stalled
63.It Li ITLB_MISS
64Instruction TLB miss.
65.It Li DTLB_MISS
66Data TLB miss.
67.It Li BRANCH_RETIRED
68Branch instruction retired (executed).
69.It Li BRANCH_MISPRED
70Branch mispredicted.
71.It Li INSTR_RETIRED
72Instructions retired (executed).
73.It Li DC_FULL_CYCLE
74L1 data cache buffer full stall.
75Event occurs on every cycle the
76condition is present.
77.It Li DC_FULL_CONTIG
78L1 data cache buffer full stall.
79Event occurs once for each contiguous sequence of this type of stall.
80.It Li DC_ACCESS
81L1 data cache access, not including cache operations.
82.It Li DC_MISS
83L1 data cache miss, not including cache operations.
84.It Li DC_WRITEBACK
85L1 data cache write-back.
86Occurs for each cache line that's written back from the cache.
87.It Li PC_CHANGE
88Software changed the program counter.
89.It Li BRANCH_RETIRED_ALL
90Branch instruction retired (executed).
91This event counts all branch instructions, indirect or direct.
92.It Li INSTR_CYCLE
93Count the number of microarchitecture cycles each instruction requires
94to issue.
95.It Li CP_STALL
96Coprocessor stalled the instruction pipeline.
97.It Li PC_CHANGE_ALL
98Software changed the program counter (includes exceptions).
99.It Li PIPELINE_FLUSH
100Pipeline flushes due to mispredictions or exceptions.
101.It Li BACKEND_STALL
102Backend stalled the instruction pipeline.
103.It Li MULTIPLIER_USE
104Multiplier used.
105.It Li MULTIPLIER_STALLED
106Multiplier stalled the instruction pipeline.
107.It Li DATA_CACHE_STALLED
108Data cache stalled the instruction pipeline.
109.It Li L2_CACHE_REQ
110L2 cache request, not inclusing cache operations.
111.It Li L2_CACHE_MISS
112L2 cache miss, not including cache operations.
113.It Li ADDRESS_BUS_TRANS
114Address bus transaction.
115.It Li SELF_ADDRESS_BUS_TRANS
116Self initiated address bus transaction.
117.It Li DATA_BUS_TRANS
118Data bus transaction.
119.El
120.Ss Event Name Aliases
121The following table shows the mapping between the PMC-independent
122aliases supported by
123.Lb libpmc
124and the underlying hardware events used.
125.Bl -column "branch-mispredicts" "BRANCH_MISPRED"
126.It Em Alias Ta Em Event Ta
127.It Li branches Ta Li BRANCH_RETIRED Ta
128.It Li branch-mispredicts Ta Li BRANCH_MISPRED Ta
129.It Li dc-misses Ta Li DC_MISS Ta
130.It Li ic-misses Ta Li IC_MISS Ta
131.It Li instructions Ta Li INSTR_RETIRED Ta
132.El
133.Sh SEE ALSO
134.Xr pmc 3 ,
135.Xr pmc_cpuinfo 3 ,
136.Xr pmclog 3 ,
137.Xr hwpmc 4
| 25.\"
26.Dd December 23, 2009
27.Os
28.Dt PMC.XSCALE 3
29.Sh NAME
30.Nm pmc.xscale
31.Nd measurement events for
32.Tn Intel
33.Tn XScale
34family CPUs
35.Sh LIBRARY
36.Lb libpmc
37.Sh SYNOPSIS
38.In pmc.h
39.Sh DESCRIPTION
40.Tn Intel XScale
41CPUs are ARM CPUs based on the ARMv5e core.
42.Pp
43Second generation cores have 2 counters, while third generation cores
44have 4 counters.
45Third generation cores also have an increased number of PMC events.
46.Pp
47.Tn Intel XScale
48PMCs are documented in
49.Rs
50.%B "3rd Generation Intel XScale Microarchitecture Developer's Manual"
51.%D May 2007
52.Re
53.Ss Event Specifiers (Programmable PMCs)
54.Tn Intel XScale
55programmable PMCs support the following events:
56.Bl -tag -width indent
57.It Li IC_FETCH
58External memory fetch due to L1 instruction cache miss.
59.It Li IC_MISS
60Instruction cache or TLB miss.
61.It Li DATA_DEPENDENCY_STALLED
62A data dependency stalled
63.It Li ITLB_MISS
64Instruction TLB miss.
65.It Li DTLB_MISS
66Data TLB miss.
67.It Li BRANCH_RETIRED
68Branch instruction retired (executed).
69.It Li BRANCH_MISPRED
70Branch mispredicted.
71.It Li INSTR_RETIRED
72Instructions retired (executed).
73.It Li DC_FULL_CYCLE
74L1 data cache buffer full stall.
75Event occurs on every cycle the
76condition is present.
77.It Li DC_FULL_CONTIG
78L1 data cache buffer full stall.
79Event occurs once for each contiguous sequence of this type of stall.
80.It Li DC_ACCESS
81L1 data cache access, not including cache operations.
82.It Li DC_MISS
83L1 data cache miss, not including cache operations.
84.It Li DC_WRITEBACK
85L1 data cache write-back.
86Occurs for each cache line that's written back from the cache.
87.It Li PC_CHANGE
88Software changed the program counter.
89.It Li BRANCH_RETIRED_ALL
90Branch instruction retired (executed).
91This event counts all branch instructions, indirect or direct.
92.It Li INSTR_CYCLE
93Count the number of microarchitecture cycles each instruction requires
94to issue.
95.It Li CP_STALL
96Coprocessor stalled the instruction pipeline.
97.It Li PC_CHANGE_ALL
98Software changed the program counter (includes exceptions).
99.It Li PIPELINE_FLUSH
100Pipeline flushes due to mispredictions or exceptions.
101.It Li BACKEND_STALL
102Backend stalled the instruction pipeline.
103.It Li MULTIPLIER_USE
104Multiplier used.
105.It Li MULTIPLIER_STALLED
106Multiplier stalled the instruction pipeline.
107.It Li DATA_CACHE_STALLED
108Data cache stalled the instruction pipeline.
109.It Li L2_CACHE_REQ
110L2 cache request, not inclusing cache operations.
111.It Li L2_CACHE_MISS
112L2 cache miss, not including cache operations.
113.It Li ADDRESS_BUS_TRANS
114Address bus transaction.
115.It Li SELF_ADDRESS_BUS_TRANS
116Self initiated address bus transaction.
117.It Li DATA_BUS_TRANS
118Data bus transaction.
119.El
120.Ss Event Name Aliases
121The following table shows the mapping between the PMC-independent
122aliases supported by
123.Lb libpmc
124and the underlying hardware events used.
125.Bl -column "branch-mispredicts" "BRANCH_MISPRED"
126.It Em Alias Ta Em Event Ta
127.It Li branches Ta Li BRANCH_RETIRED Ta
128.It Li branch-mispredicts Ta Li BRANCH_MISPRED Ta
129.It Li dc-misses Ta Li DC_MISS Ta
130.It Li ic-misses Ta Li IC_MISS Ta
131.It Li instructions Ta Li INSTR_RETIRED Ta
132.El
133.Sh SEE ALSO
134.Xr pmc 3 ,
135.Xr pmc_cpuinfo 3 ,
136.Xr pmclog 3 ,
137.Xr hwpmc 4
|