1/*
2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
4 *
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
8 *
9 * All advertising materials mentioning features or use of this software
10 * must display the following acknowledgement:
11 * This product includes software developed by the University of
12 * California, Lawrence Berkeley Laboratory.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. All advertising materials mentioning features or use of this software
23 * must display the following acknowledgement:
24 * This product includes software developed by the University of
25 * California, Berkeley and its contributors.
26 * 4. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
41 *
42 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
43 * $NetBSD: fpu_implode.c,v 1.8 2001/08/26 05:44:46 eeh Exp $
44 */
45
46#include <sys/cdefs.h>
| 1/*
2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
4 *
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
8 *
9 * All advertising materials mentioning features or use of this software
10 * must display the following acknowledgement:
11 * This product includes software developed by the University of
12 * California, Lawrence Berkeley Laboratory.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. All advertising materials mentioning features or use of this software
23 * must display the following acknowledgement:
24 * This product includes software developed by the University of
25 * California, Berkeley and its contributors.
26 * 4. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
41 *
42 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
43 * $NetBSD: fpu_implode.c,v 1.8 2001/08/26 05:44:46 eeh Exp $
44 */
45
46#include <sys/cdefs.h>
|
47__FBSDID("$FreeBSD: head/lib/libc/sparc64/fpu/fpu_implode.c 92986 2002-03-22 21:53:29Z obrien $");
| 47__FBSDID("$FreeBSD: head/lib/libc/sparc64/fpu/fpu_implode.c 95587 2002-04-27 21:56:28Z jake $");
|
48
49/*
50 * FPU subroutines: `implode' internal format numbers into the machine's
51 * `packed binary' format.
52 */
53
54#include <sys/param.h>
55
56#include <machine/frame.h>
57#include <machine/fp.h>
58#include <machine/fsr.h>
59#include <machine/ieee.h>
60#include <machine/instr.h>
61
62#include "fpu_arith.h"
63#include "fpu_emu.h"
64#include "fpu_extern.h"
| 48
49/*
50 * FPU subroutines: `implode' internal format numbers into the machine's
51 * `packed binary' format.
52 */
53
54#include <sys/param.h>
55
56#include <machine/frame.h>
57#include <machine/fp.h>
58#include <machine/fsr.h>
59#include <machine/ieee.h>
60#include <machine/instr.h>
61
62#include "fpu_arith.h"
63#include "fpu_emu.h"
64#include "fpu_extern.h"
|
| 65#include "__sparc_utrap_private.h"
|
65
66static int round(struct fpemu *, struct fpn *);
67static int toinf(struct fpemu *, int);
68
69/*
70 * Round a number (algorithm from Motorola MC68882 manual, modified for
71 * our internal format). Set inexact exception if rounding is required.
72 * Return true iff we rounded up.
73 *
74 * After rounding, we discard the guard and round bits by shifting right
75 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
76 * This saves effort later.
77 *
78 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
79 * responsibility to fix this if necessary.
80 */
81static int
82round(struct fpemu *fe, struct fpn *fp)
83{
84 u_int m0, m1, m2, m3;
85 int gr, s;
86
87 m0 = fp->fp_mant[0];
88 m1 = fp->fp_mant[1];
89 m2 = fp->fp_mant[2];
90 m3 = fp->fp_mant[3];
91 gr = m3 & 3;
92 s = fp->fp_sticky;
93
94 /* mant >>= FP_NG */
95 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
96 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
97 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
98 m0 >>= FP_NG;
99
100 if ((gr | s) == 0) /* result is exact: no rounding needed */
101 goto rounddown;
102
103 fe->fe_cx |= FSR_NX; /* inexact */
104
105 /* Go to rounddown to round down; break to round up. */
106 switch (FSR_GET_RD(fe->fe_fsr)) {
107 case FSR_RD_N:
108 default:
109 /*
110 * Round only if guard is set (gr & 2). If guard is set,
111 * but round & sticky both clear, then we want to round
112 * but have a tie, so round to even, i.e., add 1 iff odd.
113 */
114 if ((gr & 2) == 0)
115 goto rounddown;
116 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
117 break;
118 goto rounddown;
119
120 case FSR_RD_Z:
121 /* Round towards zero, i.e., down. */
122 goto rounddown;
123
124 case FSR_RD_NINF:
125 /* Round towards -Inf: up if negative, down if positive. */
126 if (fp->fp_sign)
127 break;
128 goto rounddown;
129
130 case FSR_RD_PINF:
131 /* Round towards +Inf: up if positive, down otherwise. */
132 if (!fp->fp_sign)
133 break;
134 goto rounddown;
135 }
136
137 /* Bump low bit of mantissa, with carry. */
138 FPU_ADDS(m3, m3, 1);
139 FPU_ADDCS(m2, m2, 0);
140 FPU_ADDCS(m1, m1, 0);
141 FPU_ADDC(m0, m0, 0);
142 fp->fp_mant[0] = m0;
143 fp->fp_mant[1] = m1;
144 fp->fp_mant[2] = m2;
145 fp->fp_mant[3] = m3;
146 return (1);
147
148rounddown:
149 fp->fp_mant[0] = m0;
150 fp->fp_mant[1] = m1;
151 fp->fp_mant[2] = m2;
152 fp->fp_mant[3] = m3;
153 return (0);
154}
155
156/*
157 * For overflow: return true if overflow is to go to +/-Inf, according
158 * to the sign of the overflowing result. If false, overflow is to go
159 * to the largest magnitude value instead.
160 */
161static int
162toinf(struct fpemu *fe, int sign)
163{
164 int inf;
165
166 /* look at rounding direction */
167 switch (FSR_GET_RD(fe->fe_fsr)) {
168 default:
169 case FSR_RD_N: /* the nearest value is always Inf */
170 inf = 1;
171 break;
172
173 case FSR_RD_Z: /* toward 0 => never towards Inf */
174 inf = 0;
175 break;
176
177 case FSR_RD_PINF: /* toward +Inf iff positive */
178 inf = sign == 0;
179 break;
180
181 case FSR_RD_NINF: /* toward -Inf iff negative */
182 inf = sign;
183 break;
184 }
185 return (inf);
186}
187
188/*
189 * fpn -> int (int value returned as return value).
190 *
191 * N.B.: this conversion always rounds towards zero (this is a peculiarity
192 * of the SPARC instruction set).
193 */
194u_int
195__fpu_ftoi(fe, fp)
196 struct fpemu *fe;
197 struct fpn *fp;
198{
199 u_int i;
200 int sign, exp;
201
202 sign = fp->fp_sign;
203 switch (fp->fp_class) {
204
205 case FPC_ZERO:
206 return (0);
207
208 case FPC_NUM:
209 /*
210 * If exp >= 2^32, overflow. Otherwise shift value right
211 * into last mantissa word (this will not exceed 0xffffffff),
212 * shifting any guard and round bits out into the sticky
213 * bit. Then ``round'' towards zero, i.e., just set an
214 * inexact exception if sticky is set (see round()).
215 * If the result is > 0x80000000, or is positive and equals
216 * 0x80000000, overflow; otherwise the last fraction word
217 * is the result.
218 */
219 if ((exp = fp->fp_exp) >= 32)
220 break;
221 /* NB: the following includes exp < 0 cases */
222 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
223 fe->fe_cx |= FSR_NX;
224 i = fp->fp_mant[3];
225 if (i >= ((u_int)0x80000000 + sign))
226 break;
227 return (sign ? -i : i);
228
229 default: /* Inf, qNaN, sNaN */
230 break;
231 }
232 /* overflow: replace any inexact exception with invalid */
233 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
234 return (0x7fffffff + sign);
235}
236
237/*
238 * fpn -> extended int (high bits of int value returned as return value).
239 *
240 * N.B.: this conversion always rounds towards zero (this is a peculiarity
241 * of the SPARC instruction set).
242 */
243u_int
244__fpu_ftox(fe, fp, res)
245 struct fpemu *fe;
246 struct fpn *fp;
247 u_int *res;
248{
249 u_int64_t i;
250 int sign, exp;
251
252 sign = fp->fp_sign;
253 switch (fp->fp_class) {
254
255 case FPC_ZERO:
256 res[1] = 0;
257 return (0);
258
259 case FPC_NUM:
260 /*
261 * If exp >= 2^64, overflow. Otherwise shift value right
262 * into last mantissa word (this will not exceed 0xffffffffffffffff),
263 * shifting any guard and round bits out into the sticky
264 * bit. Then ``round'' towards zero, i.e., just set an
265 * inexact exception if sticky is set (see round()).
266 * If the result is > 0x8000000000000000, or is positive and equals
267 * 0x8000000000000000, overflow; otherwise the last fraction word
268 * is the result.
269 */
270 if ((exp = fp->fp_exp) >= 64)
271 break;
272 /* NB: the following includes exp < 0 cases */
273 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
274 fe->fe_cx |= FSR_NX;
275 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
276 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
277 break;
278 if (sign)
279 i = -1;
280 res[1] = (int)i;
281 return (i >> 32);
282
283 default: /* Inf, qNaN, sNaN */
284 break;
285 }
286 /* overflow: replace any inexact exception with invalid */
287 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
288 return (0x7fffffffffffffffLL + sign);
289}
290
291/*
292 * fpn -> single (32 bit single returned as return value).
293 * We assume <= 29 bits in a single-precision fraction (1.f part).
294 */
295u_int
296__fpu_ftos(fe, fp)
297 struct fpemu *fe;
298 struct fpn *fp;
299{
300 u_int sign = fp->fp_sign << 31;
301 int exp;
302
303#define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
304#define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
305
306 /* Take care of non-numbers first. */
307 if (ISNAN(fp)) {
308 /*
309 * Preserve upper bits of NaN, per SPARC V8 appendix N.
310 * Note that fp->fp_mant[0] has the quiet bit set,
311 * even if it is classified as a signalling NaN.
312 */
313 (void) __fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
314 exp = SNG_EXP_INFNAN;
315 goto done;
316 }
317 if (ISINF(fp))
318 return (sign | SNG_EXP(SNG_EXP_INFNAN));
319 if (ISZERO(fp))
320 return (sign);
321
322 /*
323 * Normals (including subnormals). Drop all the fraction bits
324 * (including the explicit ``implied'' 1 bit) down into the
325 * single-precision range. If the number is subnormal, move
326 * the ``implied'' 1 into the explicit range as well, and shift
327 * right to introduce leading zeroes. Rounding then acts
328 * differently for normals and subnormals: the largest subnormal
329 * may round to the smallest normal (1.0 x 2^minexp), or may
330 * remain subnormal. In the latter case, signal an underflow
331 * if the result was inexact or if underflow traps are enabled.
332 *
333 * Rounding a normal, on the other hand, always produces another
334 * normal (although either way the result might be too big for
335 * single precision, and cause an overflow). If rounding a
336 * normal produces 2.0 in the fraction, we need not adjust that
337 * fraction at all, since both 1.0 and 2.0 are zero under the
338 * fraction mask.
339 *
340 * Note that the guard and round bits vanish from the number after
341 * rounding.
342 */
343 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
344 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
345 (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
346 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
347 return (sign | SNG_EXP(1) | 0);
348 if ((fe->fe_cx & FSR_NX) ||
349 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
350 fe->fe_cx |= FSR_UF;
351 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
352 }
353 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
354 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
355#ifdef DIAGNOSTIC
356 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
| 66
67static int round(struct fpemu *, struct fpn *);
68static int toinf(struct fpemu *, int);
69
70/*
71 * Round a number (algorithm from Motorola MC68882 manual, modified for
72 * our internal format). Set inexact exception if rounding is required.
73 * Return true iff we rounded up.
74 *
75 * After rounding, we discard the guard and round bits by shifting right
76 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
77 * This saves effort later.
78 *
79 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
80 * responsibility to fix this if necessary.
81 */
82static int
83round(struct fpemu *fe, struct fpn *fp)
84{
85 u_int m0, m1, m2, m3;
86 int gr, s;
87
88 m0 = fp->fp_mant[0];
89 m1 = fp->fp_mant[1];
90 m2 = fp->fp_mant[2];
91 m3 = fp->fp_mant[3];
92 gr = m3 & 3;
93 s = fp->fp_sticky;
94
95 /* mant >>= FP_NG */
96 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
97 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
98 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
99 m0 >>= FP_NG;
100
101 if ((gr | s) == 0) /* result is exact: no rounding needed */
102 goto rounddown;
103
104 fe->fe_cx |= FSR_NX; /* inexact */
105
106 /* Go to rounddown to round down; break to round up. */
107 switch (FSR_GET_RD(fe->fe_fsr)) {
108 case FSR_RD_N:
109 default:
110 /*
111 * Round only if guard is set (gr & 2). If guard is set,
112 * but round & sticky both clear, then we want to round
113 * but have a tie, so round to even, i.e., add 1 iff odd.
114 */
115 if ((gr & 2) == 0)
116 goto rounddown;
117 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
118 break;
119 goto rounddown;
120
121 case FSR_RD_Z:
122 /* Round towards zero, i.e., down. */
123 goto rounddown;
124
125 case FSR_RD_NINF:
126 /* Round towards -Inf: up if negative, down if positive. */
127 if (fp->fp_sign)
128 break;
129 goto rounddown;
130
131 case FSR_RD_PINF:
132 /* Round towards +Inf: up if positive, down otherwise. */
133 if (!fp->fp_sign)
134 break;
135 goto rounddown;
136 }
137
138 /* Bump low bit of mantissa, with carry. */
139 FPU_ADDS(m3, m3, 1);
140 FPU_ADDCS(m2, m2, 0);
141 FPU_ADDCS(m1, m1, 0);
142 FPU_ADDC(m0, m0, 0);
143 fp->fp_mant[0] = m0;
144 fp->fp_mant[1] = m1;
145 fp->fp_mant[2] = m2;
146 fp->fp_mant[3] = m3;
147 return (1);
148
149rounddown:
150 fp->fp_mant[0] = m0;
151 fp->fp_mant[1] = m1;
152 fp->fp_mant[2] = m2;
153 fp->fp_mant[3] = m3;
154 return (0);
155}
156
157/*
158 * For overflow: return true if overflow is to go to +/-Inf, according
159 * to the sign of the overflowing result. If false, overflow is to go
160 * to the largest magnitude value instead.
161 */
162static int
163toinf(struct fpemu *fe, int sign)
164{
165 int inf;
166
167 /* look at rounding direction */
168 switch (FSR_GET_RD(fe->fe_fsr)) {
169 default:
170 case FSR_RD_N: /* the nearest value is always Inf */
171 inf = 1;
172 break;
173
174 case FSR_RD_Z: /* toward 0 => never towards Inf */
175 inf = 0;
176 break;
177
178 case FSR_RD_PINF: /* toward +Inf iff positive */
179 inf = sign == 0;
180 break;
181
182 case FSR_RD_NINF: /* toward -Inf iff negative */
183 inf = sign;
184 break;
185 }
186 return (inf);
187}
188
189/*
190 * fpn -> int (int value returned as return value).
191 *
192 * N.B.: this conversion always rounds towards zero (this is a peculiarity
193 * of the SPARC instruction set).
194 */
195u_int
196__fpu_ftoi(fe, fp)
197 struct fpemu *fe;
198 struct fpn *fp;
199{
200 u_int i;
201 int sign, exp;
202
203 sign = fp->fp_sign;
204 switch (fp->fp_class) {
205
206 case FPC_ZERO:
207 return (0);
208
209 case FPC_NUM:
210 /*
211 * If exp >= 2^32, overflow. Otherwise shift value right
212 * into last mantissa word (this will not exceed 0xffffffff),
213 * shifting any guard and round bits out into the sticky
214 * bit. Then ``round'' towards zero, i.e., just set an
215 * inexact exception if sticky is set (see round()).
216 * If the result is > 0x80000000, or is positive and equals
217 * 0x80000000, overflow; otherwise the last fraction word
218 * is the result.
219 */
220 if ((exp = fp->fp_exp) >= 32)
221 break;
222 /* NB: the following includes exp < 0 cases */
223 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
224 fe->fe_cx |= FSR_NX;
225 i = fp->fp_mant[3];
226 if (i >= ((u_int)0x80000000 + sign))
227 break;
228 return (sign ? -i : i);
229
230 default: /* Inf, qNaN, sNaN */
231 break;
232 }
233 /* overflow: replace any inexact exception with invalid */
234 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
235 return (0x7fffffff + sign);
236}
237
238/*
239 * fpn -> extended int (high bits of int value returned as return value).
240 *
241 * N.B.: this conversion always rounds towards zero (this is a peculiarity
242 * of the SPARC instruction set).
243 */
244u_int
245__fpu_ftox(fe, fp, res)
246 struct fpemu *fe;
247 struct fpn *fp;
248 u_int *res;
249{
250 u_int64_t i;
251 int sign, exp;
252
253 sign = fp->fp_sign;
254 switch (fp->fp_class) {
255
256 case FPC_ZERO:
257 res[1] = 0;
258 return (0);
259
260 case FPC_NUM:
261 /*
262 * If exp >= 2^64, overflow. Otherwise shift value right
263 * into last mantissa word (this will not exceed 0xffffffffffffffff),
264 * shifting any guard and round bits out into the sticky
265 * bit. Then ``round'' towards zero, i.e., just set an
266 * inexact exception if sticky is set (see round()).
267 * If the result is > 0x8000000000000000, or is positive and equals
268 * 0x8000000000000000, overflow; otherwise the last fraction word
269 * is the result.
270 */
271 if ((exp = fp->fp_exp) >= 64)
272 break;
273 /* NB: the following includes exp < 0 cases */
274 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
275 fe->fe_cx |= FSR_NX;
276 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
277 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
278 break;
279 if (sign)
280 i = -1;
281 res[1] = (int)i;
282 return (i >> 32);
283
284 default: /* Inf, qNaN, sNaN */
285 break;
286 }
287 /* overflow: replace any inexact exception with invalid */
288 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
289 return (0x7fffffffffffffffLL + sign);
290}
291
292/*
293 * fpn -> single (32 bit single returned as return value).
294 * We assume <= 29 bits in a single-precision fraction (1.f part).
295 */
296u_int
297__fpu_ftos(fe, fp)
298 struct fpemu *fe;
299 struct fpn *fp;
300{
301 u_int sign = fp->fp_sign << 31;
302 int exp;
303
304#define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
305#define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
306
307 /* Take care of non-numbers first. */
308 if (ISNAN(fp)) {
309 /*
310 * Preserve upper bits of NaN, per SPARC V8 appendix N.
311 * Note that fp->fp_mant[0] has the quiet bit set,
312 * even if it is classified as a signalling NaN.
313 */
314 (void) __fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
315 exp = SNG_EXP_INFNAN;
316 goto done;
317 }
318 if (ISINF(fp))
319 return (sign | SNG_EXP(SNG_EXP_INFNAN));
320 if (ISZERO(fp))
321 return (sign);
322
323 /*
324 * Normals (including subnormals). Drop all the fraction bits
325 * (including the explicit ``implied'' 1 bit) down into the
326 * single-precision range. If the number is subnormal, move
327 * the ``implied'' 1 into the explicit range as well, and shift
328 * right to introduce leading zeroes. Rounding then acts
329 * differently for normals and subnormals: the largest subnormal
330 * may round to the smallest normal (1.0 x 2^minexp), or may
331 * remain subnormal. In the latter case, signal an underflow
332 * if the result was inexact or if underflow traps are enabled.
333 *
334 * Rounding a normal, on the other hand, always produces another
335 * normal (although either way the result might be too big for
336 * single precision, and cause an overflow). If rounding a
337 * normal produces 2.0 in the fraction, we need not adjust that
338 * fraction at all, since both 1.0 and 2.0 are zero under the
339 * fraction mask.
340 *
341 * Note that the guard and round bits vanish from the number after
342 * rounding.
343 */
344 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
345 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
346 (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
347 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
348 return (sign | SNG_EXP(1) | 0);
349 if ((fe->fe_cx & FSR_NX) ||
350 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
351 fe->fe_cx |= FSR_UF;
352 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
353 }
354 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
355 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
356#ifdef DIAGNOSTIC
357 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
|
357 __fpu_panic("fpu_ftos");
| 358 __utrap_panic("fpu_ftos");
|
358#endif
359 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
360 exp++;
361 if (exp >= SNG_EXP_INFNAN) {
362 /* overflow to inf or to max single */
363 fe->fe_cx |= FSR_OF | FSR_NX;
364 if (toinf(fe, sign))
365 return (sign | SNG_EXP(SNG_EXP_INFNAN));
366 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
367 }
368done:
369 /* phew, made it */
370 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
371}
372
373/*
374 * fpn -> double (32 bit high-order result returned; 32-bit low order result
375 * left in res[1]). Assumes <= 61 bits in double precision fraction.
376 *
377 * This code mimics fpu_ftos; see it for comments.
378 */
379u_int
380__fpu_ftod(fe, fp, res)
381 struct fpemu *fe;
382 struct fpn *fp;
383 u_int *res;
384{
385 u_int sign = fp->fp_sign << 31;
386 int exp;
387
388#define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
389#define DBL_MASK (DBL_EXP(1) - 1)
390
391 if (ISNAN(fp)) {
392 (void) __fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
393 exp = DBL_EXP_INFNAN;
394 goto done;
395 }
396 if (ISINF(fp)) {
397 sign |= DBL_EXP(DBL_EXP_INFNAN);
398 goto zero;
399 }
400 if (ISZERO(fp)) {
401zero: res[1] = 0;
402 return (sign);
403 }
404
405 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
406 (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
407 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
408 res[1] = 0;
409 return (sign | DBL_EXP(1) | 0);
410 }
411 if ((fe->fe_cx & FSR_NX) ||
412 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
413 fe->fe_cx |= FSR_UF;
414 exp = 0;
415 goto done;
416 }
417 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
418 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
419 exp++;
420 if (exp >= DBL_EXP_INFNAN) {
421 fe->fe_cx |= FSR_OF | FSR_NX;
422 if (toinf(fe, sign)) {
423 res[1] = 0;
424 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
425 }
426 res[1] = ~0;
427 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
428 }
429done:
430 res[1] = fp->fp_mant[3];
431 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
432}
433
434/*
435 * fpn -> extended (32 bit high-order result returned; low-order fraction
436 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but
437 * our internal format *is* extended precision, plus 2 bits for guard/round,
438 * so we can avoid a small bit of work.
439 */
440u_int
441__fpu_ftoq(fe, fp, res)
442 struct fpemu *fe;
443 struct fpn *fp;
444 u_int *res;
445{
446 u_int sign = fp->fp_sign << 31;
447 int exp;
448
449#define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31))
450#define EXT_MASK (EXT_EXP(1) - 1)
451
452 if (ISNAN(fp)) {
453 (void) __fpu_shr(fp, 2); /* since we are not rounding */
454 exp = EXT_EXP_INFNAN;
455 goto done;
456 }
457 if (ISINF(fp)) {
458 sign |= EXT_EXP(EXT_EXP_INFNAN);
459 goto zero;
460 }
461 if (ISZERO(fp)) {
462zero: res[1] = res[2] = res[3] = 0;
463 return (sign);
464 }
465
466 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) {
467 (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp);
468 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) {
469 res[1] = res[2] = res[3] = 0;
470 return (sign | EXT_EXP(1) | 0);
471 }
472 if ((fe->fe_cx & FSR_NX) ||
473 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
474 fe->fe_cx |= FSR_UF;
475 exp = 0;
476 goto done;
477 }
478 /* Since internal == extended, no need to shift here. */
479 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2))
480 exp++;
481 if (exp >= EXT_EXP_INFNAN) {
482 fe->fe_cx |= FSR_OF | FSR_NX;
483 if (toinf(fe, sign)) {
484 res[1] = res[2] = res[3] = 0;
485 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0);
486 }
487 res[1] = res[2] = res[3] = ~0;
488 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK);
489 }
490done:
491 res[1] = fp->fp_mant[1];
492 res[2] = fp->fp_mant[2];
493 res[3] = fp->fp_mant[3];
494 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK));
495}
496
497/*
498 * Implode an fpn, writing the result into the given space.
499 */
500void
501__fpu_implode(fe, fp, type, space)
502 struct fpemu *fe;
503 struct fpn *fp;
504 int type;
505 u_int *space;
506{
507
508 switch (type) {
509
510 case FTYPE_LNG:
511 space[0] = __fpu_ftox(fe, fp, space);
512 break;
513
514 case FTYPE_INT:
515 space[0] = __fpu_ftoi(fe, fp);
516 break;
517
518 case FTYPE_SNG:
519 space[0] = __fpu_ftos(fe, fp);
520 break;
521
522 case FTYPE_DBL:
523 space[0] = __fpu_ftod(fe, fp, space);
524 break;
525
526 case FTYPE_EXT:
527 /* funky rounding precision options ?? */
528 space[0] = __fpu_ftoq(fe, fp, space);
529 break;
530
531 default:
| 359#endif
360 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
361 exp++;
362 if (exp >= SNG_EXP_INFNAN) {
363 /* overflow to inf or to max single */
364 fe->fe_cx |= FSR_OF | FSR_NX;
365 if (toinf(fe, sign))
366 return (sign | SNG_EXP(SNG_EXP_INFNAN));
367 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
368 }
369done:
370 /* phew, made it */
371 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
372}
373
374/*
375 * fpn -> double (32 bit high-order result returned; 32-bit low order result
376 * left in res[1]). Assumes <= 61 bits in double precision fraction.
377 *
378 * This code mimics fpu_ftos; see it for comments.
379 */
380u_int
381__fpu_ftod(fe, fp, res)
382 struct fpemu *fe;
383 struct fpn *fp;
384 u_int *res;
385{
386 u_int sign = fp->fp_sign << 31;
387 int exp;
388
389#define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
390#define DBL_MASK (DBL_EXP(1) - 1)
391
392 if (ISNAN(fp)) {
393 (void) __fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
394 exp = DBL_EXP_INFNAN;
395 goto done;
396 }
397 if (ISINF(fp)) {
398 sign |= DBL_EXP(DBL_EXP_INFNAN);
399 goto zero;
400 }
401 if (ISZERO(fp)) {
402zero: res[1] = 0;
403 return (sign);
404 }
405
406 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
407 (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
408 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
409 res[1] = 0;
410 return (sign | DBL_EXP(1) | 0);
411 }
412 if ((fe->fe_cx & FSR_NX) ||
413 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
414 fe->fe_cx |= FSR_UF;
415 exp = 0;
416 goto done;
417 }
418 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
419 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
420 exp++;
421 if (exp >= DBL_EXP_INFNAN) {
422 fe->fe_cx |= FSR_OF | FSR_NX;
423 if (toinf(fe, sign)) {
424 res[1] = 0;
425 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
426 }
427 res[1] = ~0;
428 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
429 }
430done:
431 res[1] = fp->fp_mant[3];
432 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
433}
434
435/*
436 * fpn -> extended (32 bit high-order result returned; low-order fraction
437 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but
438 * our internal format *is* extended precision, plus 2 bits for guard/round,
439 * so we can avoid a small bit of work.
440 */
441u_int
442__fpu_ftoq(fe, fp, res)
443 struct fpemu *fe;
444 struct fpn *fp;
445 u_int *res;
446{
447 u_int sign = fp->fp_sign << 31;
448 int exp;
449
450#define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31))
451#define EXT_MASK (EXT_EXP(1) - 1)
452
453 if (ISNAN(fp)) {
454 (void) __fpu_shr(fp, 2); /* since we are not rounding */
455 exp = EXT_EXP_INFNAN;
456 goto done;
457 }
458 if (ISINF(fp)) {
459 sign |= EXT_EXP(EXT_EXP_INFNAN);
460 goto zero;
461 }
462 if (ISZERO(fp)) {
463zero: res[1] = res[2] = res[3] = 0;
464 return (sign);
465 }
466
467 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) {
468 (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp);
469 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) {
470 res[1] = res[2] = res[3] = 0;
471 return (sign | EXT_EXP(1) | 0);
472 }
473 if ((fe->fe_cx & FSR_NX) ||
474 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
475 fe->fe_cx |= FSR_UF;
476 exp = 0;
477 goto done;
478 }
479 /* Since internal == extended, no need to shift here. */
480 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2))
481 exp++;
482 if (exp >= EXT_EXP_INFNAN) {
483 fe->fe_cx |= FSR_OF | FSR_NX;
484 if (toinf(fe, sign)) {
485 res[1] = res[2] = res[3] = 0;
486 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0);
487 }
488 res[1] = res[2] = res[3] = ~0;
489 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK);
490 }
491done:
492 res[1] = fp->fp_mant[1];
493 res[2] = fp->fp_mant[2];
494 res[3] = fp->fp_mant[3];
495 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK));
496}
497
498/*
499 * Implode an fpn, writing the result into the given space.
500 */
501void
502__fpu_implode(fe, fp, type, space)
503 struct fpemu *fe;
504 struct fpn *fp;
505 int type;
506 u_int *space;
507{
508
509 switch (type) {
510
511 case FTYPE_LNG:
512 space[0] = __fpu_ftox(fe, fp, space);
513 break;
514
515 case FTYPE_INT:
516 space[0] = __fpu_ftoi(fe, fp);
517 break;
518
519 case FTYPE_SNG:
520 space[0] = __fpu_ftos(fe, fp);
521 break;
522
523 case FTYPE_DBL:
524 space[0] = __fpu_ftod(fe, fp, space);
525 break;
526
527 case FTYPE_EXT:
528 /* funky rounding precision options ?? */
529 space[0] = __fpu_ftoq(fe, fp, space);
530 break;
531
532 default:
|
532 __fpu_panic("fpu_implode");
| 533 __utrap_panic("fpu_implode");
|
533 }
534 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n",
535 space[0], space[1], space[2], space[3]));
536}
| 534 }
535 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n",
536 space[0], space[1], space[2], space[3]));
537}
|