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t4.h (273806) t4.h (297124)
1/*
2 * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:

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323
324struct t4_sq {
325 union t4_wr *queue;
326 struct t4_swsqe *sw_sq;
327 struct t4_swsqe *oldest_read;
328 volatile u32 *udb;
329 size_t memsize;
330 u32 qid;
1/*
2 * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:

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323
324struct t4_sq {
325 union t4_wr *queue;
326 struct t4_swsqe *sw_sq;
327 struct t4_swsqe *oldest_read;
328 volatile u32 *udb;
329 size_t memsize;
330 u32 qid;
331 u32 bar2_qid;
331 void *ma_sync;
332 u16 in_use;
333 u16 size;
334 u16 cidx;
335 u16 pidx;
336 u16 wq_pidx;
337 u16 flags;
338 short flush_cidx;
332 void *ma_sync;
333 u16 in_use;
334 u16 size;
335 u16 cidx;
336 u16 pidx;
337 u16 wq_pidx;
338 u16 flags;
339 short flush_cidx;
340 int wc_reg_available;
339};
340
341struct t4_swrqe {
342 u64 wr_id;
343};
344
345struct t4_rq {
346 union t4_recv_wr *queue;
347 struct t4_swrqe *sw_rq;
348 volatile u32 *udb;
349 size_t memsize;
350 u32 qid;
341};
342
343struct t4_swrqe {
344 u64 wr_id;
345};
346
347struct t4_rq {
348 union t4_recv_wr *queue;
349 struct t4_swrqe *sw_rq;
350 volatile u32 *udb;
351 size_t memsize;
352 u32 qid;
353 u32 bar2_qid;
351 u32 msn;
352 u32 rqt_hwaddr;
353 u16 rqt_size;
354 u16 in_use;
355 u16 size;
356 u16 cidx;
357 u16 pidx;
358 u16 wq_pidx;
354 u32 msn;
355 u32 rqt_hwaddr;
356 u16 rqt_size;
357 u16 in_use;
358 u16 size;
359 u16 cidx;
360 u16 pidx;
361 u16 wq_pidx;
362 int wc_reg_available;
359};
360
361struct t4_wq {
362 struct t4_sq sq;
363 struct t4_rq rq;
364 struct c4iw_rdev *rdev;
365 u32 qid_mask;
366 int error;

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480extern int ma_wr;
481extern int t5_en_wc;
482
483static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
484 union t4_wr *wqe)
485{
486 wc_wmb();
487 if (t5) {
363};
364
365struct t4_wq {
366 struct t4_sq sq;
367 struct t4_rq rq;
368 struct c4iw_rdev *rdev;
369 u32 qid_mask;
370 int error;

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484extern int ma_wr;
485extern int t5_en_wc;
486
487static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
488 union t4_wr *wqe)
489{
490 wc_wmb();
491 if (t5) {
488 if (t5_en_wc && inc == 1) {
492 if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
489 PDBG("%s: WC wq->sq.pidx = %d; len16=%d\n",
490 __func__, wq->sq.pidx, len16);
491 copy_wqe_to_udb(wq->sq.udb + 14, wqe);
492 } else {
493 PDBG("%s: DB wq->sq.pidx = %d; len16=%d\n",
494 __func__, wq->sq.pidx, len16);
493 PDBG("%s: WC wq->sq.pidx = %d; len16=%d\n",
494 __func__, wq->sq.pidx, len16);
495 copy_wqe_to_udb(wq->sq.udb + 14, wqe);
496 } else {
497 PDBG("%s: DB wq->sq.pidx = %d; len16=%d\n",
498 __func__, wq->sq.pidx, len16);
495 writel(V_PIDX_T5(inc), wq->sq.udb);
499 writel(V_QID(wq->sq.bar2_qid) | V_PIDX_T5(inc), wq->sq.udb);
496 }
497 wc_wmb();
498 return;
499 }
500 if (ma_wr) {
501 if (t4_sq_onchip(wq)) {
502 int i;
503 for (i = 0; i < 16; i++)

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513 writel(V_QID(wq->sq.qid & wq->qid_mask) | V_PIDX(inc), wq->sq.udb);
514}
515
516static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
517 union t4_recv_wr *wqe)
518{
519 wc_wmb();
520 if (t5) {
500 }
501 wc_wmb();
502 return;
503 }
504 if (ma_wr) {
505 if (t4_sq_onchip(wq)) {
506 int i;
507 for (i = 0; i < 16; i++)

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517 writel(V_QID(wq->sq.qid & wq->qid_mask) | V_PIDX(inc), wq->sq.udb);
518}
519
520static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
521 union t4_recv_wr *wqe)
522{
523 wc_wmb();
524 if (t5) {
521 if (t5_en_wc && inc == 1) {
525 if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
522 PDBG("%s: WC wq->rq.pidx = %d; len16=%d\n",
523 __func__, wq->rq.pidx, len16);
524 copy_wqe_to_udb(wq->rq.udb + 14, wqe);
525 } else {
526 PDBG("%s: DB wq->rq.pidx = %d; len16=%d\n",
527 __func__, wq->rq.pidx, len16);
526 PDBG("%s: WC wq->rq.pidx = %d; len16=%d\n",
527 __func__, wq->rq.pidx, len16);
528 copy_wqe_to_udb(wq->rq.udb + 14, wqe);
529 } else {
530 PDBG("%s: DB wq->rq.pidx = %d; len16=%d\n",
531 __func__, wq->rq.pidx, len16);
528 writel(V_PIDX_T5(inc), wq->rq.udb);
532 writel(V_QID(wq->rq.bar2_qid) | V_PIDX_T5(inc), wq->rq.udb);
529 }
530 wc_wmb();
531 return;
532 }
533 writel(V_QID(wq->rq.qid & wq->qid_mask) | V_PIDX(inc), wq->rq.udb);
534}
535
536static inline int t4_wq_in_error(struct t4_wq *wq)

--- 179 unchanged lines hidden --- 		533 }
534 wc_wmb();
535 return;
536 }
537 writel(V_QID(wq->rq.qid & wq->qid_mask) | V_PIDX(inc), wq->rq.udb);
538}
539
540static inline int t4_wq_in_error(struct t4_wq *wq)

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