DisassemblerEmitter.cpp (208954) | DisassemblerEmitter.cpp (218893) |
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1//===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "DisassemblerEmitter.h" 11#include "CodeGenTarget.h" 12#include "Record.h" 13#include "X86DisassemblerTables.h" 14#include "X86RecognizableInstr.h" 15#include "ARMDecoderEmitter.h" | 1//===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "DisassemblerEmitter.h" 11#include "CodeGenTarget.h" 12#include "Record.h" 13#include "X86DisassemblerTables.h" 14#include "X86RecognizableInstr.h" 15#include "ARMDecoderEmitter.h" |
16#include "FixedLenDecoderEmitter.h" |
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16 17using namespace llvm; 18using namespace llvm::X86Disassembler; 19 20/// DisassemblerEmitter - Contains disassembler table emitters for various 21/// architectures. 22 23/// X86 Disassembler Emitter --- 65 unchanged lines hidden (view full) --- 89/// populate ModRMDecisions. 90/// X86RecognizableInstr.h contains the interface for a single instruction, 91/// which knows how to translate itself from a CodeGenInstruction and provide 92/// the information necessary for integration into the tables. 93/// X86RecognizableInstr.cpp contains the implementation for a single 94/// instruction. 95 96void DisassemblerEmitter::run(raw_ostream &OS) { | 17 18using namespace llvm; 19using namespace llvm::X86Disassembler; 20 21/// DisassemblerEmitter - Contains disassembler table emitters for various 22/// architectures. 23 24/// X86 Disassembler Emitter --- 65 unchanged lines hidden (view full) --- 90/// populate ModRMDecisions. 91/// X86RecognizableInstr.h contains the interface for a single instruction, 92/// which knows how to translate itself from a CodeGenInstruction and provide 93/// the information necessary for integration into the tables. 94/// X86RecognizableInstr.cpp contains the implementation for a single 95/// instruction. 96 97void DisassemblerEmitter::run(raw_ostream &OS) { |
97 CodeGenTarget Target; | 98 CodeGenTarget Target(Records); |
98 99 OS << "/*===- TableGen'erated file " 100 << "---------------------------------------*- C -*-===*\n" 101 << " *\n" 102 << " * " << Target.getName() << " Disassembler\n" 103 << " *\n" 104 << " * Automatically generated file, do not edit!\n" 105 << " *\n" --- 16 unchanged lines hidden (view full) --- 122 throw TGError(Target.getTargetRecord()->getLoc(), 123 "Primary decode conflict"); 124 125 Tables.emit(OS); 126 return; 127 } 128 129 // Fixed-instruction-length targets use a common disassembler. | 99 100 OS << "/*===- TableGen'erated file " 101 << "---------------------------------------*- C -*-===*\n" 102 << " *\n" 103 << " * " << Target.getName() << " Disassembler\n" 104 << " *\n" 105 << " * Automatically generated file, do not edit!\n" 106 << " *\n" --- 16 unchanged lines hidden (view full) --- 123 throw TGError(Target.getTargetRecord()->getLoc(), 124 "Primary decode conflict"); 125 126 Tables.emit(OS); 127 return; 128 } 129 130 // Fixed-instruction-length targets use a common disassembler. |
131 // ARM use its own implementation for now. |
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130 if (Target.getName() == "ARM") { 131 ARMDecoderEmitter(Records).run(OS); 132 return; 133 } 134 | 132 if (Target.getName() == "ARM") { 133 ARMDecoderEmitter(Records).run(OS); 134 return; 135 } 136 |
135 throw TGError(Target.getTargetRecord()->getLoc(), 136 "Unable to generate disassembler for this target"); | 137 FixedLenDecoderEmitter(Records).run(OS); |
137} | 138} |