1//===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "DisassemblerEmitter.h"
11#include "CodeGenTarget.h"
12#include "Record.h"
13#include "X86DisassemblerTables.h"
14#include "X86RecognizableInstr.h"
15#include "ARMDecoderEmitter.h"
16
17using namespace llvm;
18using namespace llvm::X86Disassembler;
19
20/// DisassemblerEmitter - Contains disassembler table emitters for various
21/// architectures.
22
23/// X86 Disassembler Emitter

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89/// populate ModRMDecisions.
90/// X86RecognizableInstr.h contains the interface for a single instruction,
91/// which knows how to translate itself from a CodeGenInstruction and provide
92/// the information necessary for integration into the tables.
93/// X86RecognizableInstr.cpp contains the implementation for a single
94/// instruction.
95
96void DisassemblerEmitter::run(raw_ostream &OS) {
97 CodeGenTarget Target;
98
99 OS << "/*===- TableGen'erated file "
100 << "---------------------------------------*- C -*-===*\n"
101 << " *\n"
102 << " * " << Target.getName() << " Disassembler\n"
103 << " *\n"
104 << " * Automatically generated file, do not edit!\n"
105 << " *\n"

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122 throw TGError(Target.getTargetRecord()->getLoc(),
123 "Primary decode conflict");
124
125 Tables.emit(OS);
126 return;
127 }
128
129 // Fixed-instruction-length targets use a common disassembler.
130 if (Target.getName() == "ARM") {
131 ARMDecoderEmitter(Records).run(OS);
132 return;
133 }
134
135 throw TGError(Target.getTargetRecord()->getLoc(),
136 "Unable to generate disassembler for this target");
137}